Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 43
- Kernel Errors: 54
- Boot result: PASS
- Errors: 0
- Warnings: 1
1 17:16:00.202555 lava-dispatcher, installed at version: 2022.10
2 17:16:00.202737 start: 0 validate
3 17:16:00.202873 Start time: 2022-11-22 17:16:00.202862+00:00 (UTC)
4 17:16:00.203002 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:16:00.203130 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20221116.0%2Farm64%2Finitrd.cpio.gz exists
6 17:16:00.206147 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:16:00.206267 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.staging.kernelci.org%2Fkernelci%2Fstaging-mainline%2Fstaging-mainline-20221122.0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:16:00.207704 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:16:00.207839 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.staging.kernelci.org%2Fkernelci%2Fstaging-mainline%2Fstaging-mainline-20221122.0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:16:00.209166 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:16:00.209291 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fdebian%2Fbullseye%2F20221116.0%2Farm64%2Ffull.rootfs.tar.xz exists
12 17:16:00.210692 Using caching service: 'http://localhost/cache/?uri=%s'
13 17:16:00.210812 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.staging.kernelci.org%2Fkernelci%2Fstaging-mainline%2Fstaging-mainline-20221122.0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
14 17:16:00.213785 validate duration: 0.01
16 17:16:00.214015 start: 1 tftp-deploy (timeout 00:10:00) [common]
17 17:16:00.214138 start: 1.1 download-retry (timeout 00:10:00) [common]
18 17:16:00.214244 start: 1.1.1 http-download (timeout 00:10:00) [common]
19 17:16:00.214345 Not decompressing ramdisk as can be used compressed.
20 17:16:00.214425 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20221116.0/arm64/initrd.cpio.gz
21 17:16:00.214489 saving as /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/ramdisk/initrd.cpio.gz
22 17:16:00.214551 total size: 4662417 (4MB)
23 17:16:00.217272 progress 0% (0MB)
24 17:16:00.224863 progress 5% (0MB)
25 17:16:00.230802 progress 10% (0MB)
26 17:16:00.234397 progress 15% (0MB)
27 17:16:00.236944 progress 20% (0MB)
28 17:16:00.240784 progress 25% (1MB)
29 17:16:00.246343 progress 30% (1MB)
30 17:16:00.250729 progress 35% (1MB)
31 17:16:00.255584 progress 40% (1MB)
32 17:16:00.260951 progress 45% (2MB)
33 17:16:00.264399 progress 50% (2MB)
34 17:16:00.269736 progress 55% (2MB)
35 17:16:00.273528 progress 60% (2MB)
36 17:16:00.277949 progress 65% (2MB)
37 17:16:00.281776 progress 70% (3MB)
38 17:16:00.286754 progress 75% (3MB)
39 17:16:00.290596 progress 80% (3MB)
40 17:16:00.295069 progress 85% (3MB)
41 17:16:00.299687 progress 90% (4MB)
42 17:16:00.302520 progress 95% (4MB)
43 17:16:00.306202 progress 100% (4MB)
44 17:16:00.306407 4MB downloaded in 0.09s (48.41MB/s)
45 17:16:00.306599 end: 1.1.1 http-download (duration 00:00:00) [common]
47 17:16:00.306935 end: 1.1 download-retry (duration 00:00:00) [common]
48 17:16:00.307029 start: 1.2 download-retry (timeout 00:10:00) [common]
49 17:16:00.307117 start: 1.2.1 http-download (timeout 00:10:00) [common]
50 17:16:00.307222 downloading http://storage.staging.kernelci.org/kernelci/staging-mainline/staging-mainline-20221122.0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
51 17:16:00.307290 saving as /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/kernel/Image
52 17:16:00.307352 total size: 37693952 (35MB)
53 17:16:00.307412 No compression specified
54 17:16:00.309560 progress 0% (0MB)
55 17:16:00.340969 progress 5% (1MB)
56 17:16:00.377988 progress 10% (3MB)
57 17:16:00.411055 progress 15% (5MB)
58 17:16:00.435243 progress 20% (7MB)
59 17:16:00.471368 progress 25% (9MB)
60 17:16:00.505401 progress 30% (10MB)
61 17:16:00.536887 progress 35% (12MB)
62 17:16:00.573336 progress 40% (14MB)
63 17:16:00.606659 progress 45% (16MB)
64 17:16:00.642076 progress 50% (18MB)
65 17:16:00.675429 progress 55% (19MB)
66 17:16:00.709266 progress 60% (21MB)
67 17:16:00.743718 progress 65% (23MB)
68 17:16:00.779225 progress 70% (25MB)
69 17:16:00.811081 progress 75% (26MB)
70 17:16:00.846793 progress 80% (28MB)
71 17:16:00.881492 progress 85% (30MB)
72 17:16:00.914526 progress 90% (32MB)
73 17:16:00.948893 progress 95% (34MB)
74 17:16:00.983336 progress 100% (35MB)
75 17:16:00.983600 35MB downloaded in 0.68s (53.16MB/s)
76 17:16:00.983763 end: 1.2.1 http-download (duration 00:00:01) [common]
78 17:16:00.984012 end: 1.2 download-retry (duration 00:00:01) [common]
79 17:16:00.984144 start: 1.3 download-retry (timeout 00:09:59) [common]
80 17:16:00.984237 start: 1.3.1 http-download (timeout 00:09:59) [common]
81 17:16:00.984342 downloading http://storage.staging.kernelci.org/kernelci/staging-mainline/staging-mainline-20221122.0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
82 17:16:00.984419 saving as /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/dtb/mt8192-asurada-spherion-r0.dtb
83 17:16:00.984483 total size: 46773 (0MB)
84 17:16:00.984545 No compression specified
85 17:16:00.990481 progress 70% (0MB)
86 17:16:00.991249 progress 100% (0MB)
87 17:16:00.991452 0MB downloaded in 0.01s (6.40MB/s)
88 17:16:00.991585 end: 1.3.1 http-download (duration 00:00:00) [common]
90 17:16:00.991828 end: 1.3 download-retry (duration 00:00:00) [common]
91 17:16:00.991927 start: 1.4 download-retry (timeout 00:09:59) [common]
92 17:16:00.992016 start: 1.4.1 http-download (timeout 00:09:59) [common]
93 17:16:00.992110 downloading http://storage.kernelci.org/images/rootfs/debian/bullseye/20221116.0/arm64/full.rootfs.tar.xz
94 17:16:00.992178 saving as /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/nfsrootfs/full.rootfs.tar
95 17:16:00.992248 total size: 125150152 (119MB)
96 17:16:00.992312 Using unxz to decompress xz
97 17:16:00.998108 progress 0% (0MB)
98 17:16:01.324687 progress 5% (5MB)
99 17:16:01.670858 progress 10% (11MB)
100 17:16:01.994917 progress 15% (17MB)
101 17:16:02.202354 progress 20% (23MB)
102 17:16:02.380243 progress 25% (29MB)
103 17:16:02.727609 progress 30% (35MB)
104 17:16:03.077279 progress 35% (41MB)
105 17:16:03.461279 progress 40% (47MB)
106 17:16:03.833291 progress 45% (53MB)
107 17:16:04.216417 progress 50% (59MB)
108 17:16:04.570169 progress 55% (65MB)
109 17:16:04.931146 progress 60% (71MB)
110 17:16:05.273453 progress 65% (77MB)
111 17:16:05.625782 progress 70% (83MB)
112 17:16:05.990508 progress 75% (89MB)
113 17:16:06.397522 progress 80% (95MB)
114 17:16:06.804609 progress 85% (101MB)
115 17:16:07.039332 progress 90% (107MB)
116 17:16:07.365232 progress 95% (113MB)
117 17:16:07.731222 progress 100% (119MB)
118 17:16:07.736343 119MB downloaded in 6.74s (17.70MB/s)
119 17:16:07.736620 end: 1.4.1 http-download (duration 00:00:07) [common]
121 17:16:07.736893 end: 1.4 download-retry (duration 00:00:07) [common]
122 17:16:07.736990 start: 1.5 download-retry (timeout 00:09:52) [common]
123 17:16:07.737082 start: 1.5.1 http-download (timeout 00:09:52) [common]
124 17:16:07.737197 downloading http://storage.staging.kernelci.org/kernelci/staging-mainline/staging-mainline-20221122.0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
125 17:16:07.737269 saving as /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/modules/modules.tar
126 17:16:07.737376 total size: 9185096 (8MB)
127 17:16:07.737444 Using unxz to decompress xz
128 17:16:07.744859 progress 0% (0MB)
129 17:16:07.774386 progress 5% (0MB)
130 17:16:07.796973 progress 10% (0MB)
131 17:16:07.823497 progress 15% (1MB)
132 17:16:07.849918 progress 20% (1MB)
133 17:16:07.876787 progress 25% (2MB)
134 17:16:07.903506 progress 30% (2MB)
135 17:16:07.929309 progress 35% (3MB)
136 17:16:07.955703 progress 40% (3MB)
137 17:16:07.980404 progress 45% (3MB)
138 17:16:08.008147 progress 50% (4MB)
139 17:16:08.034443 progress 55% (4MB)
140 17:16:08.059727 progress 60% (5MB)
141 17:16:08.085567 progress 65% (5MB)
142 17:16:08.111030 progress 70% (6MB)
143 17:16:08.135856 progress 75% (6MB)
144 17:16:08.163614 progress 80% (7MB)
145 17:16:08.194261 progress 85% (7MB)
146 17:16:08.220222 progress 90% (7MB)
147 17:16:08.245260 progress 95% (8MB)
148 17:16:08.269897 progress 100% (8MB)
149 17:16:08.275101 8MB downloaded in 0.54s (16.29MB/s)
150 17:16:08.275354 end: 1.5.1 http-download (duration 00:00:01) [common]
152 17:16:08.275627 end: 1.5 download-retry (duration 00:00:01) [common]
153 17:16:08.275725 start: 1.6 prepare-tftp-overlay (timeout 00:09:52) [common]
154 17:16:08.275824 start: 1.6.1 extract-nfsrootfs (timeout 00:09:52) [common]
155 17:16:09.498639 Extracted nfsroot to /var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep
156 17:16:09.498842 end: 1.6.1 extract-nfsrootfs (duration 00:00:01) [common]
157 17:16:09.498947 start: 1.6.2 lava-overlay (timeout 00:09:51) [common]
158 17:16:09.499086 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l
159 17:16:09.499189 makedir: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin
160 17:16:09.499276 makedir: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/tests
161 17:16:09.499360 makedir: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/results
162 17:16:09.499458 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-add-keys
163 17:16:09.499588 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-add-sources
164 17:16:09.499705 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-background-process-start
165 17:16:09.499819 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-background-process-stop
166 17:16:09.499932 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-common-functions
167 17:16:09.500048 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-echo-ipv4
168 17:16:09.500162 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-install-packages
169 17:16:09.500274 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-installed-packages
170 17:16:09.500384 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-os-build
171 17:16:09.500495 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-probe-channel
172 17:16:09.500606 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-probe-ip
173 17:16:09.500723 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-target-ip
174 17:16:09.500832 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-target-mac
175 17:16:09.500942 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-target-storage
176 17:16:09.501056 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-case
177 17:16:09.501169 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-event
178 17:16:09.501280 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-feedback
179 17:16:09.501437 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-raise
180 17:16:09.501548 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-reference
181 17:16:09.501659 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-runner
182 17:16:09.501770 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-set
183 17:16:09.501879 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-test-shell
184 17:16:09.501990 Updating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-install-packages (oe)
185 17:16:09.502104 Updating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/bin/lava-installed-packages (oe)
186 17:16:09.502203 Creating /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/environment
187 17:16:09.502289 LAVA metadata
188 17:16:09.502358 - LAVA_JOB_ID=8082983
189 17:16:09.502423 - LAVA_DISPATCHER_IP=192.168.201.1
190 17:16:09.502521 start: 1.6.2.1 lava-vland-overlay (timeout 00:09:51) [common]
191 17:16:09.502588 skipped lava-vland-overlay
192 17:16:09.502667 end: 1.6.2.1 lava-vland-overlay (duration 00:00:00) [common]
193 17:16:09.502751 start: 1.6.2.2 lava-multinode-overlay (timeout 00:09:51) [common]
194 17:16:09.502815 skipped lava-multinode-overlay
195 17:16:09.502892 end: 1.6.2.2 lava-multinode-overlay (duration 00:00:00) [common]
196 17:16:09.502975 start: 1.6.2.3 test-definition (timeout 00:09:51) [common]
197 17:16:09.503048 Loading test definitions
198 17:16:09.503142 start: 1.6.2.3.1 inline-repo-action (timeout 00:09:51) [common]
199 17:16:09.503215 Using /lava-8082983 at stage 0
200 17:16:09.503476 uuid=8082983_1.6.2.3.1 testdef=None
201 17:16:09.503568 end: 1.6.2.3.1 inline-repo-action (duration 00:00:00) [common]
202 17:16:09.503657 start: 1.6.2.3.2 test-overlay (timeout 00:09:51) [common]
203 17:16:09.504161 end: 1.6.2.3.2 test-overlay (duration 00:00:00) [common]
205 17:16:09.504397 start: 1.6.2.3.3 test-install-overlay (timeout 00:09:51) [common]
206 17:16:09.504970 end: 1.6.2.3.3 test-install-overlay (duration 00:00:00) [common]
208 17:16:09.505216 start: 1.6.2.3.4 test-runscript-overlay (timeout 00:09:51) [common]
209 17:16:09.505800 runner path: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/0/tests/0_dmesg test_uuid 8082983_1.6.2.3.1
210 17:16:09.505949 end: 1.6.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
212 17:16:09.506188 start: 1.6.2.3.5 inline-repo-action (timeout 00:09:51) [common]
213 17:16:09.506263 Using /lava-8082983 at stage 1
214 17:16:09.506504 uuid=8082983_1.6.2.3.5 testdef=None
215 17:16:09.506596 end: 1.6.2.3.5 inline-repo-action (duration 00:00:00) [common]
216 17:16:09.506685 start: 1.6.2.3.6 test-overlay (timeout 00:09:51) [common]
217 17:16:09.507126 end: 1.6.2.3.6 test-overlay (duration 00:00:00) [common]
219 17:16:09.507357 start: 1.6.2.3.7 test-install-overlay (timeout 00:09:51) [common]
220 17:16:09.507929 end: 1.6.2.3.7 test-install-overlay (duration 00:00:00) [common]
222 17:16:09.508171 start: 1.6.2.3.8 test-runscript-overlay (timeout 00:09:51) [common]
223 17:16:09.508718 runner path: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/1/tests/1_bootrr test_uuid 8082983_1.6.2.3.5
224 17:16:09.508862 end: 1.6.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
226 17:16:09.509076 Creating lava-test-runner.conf files
227 17:16:09.509143 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/0 for stage 0
228 17:16:09.509226 - 0_dmesg
229 17:16:09.509301 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8082983/lava-overlay-d1o4f66l/lava-8082983/1 for stage 1
230 17:16:09.509485 - 1_bootrr
231 17:16:09.509580 end: 1.6.2.3 test-definition (duration 00:00:00) [common]
232 17:16:09.509668 start: 1.6.2.4 compress-overlay (timeout 00:09:51) [common]
233 17:16:09.515160 end: 1.6.2.4 compress-overlay (duration 00:00:00) [common]
234 17:16:09.515269 start: 1.6.2.5 persistent-nfs-overlay (timeout 00:09:51) [common]
235 17:16:09.515362 end: 1.6.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
236 17:16:09.515452 end: 1.6.2 lava-overlay (duration 00:00:00) [common]
237 17:16:09.515541 start: 1.6.3 extract-overlay-ramdisk (timeout 00:09:51) [common]
238 17:16:09.605048 end: 1.6.3 extract-overlay-ramdisk (duration 00:00:00) [common]
239 17:16:09.605423 start: 1.6.4 extract-modules (timeout 00:09:51) [common]
240 17:16:09.605535 extracting modules file /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep
241 17:16:09.725537 extracting modules file /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8082983/extract-overlay-ramdisk-daqfxa4q/ramdisk
242 17:16:09.843501 end: 1.6.4 extract-modules (duration 00:00:00) [common]
243 17:16:09.843674 start: 1.6.5 apply-overlay-tftp (timeout 00:09:50) [common]
244 17:16:09.843773 [common] Applying overlay to NFS
245 17:16:09.843847 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8082983/compress-overlay-uj8g07cf/overlay-1.6.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep
246 17:16:09.847618 end: 1.6.5 apply-overlay-tftp (duration 00:00:00) [common]
247 17:16:09.847728 start: 1.6.6 configure-preseed-file (timeout 00:09:50) [common]
248 17:16:09.847824 end: 1.6.6 configure-preseed-file (duration 00:00:00) [common]
249 17:16:09.847917 start: 1.6.7 compress-ramdisk (timeout 00:09:50) [common]
250 17:16:09.847999 Building ramdisk /var/lib/lava/dispatcher/tmp/8082983/extract-overlay-ramdisk-daqfxa4q/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8082983/extract-overlay-ramdisk-daqfxa4q/ramdisk
251 17:16:10.003532 >> 125332 blocks
252 17:16:11.851388 rename /var/lib/lava/dispatcher/tmp/8082983/extract-overlay-ramdisk-daqfxa4q/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/ramdisk/ramdisk.cpio.gz
253 17:16:11.851791 end: 1.6.7 compress-ramdisk (duration 00:00:02) [common]
254 17:16:11.851917 start: 1.6.8 prepare-kernel (timeout 00:09:48) [common]
255 17:16:11.852018 start: 1.6.8.1 prepare-fit (timeout 00:09:48) [common]
256 17:16:11.852118 Calling: 'nice' 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/kernel/Image'
257 17:16:22.560469 Returned 0 in 10 seconds
258 17:16:22.661455 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/kernel/image.itb
259 17:16:22.695340 output: FIT description: Kernel Image image with one or more FDT blobs
260 17:16:22.695661 output: Created: Tue Nov 22 17:16:22 2022
261 17:16:22.695748 output: Image 0 (kernel-1)
262 17:16:22.695816 output: Description:
263 17:16:22.695881 output: Created: Tue Nov 22 17:16:22 2022
264 17:16:22.695945 output: Type: Kernel Image
265 17:16:22.696026 output: Compression: lzma compressed
266 17:16:22.696089 output: Data Size: 9039409 Bytes = 8827.55 KiB = 8.62 MiB
267 17:16:22.696148 output: Architecture: AArch64
268 17:16:22.696211 output: OS: Linux
269 17:16:22.696287 output: Load Address: 0x00000000
270 17:16:22.696366 output: Entry Point: 0x00000000
271 17:16:22.696424 output: Image 1 (fdt-1)
272 17:16:22.696481 output: Description: mt8192-asurada-spherion-r0
273 17:16:22.696537 output: Created: Tue Nov 22 17:16:22 2022
274 17:16:22.696593 output: Type: Kernel Image
275 17:16:22.696650 output: Compression: uncompressed
276 17:16:22.696706 output: Data Size: 46773 Bytes = 45.68 KiB = 0.04 MiB
277 17:16:22.696763 output: Architecture: AArch64
278 17:16:22.696819 output: OS: Unknown OS
279 17:16:22.696875 output: Load Address: unavailable
280 17:16:22.696930 output: Entry Point: unavailable
281 17:16:22.696985 output: Image 2 (ramdisk-1)
282 17:16:22.697040 output: Description: unavailable
283 17:16:22.697095 output: Created: Tue Nov 22 17:16:22 2022
284 17:16:22.697151 output: Type: RAMDisk Image
285 17:16:22.697206 output: Compression: Unknown Compression
286 17:16:22.697262 output: Data Size: 18637409 Bytes = 18200.59 KiB = 17.77 MiB
287 17:16:22.697324 output: Architecture: Unknown Architecture
288 17:16:22.697413 output: OS: Linux
289 17:16:22.697468 output: Load Address: unavailable
290 17:16:22.697524 output: Entry Point: unavailable
291 17:16:22.697580 output: Default Configuration: 'conf-1'
292 17:16:22.697636 output: Configuration 0 (conf-1)
293 17:16:22.697692 output: Description: mt8192-asurada-spherion-r0
294 17:16:22.697747 output: Kernel: kernel-1
295 17:16:22.697802 output: Init Ramdisk: ramdisk-1
296 17:16:22.697858 output: FDT: fdt-1
297 17:16:22.697914 output:
298 17:16:22.698108 end: 1.6.8.1 prepare-fit (duration 00:00:11) [common]
299 17:16:22.698203 end: 1.6.8 prepare-kernel (duration 00:00:11) [common]
300 17:16:22.698312 end: 1.6 prepare-tftp-overlay (duration 00:00:14) [common]
301 17:16:22.698409 start: 1.7 lxc-create-udev-rule-action (timeout 00:09:38) [common]
302 17:16:22.698486 No LXC device requested
303 17:16:22.698568 end: 1.7 lxc-create-udev-rule-action (duration 00:00:00) [common]
304 17:16:22.698655 start: 1.8 deploy-device-env (timeout 00:09:38) [common]
305 17:16:22.698735 end: 1.8 deploy-device-env (duration 00:00:00) [common]
306 17:16:22.698805 Checking files for TFTP limit of 4294967296 bytes.
307 17:16:22.699264 end: 1 tftp-deploy (duration 00:00:22) [common]
308 17:16:22.699372 start: 2 depthcharge-action (timeout 00:05:00) [common]
309 17:16:22.699468 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
310 17:16:22.699596 substitutions:
311 17:16:22.699665 - {DTB}: 8082983/tftp-deploy-tjk8rzjj/dtb/mt8192-asurada-spherion-r0.dtb
312 17:16:22.699731 - {INITRD}: 8082983/tftp-deploy-tjk8rzjj/ramdisk/ramdisk.cpio.gz
313 17:16:22.699794 - {KERNEL}: 8082983/tftp-deploy-tjk8rzjj/kernel/Image
314 17:16:22.699855 - {LAVA_MAC}: None
315 17:16:22.699915 - {NFSROOTFS}: /var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep
316 17:16:22.699974 - {NFS_SERVER_IP}: 192.168.201.1
317 17:16:22.700032 - {PRESEED_CONFIG}: None
318 17:16:22.700091 - {PRESEED_LOCAL}: None
319 17:16:22.700148 - {RAMDISK}: 8082983/tftp-deploy-tjk8rzjj/ramdisk/ramdisk.cpio.gz
320 17:16:22.700206 - {ROOT_PART}: None
321 17:16:22.700263 - {ROOT}: None
322 17:16:22.700320 - {SERVER_IP}: 192.168.201.1
323 17:16:22.700377 - {TEE}: None
324 17:16:22.700433 Parsed boot commands:
325 17:16:22.700490 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
326 17:16:22.700648 Parsed boot commands: tftpboot 192.168.201.1 8082983/tftp-deploy-tjk8rzjj/kernel/image.itb 8082983/tftp-deploy-tjk8rzjj/kernel/cmdline
327 17:16:22.700743 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
328 17:16:22.700830 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
329 17:16:22.700928 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
330 17:16:22.701014 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
331 17:16:22.701086 Not connected, no need to disconnect.
332 17:16:22.701164 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
333 17:16:22.701249 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
334 17:16:22.701342 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-9'
335 17:16:22.703920 Setting prompt string to ['lava-test: # ']
336 17:16:22.704206 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
337 17:16:22.704313 end: 2.2.1 reset-connection (duration 00:00:00) [common]
338 17:16:22.704435 start: 2.2.2 reset-device (timeout 00:05:00) [common]
339 17:16:22.704541 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
340 17:16:22.704737 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=reboot'
341 17:16:22.723446 >> Command sent successfully.
342 17:16:22.725498 Returned 0 in 0 seconds
343 17:16:22.826292 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
345 17:16:22.826625 end: 2.2.2 reset-device (duration 00:00:00) [common]
346 17:16:22.826729 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
347 17:16:22.826818 Setting prompt string to 'Starting depthcharge on Spherion...'
348 17:16:22.826885 Changing prompt to 'Starting depthcharge on Spherion...'
349 17:16:22.826954 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
350 17:16:22.827230 [Enter `^Ec?' for help]
351 17:16:28.644885
352 17:16:28.645105
353 17:16:28.645224 F0: 102B 0000
354 17:16:28.645349
355 17:16:28.645459 F3: 1001 0000 [0200]
356 17:16:28.645572
357 17:16:28.649067 F3: 1001 0000
358 17:16:28.649194
359 17:16:28.649313 F7: 102D 0000
360 17:16:28.649457
361 17:16:28.649569 F1: 0000 0000
362 17:16:28.649677
363 17:16:28.652595 V0: 0000 0000 [0001]
364 17:16:28.652719
365 17:16:28.652833 00: 0007 8000
366 17:16:28.652947
367 17:16:28.656218 01: 0000 0000
368 17:16:28.656341
369 17:16:28.656455 BP: 0C00 0209 [0000]
370 17:16:28.656565
371 17:16:28.659778 G0: 1182 0000
372 17:16:28.659902
373 17:16:28.660015 EC: 0000 0021 [4000]
374 17:16:28.660125
375 17:16:28.663351 S7: 0000 0000 [0000]
376 17:16:28.663474
377 17:16:28.663587 CC: 0000 0000 [0001]
378 17:16:28.663697
379 17:16:28.666782 T0: 0000 0040 [010F]
380 17:16:28.666906
381 17:16:28.667019 Jump to BL
382 17:16:28.667130
383 17:16:28.667241
384 17:16:28.691741
385 17:16:28.691879
386 17:16:28.699232 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
387 17:16:28.703008 ARM64: Exception handlers installed.
388 17:16:28.706503 ARM64: Testing exception
389 17:16:28.709790 ARM64: Done test exception
390 17:16:28.717074 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
391 17:16:28.724571 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
392 17:16:28.731809 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
393 17:16:28.742984 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
394 17:16:28.749547 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
395 17:16:28.756359 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
396 17:16:28.759467
397 17:16:28.769543 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
398 17:16:28.775864 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
399 17:16:28.794471 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
400 17:16:28.797975 WDT: Last reset was cold boot
401 17:16:28.800939 SPI1(PAD0) initialized at 2873684 Hz
402 17:16:28.804529 SPI5(PAD0) initialized at 992727 Hz
403 17:16:28.807944 VBOOT: Loading verstage.
404 17:16:28.814289 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
405 17:16:28.817743 FMAP: Found "FLASH" version 1.1 at 0x20000.
406 17:16:28.821252 FMAP: base = 0x0 size = 0x800000 #areas = 25
407 17:16:28.824502 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
408 17:16:28.831906 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
409 17:16:28.838732 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
410 17:16:28.849485 read SPI 0x96554 0xa1eb: 4591 us, 9028 KB/s, 72.224 Mbps
411 17:16:28.849615
412 17:16:28.849731
413 17:16:28.859638 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
414 17:16:28.862874 ARM64: Exception handlers installed.
415 17:16:28.866401 ARM64: Testing exception
416 17:16:28.866526 ARM64: Done test exception
417 17:16:28.872836 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
418 17:16:28.875894 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
419 17:16:28.890581 Probing TPM: . done!
420 17:16:28.890707 TPM ready after 0 ms
421 17:16:28.897545 Connected to device vid:did:rid of 1ae0:0028:00
422 17:16:28.904036 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
423 17:16:28.907536
424 17:16:28.944549 Initialized TPM device CR50 revision 0
425 17:16:28.957103 tlcl_send_startup: Startup return code is 0
426 17:16:28.957278 TPM: setup succeeded
427 17:16:28.968805 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
428 17:16:28.977397 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
429 17:16:28.988427 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
430 17:16:28.996262 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
431 17:16:28.999724 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
432 17:16:29.003013 in-header: 03 07 00 00 08 00 00 00
433 17:16:29.006695 in-data: aa e4 47 04 13 02 00 00
434 17:16:29.009685 Chrome EC: UHEPI supported
435 17:16:29.016740 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
436 17:16:29.019857 in-header: 03 ad 00 00 08 00 00 00
437 17:16:29.023323 in-data: 00 20 20 08 00 00 00 00
438 17:16:29.023448 Phase 1
439 17:16:29.026197 FMAP: area GBB found @ 3f5000 (12032 bytes)
440 17:16:29.033214 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
441 17:16:29.039960 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
442 17:16:29.042969 Recovery requested (1009000e)
443 17:16:29.047125 TPM: Extending digest for VBOOT: boot mode into PCR 0
444 17:16:29.055538 tlcl_extend: response is 0
445 17:16:29.063907 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
446 17:16:29.069105 tlcl_extend: response is 0
447 17:16:29.075240 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
448 17:16:29.096115 read SPI 0x210d4 0x2173b: 15136 us, 9052 KB/s, 72.416 Mbps
449 17:16:29.102826 BS: bootblock times (exec / console): total (unknown) / 148 ms
450 17:16:29.102990
451 17:16:29.103110
452 17:16:29.113245 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
453 17:16:29.116550 ARM64: Exception handlers installed.
454 17:16:29.116685 ARM64: Testing exception
455 17:16:29.119845
456 17:16:29.119970 ARM64: Done test exception
457 17:16:29.142037 pmic_efuse_setting: Set efuses in 11 msecs
458 17:16:29.145214 pmwrap_interface_init: Select PMIF_VLD_RDY
459 17:16:29.152363 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
460 17:16:29.155662 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
461 17:16:29.159237 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
462 17:16:29.166122 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
463 17:16:29.169202 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
464 17:16:29.175764 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
465 17:16:29.179271 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
466 17:16:29.186092 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
467 17:16:29.189514 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
468 17:16:29.192939 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
469 17:16:29.199534 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
470 17:16:29.202631 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
471 17:16:29.206068 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
472 17:16:29.213200 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
473 17:16:29.219862 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
474 17:16:29.226397 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
475 17:16:29.229683 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
476 17:16:29.236164 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
477 17:16:29.242957 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
478 17:16:29.249788 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
479 17:16:29.252898 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
480 17:16:29.260147 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
481 17:16:29.263727 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
482 17:16:29.270848 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
483 17:16:29.274460 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
484 17:16:29.281073 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
485 17:16:29.284506 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
486 17:16:29.291643 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
487 17:16:29.294443 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
488 17:16:29.301800 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
489 17:16:29.305307 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
490 17:16:29.312284 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
491 17:16:29.316002 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
492 17:16:29.319235 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
493 17:16:29.326007 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
494 17:16:29.328885 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
495 17:16:29.335907 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
496 17:16:29.338893 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
497 17:16:29.345631 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
498 17:16:29.349799 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
499 17:16:29.353342 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
500 17:16:29.356977 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
501 17:16:29.363592 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
502 17:16:29.366857 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
503 17:16:29.370428 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
504 17:16:29.377172 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
505 17:16:29.380092 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
506 17:16:29.383529 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
507 17:16:29.387091 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
508 17:16:29.393566 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
509 17:16:29.396825 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
510 17:16:29.403857 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
511 17:16:29.413269 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
512 17:16:29.416780 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
513 17:16:29.426803 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
514 17:16:29.433101 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
515 17:16:29.439652 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
516 17:16:29.443516 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
517 17:16:29.446434 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
518 17:16:29.454099 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6c, sec=0x0
519 17:16:29.460865 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
520 17:16:29.464202 [RTC]rtc_osc_init,62: osc32con val = 0xde6c
521 17:16:29.467381 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
522 17:16:29.478824 [RTC]rtc_get_frequency_meter,154: input=15, output=835
523 17:16:29.488341 [RTC]rtc_get_frequency_meter,154: input=7, output=708
524 17:16:29.497343 [RTC]rtc_get_frequency_meter,154: input=11, output=772
525 17:16:29.507103 [RTC]rtc_get_frequency_meter,154: input=13, output=804
526 17:16:29.516657 [RTC]rtc_get_frequency_meter,154: input=12, output=786
527 17:16:29.526008 [RTC]rtc_get_frequency_meter,154: input=12, output=788
528 17:16:29.535860 [RTC]rtc_get_frequency_meter,154: input=13, output=804
529 17:16:29.539556 [RTC]rtc_eosc_cali,47: left: 12, middle: 12, right: 13
530 17:16:29.545956 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6c
531 17:16:29.549590 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
532 17:16:29.552691 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
533 17:16:29.559292 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
534 17:16:29.563069 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
535 17:16:29.566564 ADC[4]: Raw value=905988 ID=7
536 17:16:29.566735 ADC[3]: Raw value=214021 ID=1
537 17:16:29.569641 RAM Code: 0x71
538 17:16:29.572708 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
539 17:16:29.579436 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
540 17:16:29.586022 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
541 17:16:29.592394 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
542 17:16:29.595930 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
543 17:16:29.598864 in-header: 03 07 00 00 08 00 00 00
544 17:16:29.602325 in-data: aa e4 47 04 13 02 00 00
545 17:16:29.605777 Chrome EC: UHEPI supported
546 17:16:29.612548 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
547 17:16:29.615519 in-header: 03 dd 00 00 08 00 00 00
548 17:16:29.619126 in-data: 90 20 60 08 00 00 00 00
549 17:16:29.622523 MRC: failed to locate region type 0.
550 17:16:29.628999 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
551 17:16:29.632244 DRAM-K: Running full calibration
552 17:16:29.639417 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
553 17:16:29.639758 header.status = 0x0
554 17:16:29.642206 header.version = 0x6 (expected: 0x6)
555 17:16:29.645787 header.size = 0xd00 (expected: 0xd00)
556 17:16:29.648932 header.flags = 0x0
557 17:16:29.655761 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
558 17:16:29.672736 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
559 17:16:29.679186 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
560 17:16:29.682427 dram_init: ddr_geometry: 2
561 17:16:29.685307 [EMI] MDL number = 2
562 17:16:29.685434 [EMI] Get MDL freq = 0
563 17:16:29.688844 dram_init: ddr_type: 0
564 17:16:29.688921 is_discrete_lpddr4: 1
565 17:16:29.692412 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
566 17:16:29.692491
567 17:16:29.692556
568 17:16:29.695450 [Bian_co] ETT version 0.0.0.1
569 17:16:29.702249 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
570 17:16:29.702327
571 17:16:29.705263 dramc_set_vcore_voltage set vcore to 650000
572 17:16:29.708904 Read voltage for 800, 4
573 17:16:29.708981 Vio18 = 0
574 17:16:29.709061 Vcore = 650000
575 17:16:29.711828 Vdram = 0
576 17:16:29.711903 Vddq = 0
577 17:16:29.711970 Vmddr = 0
578 17:16:29.715431 dram_init: config_dvfs: 1
579 17:16:29.718901 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
580 17:16:29.725401 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
581 17:16:29.728459 [SwImpedanceCal] DRVP=8, DRVN=16, ODTN=9
582 17:16:29.731930 freq_region=0, Reg: DRVP=8, DRVN=16, ODTN=9
583 17:16:29.735403 [SwImpedanceCal] DRVP=14, DRVN=24, ODTN=9
584 17:16:29.739045 freq_region=1, Reg: DRVP=14, DRVN=24, ODTN=9
585 17:16:29.741987 MEM_TYPE=3, freq_sel=18
586 17:16:29.745438 sv_algorithm_assistance_LP4_1600
587 17:16:29.748496 ============ PULL DRAM RESETB DOWN ============
588 17:16:29.755433 ========== PULL DRAM RESETB DOWN end =========
589 17:16:29.758411 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
590 17:16:29.761901 ===================================
591 17:16:29.765041 LPDDR4 DRAM CONFIGURATION
592 17:16:29.768579 ===================================
593 17:16:29.768653 EX_ROW_EN[0] = 0x0
594 17:16:29.771773 EX_ROW_EN[1] = 0x0
595 17:16:29.771846 LP4Y_EN = 0x0
596 17:16:29.775209 WORK_FSP = 0x0
597 17:16:29.775286 WL = 0x2
598 17:16:29.778222 RL = 0x2
599 17:16:29.778297 BL = 0x2
600 17:16:29.781914 RPST = 0x0
601 17:16:29.781988 RD_PRE = 0x0
602 17:16:29.784932 WR_PRE = 0x1
603 17:16:29.785006 WR_PST = 0x0
604 17:16:29.788444 DBI_WR = 0x0
605 17:16:29.788520 DBI_RD = 0x0
606 17:16:29.791546
607 17:16:29.791618 OTF = 0x1
608 17:16:29.795420 ===================================
609 17:16:29.798576 ===================================
610 17:16:29.798652 ANA top config
611 17:16:29.801639 ===================================
612 17:16:29.804971 DLL_ASYNC_EN = 0
613 17:16:29.808511 ALL_SLAVE_EN = 1
614 17:16:29.811634 NEW_RANK_MODE = 1
615 17:16:29.811722 DLL_IDLE_MODE = 1
616 17:16:29.815239
617 17:16:29.815324 LP45_APHY_COMB_EN = 1
618 17:16:29.818271 TX_ODT_DIS = 1
619 17:16:29.821782 NEW_8X_MODE = 1
620 17:16:29.825125 ===================================
621 17:16:29.828612 ===================================
622 17:16:29.831931 data_rate = 1600
623 17:16:29.832006 CKR = 1
624 17:16:29.835084
625 17:16:29.835163 DQ_P2S_RATIO = 8
626 17:16:29.838011 ===================================
627 17:16:29.841795 CA_P2S_RATIO = 8
628 17:16:29.844844 DQ_CA_OPEN = 0
629 17:16:29.848472 DQ_SEMI_OPEN = 0
630 17:16:29.851471 CA_SEMI_OPEN = 0
631 17:16:29.854797 CA_FULL_RATE = 0
632 17:16:29.854888 DQ_CKDIV4_EN = 1
633 17:16:29.858418 CA_CKDIV4_EN = 1
634 17:16:29.861471 CA_PREDIV_EN = 0
635 17:16:29.865124 PH8_DLY = 0
636 17:16:29.868308 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
637 17:16:29.868516 DQ_AAMCK_DIV = 4
638 17:16:29.871767 CA_AAMCK_DIV = 4
639 17:16:29.874803 CA_ADMCK_DIV = 4
640 17:16:29.878663 DQ_TRACK_CA_EN = 0
641 17:16:29.881478 CA_PICK = 800
642 17:16:29.884648 CA_MCKIO = 800
643 17:16:29.888261 MCKIO_SEMI = 0
644 17:16:29.888371 PLL_FREQ = 3068
645 17:16:29.891412 DQ_UI_PI_RATIO = 32
646 17:16:29.894784 CA_UI_PI_RATIO = 0
647 17:16:29.898200 ===================================
648 17:16:29.901282 ===================================
649 17:16:29.904935 memory_type:LPDDR4
650 17:16:29.908330 GP_NUM : 10
651 17:16:29.908416 SRAM_EN : 1
652 17:16:29.911458 MD32_EN : 0
653 17:16:29.914552 ===================================
654 17:16:29.914640 [ANA_INIT] >>>>>>>>>>>>>>
655 17:16:29.918187 <<<<<< [CONFIGURE PHASE]: ANA_TX
656 17:16:29.921228 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
657 17:16:29.924626 ===================================
658 17:16:29.927761 data_rate = 1600,PCW = 0X7600
659 17:16:29.931645 ===================================
660 17:16:29.934652 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
661 17:16:29.941298 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
662 17:16:29.944675 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
663 17:16:29.948015
664 17:16:29.951260 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
665 17:16:29.954883 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
666 17:16:29.958021 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
667 17:16:29.961096 [ANA_INIT] flow start
668 17:16:29.961173 [ANA_INIT] PLL >>>>>>>>
669 17:16:29.964614 [ANA_INIT] PLL <<<<<<<<
670 17:16:29.968264 [ANA_INIT] MIDPI >>>>>>>>
671 17:16:29.968336 [ANA_INIT] MIDPI <<<<<<<<
672 17:16:29.971437 [ANA_INIT] DLL >>>>>>>>
673 17:16:29.974959 [ANA_INIT] flow end
674 17:16:29.977777 ============ LP4 DIFF to SE enter ============
675 17:16:29.981376 ============ LP4 DIFF to SE exit ============
676 17:16:29.984629 [ANA_INIT] <<<<<<<<<<<<<
677 17:16:29.988191 [Flow] Enable top DCM control >>>>>
678 17:16:29.991362 [Flow] Enable top DCM control <<<<<
679 17:16:29.994803 Enable DLL master slave shuffle
680 17:16:29.997782 ==============================================================
681 17:16:30.001446 Gating Mode config
682 17:16:30.004541 ==============================================================
683 17:16:30.007779
684 17:16:30.007858 Config description:
685 17:16:30.018000 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
686 17:16:30.024846 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
687 17:16:30.027972 SELPH_MODE 0: By rank 1: By Phase
688 17:16:30.034710 ==============================================================
689 17:16:30.038089 GAT_TRACK_EN = 1
690 17:16:30.041634 RX_GATING_MODE = 2
691 17:16:30.045183 RX_GATING_TRACK_MODE = 2
692 17:16:30.047996 SELPH_MODE = 1
693 17:16:30.051406 PICG_EARLY_EN = 1
694 17:16:30.051859 VALID_LAT_VALUE = 1
695 17:16:30.058245 ==============================================================
696 17:16:30.061390 Enter into Gating configuration >>>>
697 17:16:30.064967 Exit from Gating configuration <<<<
698 17:16:30.068137 Enter into DVFS_PRE_config >>>>>
699 17:16:30.078336 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
700 17:16:30.081313 Exit from DVFS_PRE_config <<<<<
701 17:16:30.084557 Enter into PICG configuration >>>>
702 17:16:30.087662 Exit from PICG configuration <<<<
703 17:16:30.091419 [RX_INPUT] configuration >>>>>
704 17:16:30.094627 [RX_INPUT] configuration <<<<<
705 17:16:30.101425 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
706 17:16:30.104690 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
707 17:16:30.112137 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
708 17:16:30.115659 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
709 17:16:30.119384
710 17:16:30.123332 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
711 17:16:30.130032 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
712 17:16:30.133762 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
713 17:16:30.137094 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
714 17:16:30.141252 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
715 17:16:30.147664 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
716 17:16:30.151731 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
717 17:16:30.155370 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
718 17:16:30.159428 ===================================
719 17:16:30.159857 LPDDR4 DRAM CONFIGURATION
720 17:16:30.162852 ===================================
721 17:16:30.166587 EX_ROW_EN[0] = 0x0
722 17:16:30.167021 EX_ROW_EN[1] = 0x0
723 17:16:30.170043 LP4Y_EN = 0x0
724 17:16:30.170467 WORK_FSP = 0x0
725 17:16:30.173801 WL = 0x2
726 17:16:30.174315 RL = 0x2
727 17:16:30.177795 BL = 0x2
728 17:16:30.178223 RPST = 0x0
729 17:16:30.181296 RD_PRE = 0x0
730 17:16:30.181731 WR_PRE = 0x1
731 17:16:30.185003 WR_PST = 0x0
732 17:16:30.185567 DBI_WR = 0x0
733 17:16:30.186033 DBI_RD = 0x0
734 17:16:30.188660 OTF = 0x1
735 17:16:30.192235 ===================================
736 17:16:30.195936 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
737 17:16:30.200184 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
738 17:16:30.204078 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
739 17:16:30.207709 ===================================
740 17:16:30.211053 LPDDR4 DRAM CONFIGURATION
741 17:16:30.215104 ===================================
742 17:16:30.215713 EX_ROW_EN[0] = 0x10
743 17:16:30.218704 EX_ROW_EN[1] = 0x0
744 17:16:30.219336 LP4Y_EN = 0x0
745 17:16:30.222566 WORK_FSP = 0x0
746 17:16:30.223014 WL = 0x2
747 17:16:30.223358 RL = 0x2
748 17:16:30.225862 BL = 0x2
749 17:16:30.226292 RPST = 0x0
750 17:16:30.229769 RD_PRE = 0x0
751 17:16:30.230194 WR_PRE = 0x1
752 17:16:30.233307 WR_PST = 0x0
753 17:16:30.233764 DBI_WR = 0x0
754 17:16:30.236991 DBI_RD = 0x0
755 17:16:30.237462 OTF = 0x1
756 17:16:30.240615 ===================================
757 17:16:30.247345 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
758 17:16:30.251342 nWR fixed to 40
759 17:16:30.251764 [ModeRegInit_LP4] CH0 RK0
760 17:16:30.255093
761 17:16:30.255493 [ModeRegInit_LP4] CH0 RK1
762 17:16:30.259096 [ModeRegInit_LP4] CH1 RK0
763 17:16:30.259495 [ModeRegInit_LP4] CH1 RK1
764 17:16:30.262660 match AC timing 13
765 17:16:30.266229 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
766 17:16:30.269799 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
767 17:16:30.276387 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
768 17:16:30.279993 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
769 17:16:30.283161 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
770 17:16:30.286670 [EMI DOE] emi_dcm 0
771 17:16:30.290038 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
772 17:16:30.290463 ==
773 17:16:30.293183 Dram Type= 6, Freq= 0, CH_0, rank 0
774 17:16:30.296422 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
775 17:16:30.296847 ==
776 17:16:30.304664 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
777 17:16:30.307722 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
778 17:16:30.311273
779 17:16:30.318737 [CA 0] Center 37 (7~68) winsize 62
780 17:16:30.321648 [CA 1] Center 37 (6~68) winsize 63
781 17:16:30.325851 [CA 2] Center 34 (4~65) winsize 62
782 17:16:30.328382 [CA 3] Center 34 (4~65) winsize 62
783 17:16:30.332256 [CA 4] Center 34 (4~64) winsize 61
784 17:16:30.336021 [CA 5] Center 33 (3~64) winsize 62
785 17:16:30.336579
786 17:16:30.339509 [CmdBusTrainingLP45] Vref(ca) range 1: 30
787 17:16:30.339957
788 17:16:30.342734 [CATrainingPosCal] consider 1 rank data
789 17:16:30.345970 u2DelayCellTimex100 = 270/100 ps
790 17:16:30.349178 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
791 17:16:30.352559 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
792 17:16:30.355824 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
793 17:16:30.358762 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
794 17:16:30.365344 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
795 17:16:30.369168 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
796 17:16:30.369659
797 17:16:30.372239 CA PerBit enable=1, Macro0, CA PI delay=33
798 17:16:30.372672
799 17:16:30.375706 [CBTSetCACLKResult] CA Dly = 33
800 17:16:30.376117 CS Dly: 6 (0~37)
801 17:16:30.376438 ==
802 17:16:30.379368 Dram Type= 6, Freq= 0, CH_0, rank 1
803 17:16:30.382507 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
804 17:16:30.385480
805 17:16:30.385888 ==
806 17:16:30.389238 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
807 17:16:30.395760 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
808 17:16:30.404755 [CA 0] Center 37 (6~68) winsize 63
809 17:16:30.408608 [CA 1] Center 37 (7~68) winsize 62
810 17:16:30.411905 [CA 2] Center 34 (4~65) winsize 62
811 17:16:30.414700 [CA 3] Center 34 (4~65) winsize 62
812 17:16:30.418115 [CA 4] Center 33 (3~64) winsize 62
813 17:16:30.421395 [CA 5] Center 33 (2~64) winsize 63
814 17:16:30.421809
815 17:16:30.424581 [CmdBusTrainingLP45] Vref(ca) range 1: 32
816 17:16:30.424991
817 17:16:30.428270 [CATrainingPosCal] consider 2 rank data
818 17:16:30.431390 u2DelayCellTimex100 = 270/100 ps
819 17:16:30.434676 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
820 17:16:30.438218 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
821 17:16:30.444708 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
822 17:16:30.448591 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
823 17:16:30.449042 CA4 delay=34 (4~64),Diff = 1 PI (7 cell)
824 17:16:30.452262
825 17:16:30.452684 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
826 17:16:30.456324
827 17:16:30.456741
828 17:16:30.457201 CA PerBit enable=1, Macro0, CA PI delay=33
829 17:16:30.459855
830 17:16:30.460289
831 17:16:30.460695 [CBTSetCACLKResult] CA Dly = 33
832 17:16:30.463430 CS Dly: 6 (0~38)
833 17:16:30.463807
834 17:16:30.467544 ----->DramcWriteLeveling(PI) begin...
835 17:16:30.467975 ==
836 17:16:30.470232 Dram Type= 6, Freq= 0, CH_0, rank 0
837 17:16:30.473622 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
838 17:16:30.473928 ==
839 17:16:30.477492 Write leveling (Byte 0): 30 => 30
840 17:16:30.480629 Write leveling (Byte 1): 29 => 29
841 17:16:30.483823 DramcWriteLeveling(PI) end<-----
842 17:16:30.484007
843 17:16:30.484150 ==
844 17:16:30.487393 Dram Type= 6, Freq= 0, CH_0, rank 0
845 17:16:30.490677 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
846 17:16:30.490833 ==
847 17:16:30.494093 [Gating] SW mode calibration
848 17:16:30.500306 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
849 17:16:30.507550 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
850 17:16:30.510781 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
851 17:16:30.513863 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
852 17:16:30.520211 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
853 17:16:30.524005 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
854 17:16:30.527434 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
855 17:16:30.533915 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
856 17:16:30.537005 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
857 17:16:30.540427 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
858 17:16:30.543536 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
859 17:16:30.550382 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
860 17:16:30.553882 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
861 17:16:30.556985 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
862 17:16:30.563716 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
863 17:16:30.567452 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
864 17:16:30.570528 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
865 17:16:30.577180 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
866 17:16:30.580562 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
867 17:16:30.583718 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
868 17:16:30.590339 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
869 17:16:30.594070 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
870 17:16:30.597163 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
871 17:16:30.604016 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
872 17:16:30.607387 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
873 17:16:30.610301 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
874 17:16:30.617119 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
875 17:16:30.620118 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
876 17:16:30.623476 0 9 8 | B1->B0 | 2323 2b2b | 0 1 | (0 0) (1 1)
877 17:16:30.630242 0 9 12 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
878 17:16:30.633778 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
879 17:16:30.637099 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
880 17:16:30.643733 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
881 17:16:30.647160 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
882 17:16:30.650319 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
883 17:16:30.653390 0 10 4 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
884 17:16:30.657099
885 17:16:30.660319 0 10 8 | B1->B0 | 3434 2b2b | 0 0 | (0 0) (0 0)
886 17:16:30.663839 0 10 12 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
887 17:16:30.666869 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
888 17:16:30.673909 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
889 17:16:30.677157 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
890 17:16:30.680208 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
891 17:16:30.687208 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
892 17:16:30.690330 0 11 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
893 17:16:30.693490 0 11 8 | B1->B0 | 2727 3b3b | 0 0 | (0 0) (0 0)
894 17:16:30.699847 0 11 12 | B1->B0 | 3939 4646 | 0 0 | (0 0) (0 0)
895 17:16:30.703341 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
896 17:16:30.706406 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
897 17:16:30.713232 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
898 17:16:30.716617 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
899 17:16:30.719737 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
900 17:16:30.726638 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
901 17:16:30.729776 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
902 17:16:30.733444 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
903 17:16:30.740265 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
904 17:16:30.743621 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
905 17:16:30.746570 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
906 17:16:30.753771 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
907 17:16:30.756578 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
908 17:16:30.760204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
909 17:16:30.767019 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
910 17:16:30.769987 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
911 17:16:30.773464 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
912 17:16:30.776687 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
913 17:16:30.780295
914 17:16:30.783261 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
915 17:16:30.786843 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
916 17:16:30.789778 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
917 17:16:30.796578 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
918 17:16:30.800109 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
919 17:16:30.803202 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
920 17:16:30.806931 Total UI for P1: 0, mck2ui 16
921 17:16:30.809694 best dqsien dly found for B0: ( 0, 14, 8)
922 17:16:30.816504 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
923 17:16:30.816649 Total UI for P1: 0, mck2ui 16
924 17:16:30.823168 best dqsien dly found for B1: ( 0, 14, 12)
925 17:16:30.826183 best DQS0 dly(MCK, UI, PI) = (0, 14, 8)
926 17:16:30.829755 best DQS1 dly(MCK, UI, PI) = (0, 14, 12)
927 17:16:30.829841
928 17:16:30.833197 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 8)
929 17:16:30.836850 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 12)
930 17:16:30.840955 [Gating] SW calibration Done
931 17:16:30.841034 ==
932 17:16:30.844262 Dram Type= 6, Freq= 0, CH_0, rank 0
933 17:16:30.847373 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
934 17:16:30.847791 ==
935 17:16:30.848116 RX Vref Scan: 0
936 17:16:30.848416
937 17:16:30.850962 RX Vref 0 -> 0, step: 1
938 17:16:30.851399
939 17:16:30.854442 RX Delay -130 -> 252, step: 16
940 17:16:30.857885 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
941 17:16:30.861556 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
942 17:16:30.865037 iDelay=222, Bit 2, Center 85 (-34 ~ 205) 240
943 17:16:30.868423 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
944 17:16:30.876180 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
945 17:16:30.879752 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
946 17:16:30.882900 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
947 17:16:30.886876 iDelay=222, Bit 7, Center 101 (-18 ~ 221) 240
948 17:16:30.890525 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
949 17:16:30.894105 iDelay=222, Bit 9, Center 61 (-66 ~ 189) 256
950 17:16:30.897813 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
951 17:16:30.901345 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
952 17:16:30.904766 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
953 17:16:30.908377 iDelay=222, Bit 13, Center 77 (-50 ~ 205) 256
954 17:16:30.915718 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
955 17:16:30.919332 iDelay=222, Bit 15, Center 77 (-50 ~ 205) 256
956 17:16:30.919490 ==
957 17:16:30.922853 Dram Type= 6, Freq= 0, CH_0, rank 0
958 17:16:30.925976 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
959 17:16:30.926132 ==
960 17:16:30.926255 DQS Delay:
961 17:16:30.929231 DQS0 = 0, DQS1 = 0
962 17:16:30.929398 DQM Delay:
963 17:16:30.932882 DQM0 = 87, DQM1 = 73
964 17:16:30.933035 DQ Delay:
965 17:16:30.936289 DQ0 =85, DQ1 =85, DQ2 =85, DQ3 =85
966 17:16:30.939456 DQ4 =85, DQ5 =69, DQ6 =101, DQ7 =101
967 17:16:30.943038 DQ8 =61, DQ9 =61, DQ10 =69, DQ11 =69
968 17:16:30.946121 DQ12 =85, DQ13 =77, DQ14 =85, DQ15 =77
969 17:16:30.946276
970 17:16:30.946399
971 17:16:30.946513 ==
972 17:16:30.949536 Dram Type= 6, Freq= 0, CH_0, rank 0
973 17:16:30.953095 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
974 17:16:30.953252 ==
975 17:16:30.953393
976 17:16:30.953541
977 17:16:30.955956
978 17:16:30.956087 TX Vref Scan disable
979 17:16:30.959575 == TX Byte 0 ==
980 17:16:30.962963 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
981 17:16:30.965963 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
982 17:16:30.970045 == TX Byte 1 ==
983 17:16:30.973904 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
984 17:16:30.977282 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
985 17:16:30.977698 ==
986 17:16:30.980945 Dram Type= 6, Freq= 0, CH_0, rank 0
987 17:16:30.984169 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
988 17:16:30.984572 ==
989 17:16:30.998064 TX Vref=22, minBit 15, minWin=26, winSum=440
990 17:16:31.001610 TX Vref=24, minBit 5, minWin=27, winSum=443
991 17:16:31.004357 TX Vref=26, minBit 5, minWin=27, winSum=443
992 17:16:31.007942 TX Vref=28, minBit 8, minWin=27, winSum=447
993 17:16:31.011206 TX Vref=30, minBit 4, minWin=27, winSum=446
994 17:16:31.014742 TX Vref=32, minBit 9, minWin=26, winSum=439
995 17:16:31.021275 [TxChooseVref] Worse bit 8, Min win 27, Win sum 447, Final Vref 28
996 17:16:31.021442
997 17:16:31.024374 Final TX Range 1 Vref 28
998 17:16:31.024527
999 17:16:31.024647 ==
1000 17:16:31.027770 Dram Type= 6, Freq= 0, CH_0, rank 0
1001 17:16:31.031386 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1002 17:16:31.031539 ==
1003 17:16:31.031662
1004 17:16:31.031775
1005 17:16:31.034458
1006 17:16:31.034613 TX Vref Scan disable
1007 17:16:31.038112 == TX Byte 0 ==
1008 17:16:31.041229 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1009 17:16:31.044177 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1010 17:16:31.047769 == TX Byte 1 ==
1011 17:16:31.051222 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1012 17:16:31.054523 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1013 17:16:31.057948
1014 17:16:31.058104
1015 17:16:31.058225 [DATLAT]
1016 17:16:31.058339 Freq=800, CH0 RK0
1017 17:16:31.058448
1018 17:16:31.061157 DATLAT Default: 0xa
1019 17:16:31.061311 0, 0xFFFF, sum = 0
1020 17:16:31.064269 1, 0xFFFF, sum = 0
1021 17:16:31.064424 2, 0xFFFF, sum = 0
1022 17:16:31.067860 3, 0xFFFF, sum = 0
1023 17:16:31.068032 4, 0xFFFF, sum = 0
1024 17:16:31.070711
1025 17:16:31.070866 5, 0xFFFF, sum = 0
1026 17:16:31.074308 6, 0xFFFF, sum = 0
1027 17:16:31.074464 7, 0xFFFF, sum = 0
1028 17:16:31.077344 8, 0xFFFF, sum = 0
1029 17:16:31.077501 9, 0x0, sum = 1
1030 17:16:31.077624 10, 0x0, sum = 2
1031 17:16:31.080942 11, 0x0, sum = 3
1032 17:16:31.081126 12, 0x0, sum = 4
1033 17:16:31.084309 best_step = 10
1034 17:16:31.084517
1035 17:16:31.084663 ==
1036 17:16:31.087599 Dram Type= 6, Freq= 0, CH_0, rank 0
1037 17:16:31.091011 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1038 17:16:31.091166 ==
1039 17:16:31.094310 RX Vref Scan: 1
1040 17:16:31.094558
1041 17:16:31.094696 Set Vref Range= 32 -> 127
1042 17:16:31.097595
1043 17:16:31.097756 RX Vref 32 -> 127, step: 1
1044 17:16:31.097879
1045 17:16:31.100717 RX Delay -111 -> 252, step: 8
1046 17:16:31.100900
1047 17:16:31.104006 Set Vref, RX VrefLevel [Byte0]: 32
1048 17:16:31.107681 [Byte1]: 32
1049 17:16:31.107853
1050 17:16:31.111227 Set Vref, RX VrefLevel [Byte0]: 33
1051 17:16:31.114317 [Byte1]: 33
1052 17:16:31.118186
1053 17:16:31.118532 Set Vref, RX VrefLevel [Byte0]: 34
1054 17:16:31.121706 [Byte1]: 34
1055 17:16:31.125947
1056 17:16:31.126341 Set Vref, RX VrefLevel [Byte0]: 35
1057 17:16:31.129196 [Byte1]: 35
1058 17:16:31.133677
1059 17:16:31.134127 Set Vref, RX VrefLevel [Byte0]: 36
1060 17:16:31.136988 [Byte1]: 36
1061 17:16:31.141097
1062 17:16:31.141540 Set Vref, RX VrefLevel [Byte0]: 37
1063 17:16:31.144619 [Byte1]: 37
1064 17:16:31.149008
1065 17:16:31.149490 Set Vref, RX VrefLevel [Byte0]: 38
1066 17:16:31.152256 [Byte1]: 38
1067 17:16:31.156748
1068 17:16:31.157123 Set Vref, RX VrefLevel [Byte0]: 39
1069 17:16:31.160181 [Byte1]: 39
1070 17:16:31.164466
1071 17:16:31.164963 Set Vref, RX VrefLevel [Byte0]: 40
1072 17:16:31.167744 [Byte1]: 40
1073 17:16:31.172212
1074 17:16:31.172652 Set Vref, RX VrefLevel [Byte0]: 41
1075 17:16:31.175251 [Byte1]: 41
1076 17:16:31.179779
1077 17:16:31.180218 Set Vref, RX VrefLevel [Byte0]: 42
1078 17:16:31.182724 [Byte1]: 42
1079 17:16:31.187422
1080 17:16:31.187861 Set Vref, RX VrefLevel [Byte0]: 43
1081 17:16:31.190633 [Byte1]: 43
1082 17:16:31.194769
1083 17:16:31.195208 Set Vref, RX VrefLevel [Byte0]: 44
1084 17:16:31.198149 [Byte1]: 44
1085 17:16:31.202723
1086 17:16:31.203165 Set Vref, RX VrefLevel [Byte0]: 45
1087 17:16:31.206178 [Byte1]: 45
1088 17:16:31.210209
1089 17:16:31.210651 Set Vref, RX VrefLevel [Byte0]: 46
1090 17:16:31.213593
1091 17:16:31.214061 [Byte1]: 46
1092 17:16:31.217722
1093 17:16:31.218159 Set Vref, RX VrefLevel [Byte0]: 47
1094 17:16:31.221313 [Byte1]: 47
1095 17:16:31.226094
1096 17:16:31.226534 Set Vref, RX VrefLevel [Byte0]: 48
1097 17:16:31.229193 [Byte1]: 48
1098 17:16:31.233239
1099 17:16:31.233707 Set Vref, RX VrefLevel [Byte0]: 49
1100 17:16:31.236692 [Byte1]: 49
1101 17:16:31.240799
1102 17:16:31.241285 Set Vref, RX VrefLevel [Byte0]: 50
1103 17:16:31.244427 [Byte1]: 50
1104 17:16:31.248711
1105 17:16:31.249252 Set Vref, RX VrefLevel [Byte0]: 51
1106 17:16:31.252144 [Byte1]: 51
1107 17:16:31.256206
1108 17:16:31.256648 Set Vref, RX VrefLevel [Byte0]: 52
1109 17:16:31.260178 [Byte1]: 52
1110 17:16:31.264119
1111 17:16:31.264766 Set Vref, RX VrefLevel [Byte0]: 53
1112 17:16:31.267065 [Byte1]: 53
1113 17:16:31.271487
1114 17:16:31.271950 Set Vref, RX VrefLevel [Byte0]: 54
1115 17:16:31.274920
1116 17:16:31.275369 [Byte1]: 54
1117 17:16:31.279700
1118 17:16:31.280137 Set Vref, RX VrefLevel [Byte0]: 55
1119 17:16:31.282554 [Byte1]: 55
1120 17:16:31.286547
1121 17:16:31.286982 Set Vref, RX VrefLevel [Byte0]: 56
1122 17:16:31.290195
1123 17:16:31.290657 [Byte1]: 56
1124 17:16:31.294789
1125 17:16:31.295240 Set Vref, RX VrefLevel [Byte0]: 57
1126 17:16:31.297753 [Byte1]: 57
1127 17:16:31.301901
1128 17:16:31.302339 Set Vref, RX VrefLevel [Byte0]: 58
1129 17:16:31.305442 [Byte1]: 58
1130 17:16:31.309683
1131 17:16:31.310119 Set Vref, RX VrefLevel [Byte0]: 59
1132 17:16:31.312862 [Byte1]: 59
1133 17:16:31.317269
1134 17:16:31.317759 Set Vref, RX VrefLevel [Byte0]: 60
1135 17:16:31.321213 [Byte1]: 60
1136 17:16:31.325158
1137 17:16:31.325497 Set Vref, RX VrefLevel [Byte0]: 61
1138 17:16:31.328499 [Byte1]: 61
1139 17:16:31.332486
1140 17:16:31.332798 Set Vref, RX VrefLevel [Byte0]: 62
1141 17:16:31.335989 [Byte1]: 62
1142 17:16:31.340382
1143 17:16:31.340624 Set Vref, RX VrefLevel [Byte0]: 63
1144 17:16:31.343848 [Byte1]: 63
1145 17:16:31.347574
1146 17:16:31.347822 Set Vref, RX VrefLevel [Byte0]: 64
1147 17:16:31.351568 [Byte1]: 64
1148 17:16:31.355344
1149 17:16:31.355580 Set Vref, RX VrefLevel [Byte0]: 65
1150 17:16:31.358960 [Byte1]: 65
1151 17:16:31.362872
1152 17:16:31.363113 Set Vref, RX VrefLevel [Byte0]: 66
1153 17:16:31.366256
1154 17:16:31.366490 [Byte1]: 66
1155 17:16:31.370908
1156 17:16:31.370993 Set Vref, RX VrefLevel [Byte0]: 67
1157 17:16:31.373654 [Byte1]: 67
1158 17:16:31.378813
1159 17:16:31.378898 Set Vref, RX VrefLevel [Byte0]: 68
1160 17:16:31.382414 [Byte1]: 68
1161 17:16:31.386330
1162 17:16:31.386421 Set Vref, RX VrefLevel [Byte0]: 69
1163 17:16:31.389582 [Byte1]: 69
1164 17:16:31.393592
1165 17:16:31.393677 Set Vref, RX VrefLevel [Byte0]: 70
1166 17:16:31.397240 [Byte1]: 70
1167 17:16:31.401593
1168 17:16:31.402030 Set Vref, RX VrefLevel [Byte0]: 71
1169 17:16:31.405211 [Byte1]: 71
1170 17:16:31.409351
1171 17:16:31.409794 Set Vref, RX VrefLevel [Byte0]: 72
1172 17:16:31.413145 [Byte1]: 72
1173 17:16:31.417095
1174 17:16:31.417598 Set Vref, RX VrefLevel [Byte0]: 73
1175 17:16:31.420295 [Byte1]: 73
1176 17:16:31.424112
1177 17:16:31.424593 Set Vref, RX VrefLevel [Byte0]: 74
1178 17:16:31.427684
1179 17:16:31.428167 [Byte1]: 74
1180 17:16:31.432177
1181 17:16:31.432725 Set Vref, RX VrefLevel [Byte0]: 75
1182 17:16:31.435646 [Byte1]: 75
1183 17:16:31.439891
1184 17:16:31.440331 Set Vref, RX VrefLevel [Byte0]: 76
1185 17:16:31.443350 [Byte1]: 76
1186 17:16:31.447315
1187 17:16:31.447751 Set Vref, RX VrefLevel [Byte0]: 77
1188 17:16:31.451180 [Byte1]: 77
1189 17:16:31.455077
1190 17:16:31.455594 Set Vref, RX VrefLevel [Byte0]: 78
1191 17:16:31.458493 [Byte1]: 78
1192 17:16:31.462507
1193 17:16:31.462854 Set Vref, RX VrefLevel [Byte0]: 79
1194 17:16:31.465935 [Byte1]: 79
1195 17:16:31.470307
1196 17:16:31.470543 Set Vref, RX VrefLevel [Byte0]: 80
1197 17:16:31.474296 [Byte1]: 80
1198 17:16:31.477919
1199 17:16:31.478120 Set Vref, RX VrefLevel [Byte0]: 81
1200 17:16:31.481273 [Byte1]: 81
1201 17:16:31.485669
1202 17:16:31.485910 Final RX Vref Byte 0 = 60 to rank0
1203 17:16:31.489093 Final RX Vref Byte 1 = 48 to rank0
1204 17:16:31.493336 Final RX Vref Byte 0 = 60 to rank1
1205 17:16:31.496538 Final RX Vref Byte 1 = 48 to rank1==
1206 17:16:31.499943 Dram Type= 6, Freq= 0, CH_0, rank 0
1207 17:16:31.503520 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1208 17:16:31.503709 ==
1209 17:16:31.503858 DQS Delay:
1210 17:16:31.507486 DQS0 = 0, DQS1 = 0
1211 17:16:31.507681 DQM Delay:
1212 17:16:31.511159 DQM0 = 87, DQM1 = 76
1213 17:16:31.511346 DQ Delay:
1214 17:16:31.514758 DQ0 =84, DQ1 =92, DQ2 =84, DQ3 =84
1215 17:16:31.518375 DQ4 =88, DQ5 =76, DQ6 =92, DQ7 =96
1216 17:16:31.518566 DQ8 =68, DQ9 =64, DQ10 =76, DQ11 =68
1217 17:16:31.522482 DQ12 =80, DQ13 =80, DQ14 =88, DQ15 =84
1218 17:16:31.522677
1219 17:16:31.522829
1220 17:16:31.525870
1221 17:16:31.533033 [DQSOSCAuto] RK0, (LSB)MR18= 0x4122, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
1222 17:16:31.533286 CH0 RK0: MR19=606, MR18=4122
1223 17:16:31.540444 CH0_RK0: MR19=0x606, MR18=0x4122, DQSOSC=393, MR23=63, INC=95, DEC=63
1224 17:16:31.540674
1225 17:16:31.543882 ----->DramcWriteLeveling(PI) begin...
1226 17:16:31.544108 ==
1227 17:16:31.547975 Dram Type= 6, Freq= 0, CH_0, rank 1
1228 17:16:31.551630 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1229 17:16:31.551855 ==
1230 17:16:31.554742 Write leveling (Byte 0): 29 => 29
1231 17:16:31.558572 Write leveling (Byte 1): 29 => 29
1232 17:16:31.562065 DramcWriteLeveling(PI) end<-----
1233 17:16:31.562287
1234 17:16:31.562464 ==
1235 17:16:31.565507 Dram Type= 6, Freq= 0, CH_0, rank 1
1236 17:16:31.569647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1237 17:16:31.569890 ==
1238 17:16:31.613637 [Gating] SW mode calibration
1239 17:16:31.614166 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1240 17:16:31.614557 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1241 17:16:31.615328 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1242 17:16:31.615712 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1243 17:16:31.616066 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1244 17:16:31.616391 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1245 17:16:31.616698 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1246 17:16:31.617013 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1247 17:16:31.617371 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1248 17:16:31.657551 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1249 17:16:31.658029 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1250 17:16:31.658470 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1251 17:16:31.658964 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1252 17:16:31.659215 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1253 17:16:31.659444 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1254 17:16:31.659903 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1255 17:16:31.660067 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1256 17:16:31.660461 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1257 17:16:31.660612 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1258 17:16:31.702247 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1259 17:16:31.702905 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1260 17:16:31.703750 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1261 17:16:31.704140 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1262 17:16:31.704506 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1263 17:16:31.704861 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1264 17:16:31.705520 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1265 17:16:31.705903 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1266 17:16:31.706281 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1267 17:16:31.706638 0 9 8 | B1->B0 | 2323 2c2c | 0 1 | (0 0) (0 0)
1268 17:16:31.722097 0 9 12 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
1269 17:16:31.722437 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1270 17:16:31.723024 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1271 17:16:31.725345 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1272 17:16:31.725539 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1273 17:16:31.728997 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1274 17:16:31.732286 0 10 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1275 17:16:31.739157 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
1276 17:16:31.742204 0 10 12 | B1->B0 | 2525 2323 | 0 0 | (1 0) (0 0)
1277 17:16:31.745874 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1278 17:16:31.751878 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1279 17:16:31.755369 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1280 17:16:31.758888 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1281 17:16:31.765215 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1282 17:16:31.768790 0 11 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (0 0)
1283 17:16:31.771946 0 11 8 | B1->B0 | 2e2e 3e3e | 0 0 | (0 0) (0 0)
1284 17:16:31.778778 0 11 12 | B1->B0 | 3f3f 4646 | 0 0 | (0 0) (0 0)
1285 17:16:31.781913 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1286 17:16:31.785215 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1287 17:16:31.792038 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1288 17:16:31.795130 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1289 17:16:31.798875 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1290 17:16:31.805472 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1291 17:16:31.808419 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
1292 17:16:31.812137 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1293 17:16:31.815242 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1294 17:16:31.818821
1295 17:16:31.821818 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1296 17:16:31.825308 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1297 17:16:31.828240 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1298 17:16:31.831695
1299 17:16:31.834767 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1300 17:16:31.838150 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1301 17:16:31.841726 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1302 17:16:31.848213 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1303 17:16:31.851877 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1304 17:16:31.854889 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1305 17:16:31.861455 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1306 17:16:31.864875 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1307 17:16:31.868407 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1308 17:16:31.875035 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1309 17:16:31.878488 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1310 17:16:31.881694 Total UI for P1: 0, mck2ui 16
1311 17:16:31.885185 best dqsien dly found for B0: ( 0, 14, 6)
1312 17:16:31.887975 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1313 17:16:31.894549 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1314 17:16:31.894670 Total UI for P1: 0, mck2ui 16
1315 17:16:31.901304 best dqsien dly found for B1: ( 0, 14, 10)
1316 17:16:31.904494 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1317 17:16:31.907982 best DQS1 dly(MCK, UI, PI) = (0, 14, 10)
1318 17:16:31.908106
1319 17:16:31.911480 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1320 17:16:31.914512 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 10)
1321 17:16:31.918173 [Gating] SW calibration Done
1322 17:16:31.918285 ==
1323 17:16:31.921222 Dram Type= 6, Freq= 0, CH_0, rank 1
1324 17:16:31.924497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1325 17:16:31.924585 ==
1326 17:16:31.927865 RX Vref Scan: 0
1327 17:16:31.927985
1328 17:16:31.928088 RX Vref 0 -> 0, step: 1
1329 17:16:31.928188
1330 17:16:31.931186 RX Delay -130 -> 252, step: 16
1331 17:16:31.934587 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
1332 17:16:31.937850
1333 17:16:31.941360 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1334 17:16:31.944910 iDelay=222, Bit 2, Center 77 (-50 ~ 205) 256
1335 17:16:31.947986 iDelay=222, Bit 3, Center 77 (-50 ~ 205) 256
1336 17:16:31.951469 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1337 17:16:31.954599 iDelay=222, Bit 5, Center 69 (-50 ~ 189) 240
1338 17:16:31.961296 iDelay=222, Bit 6, Center 93 (-34 ~ 221) 256
1339 17:16:31.964557 iDelay=222, Bit 7, Center 93 (-34 ~ 221) 256
1340 17:16:31.968331 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1341 17:16:31.971595 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1342 17:16:31.975110 iDelay=222, Bit 10, Center 77 (-50 ~ 205) 256
1343 17:16:31.981768 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1344 17:16:31.984724 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1345 17:16:31.988308 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1346 17:16:31.991783 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1347 17:16:31.994880 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1348 17:16:31.998385 ==
1349 17:16:32.001427 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 17:16:32.004951 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 17:16:32.005422 ==
1352 17:16:32.006009 DQS Delay:
1353 17:16:32.008355 DQS0 = 0, DQS1 = 0
1354 17:16:32.009018 DQM Delay:
1355 17:16:32.011707 DQM0 = 83, DQM1 = 78
1356 17:16:32.012223 DQ Delay:
1357 17:16:32.014812 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =77
1358 17:16:32.018414 DQ4 =85, DQ5 =69, DQ6 =93, DQ7 =93
1359 17:16:32.021387 DQ8 =69, DQ9 =69, DQ10 =77, DQ11 =69
1360 17:16:32.024400 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1361 17:16:32.024630
1362 17:16:32.024812
1363 17:16:32.024980 ==
1364 17:16:32.028029 Dram Type= 6, Freq= 0, CH_0, rank 1
1365 17:16:32.031564 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1366 17:16:32.031751 ==
1367 17:16:32.031897
1368 17:16:32.032034
1369 17:16:32.034426 TX Vref Scan disable
1370 17:16:32.038017 == TX Byte 0 ==
1371 17:16:32.041043 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1372 17:16:32.044912 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1373 17:16:32.048112 == TX Byte 1 ==
1374 17:16:32.051084 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1375 17:16:32.054290 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1376 17:16:32.054445 ==
1377 17:16:32.057834 Dram Type= 6, Freq= 0, CH_0, rank 1
1378 17:16:32.064514 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1379 17:16:32.064672 ==
1380 17:16:32.075865 TX Vref=22, minBit 3, minWin=27, winSum=442
1381 17:16:32.079439 TX Vref=24, minBit 8, minWin=27, winSum=447
1382 17:16:32.082271 TX Vref=26, minBit 9, minWin=27, winSum=451
1383 17:16:32.085532 TX Vref=28, minBit 8, minWin=27, winSum=449
1384 17:16:32.089267 TX Vref=30, minBit 9, minWin=27, winSum=449
1385 17:16:32.092263 TX Vref=32, minBit 8, minWin=27, winSum=446
1386 17:16:32.095834
1387 17:16:32.099230 [TxChooseVref] Worse bit 9, Min win 27, Win sum 451, Final Vref 26
1388 17:16:32.099386
1389 17:16:32.102680 Final TX Range 1 Vref 26
1390 17:16:32.102835
1391 17:16:32.102954 ==
1392 17:16:32.105544 Dram Type= 6, Freq= 0, CH_0, rank 1
1393 17:16:32.108710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1394 17:16:32.108865 ==
1395 17:16:32.108984
1396 17:16:32.112178
1397 17:16:32.112331
1398 17:16:32.112450 TX Vref Scan disable
1399 17:16:32.115319 == TX Byte 0 ==
1400 17:16:32.119038 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1401 17:16:32.122197 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1402 17:16:32.125754 == TX Byte 1 ==
1403 17:16:32.128893 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1404 17:16:32.132381 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1405 17:16:32.135859
1406 17:16:32.136284
1407 17:16:32.136615 [DATLAT]
1408 17:16:32.136922 Freq=800, CH0 RK1
1409 17:16:32.137221
1410 17:16:32.139134 DATLAT Default: 0xa
1411 17:16:32.139559 0, 0xFFFF, sum = 0
1412 17:16:32.142270 1, 0xFFFF, sum = 0
1413 17:16:32.142704 2, 0xFFFF, sum = 0
1414 17:16:32.145518 3, 0xFFFF, sum = 0
1415 17:16:32.145947 4, 0xFFFF, sum = 0
1416 17:16:32.149086
1417 17:16:32.149570 5, 0xFFFF, sum = 0
1418 17:16:32.152134 6, 0xFFFF, sum = 0
1419 17:16:32.152568 7, 0xFFFF, sum = 0
1420 17:16:32.155863 8, 0xFFFF, sum = 0
1421 17:16:32.156353 9, 0x0, sum = 1
1422 17:16:32.156793 10, 0x0, sum = 2
1423 17:16:32.159025 11, 0x0, sum = 3
1424 17:16:32.159493 12, 0x0, sum = 4
1425 17:16:32.162460 best_step = 10
1426 17:16:32.162885
1427 17:16:32.163221 ==
1428 17:16:32.165425 Dram Type= 6, Freq= 0, CH_0, rank 1
1429 17:16:32.168996 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1430 17:16:32.169239 ==
1431 17:16:32.172438 RX Vref Scan: 0
1432 17:16:32.172698
1433 17:16:32.172915 RX Vref 0 -> 0, step: 1
1434 17:16:32.173120
1435 17:16:32.175209 RX Delay -95 -> 252, step: 8
1436 17:16:32.182327 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1437 17:16:32.185333 iDelay=209, Bit 1, Center 92 (-23 ~ 208) 232
1438 17:16:32.188603 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1439 17:16:32.191972 iDelay=209, Bit 3, Center 84 (-31 ~ 200) 232
1440 17:16:32.195636 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
1441 17:16:32.202390 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1442 17:16:32.205544 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1443 17:16:32.209154 iDelay=209, Bit 7, Center 92 (-23 ~ 208) 232
1444 17:16:32.212023 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1445 17:16:32.215639 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1446 17:16:32.222222 iDelay=209, Bit 10, Center 76 (-39 ~ 192) 232
1447 17:16:32.225452 iDelay=209, Bit 11, Center 68 (-47 ~ 184) 232
1448 17:16:32.229262 iDelay=209, Bit 12, Center 84 (-31 ~ 200) 232
1449 17:16:32.232401 iDelay=209, Bit 13, Center 84 (-31 ~ 200) 232
1450 17:16:32.235819 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1451 17:16:32.242555 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1452 17:16:32.243040 ==
1453 17:16:32.245559 Dram Type= 6, Freq= 0, CH_0, rank 1
1454 17:16:32.248820 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1455 17:16:32.249275 ==
1456 17:16:32.249657 DQS Delay:
1457 17:16:32.252014 DQS0 = 0, DQS1 = 0
1458 17:16:32.252505 DQM Delay:
1459 17:16:32.255484 DQM0 = 86, DQM1 = 76
1460 17:16:32.255815 DQ Delay:
1461 17:16:32.258638 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =84
1462 17:16:32.262110 DQ4 =84, DQ5 =76, DQ6 =96, DQ7 =92
1463 17:16:32.265667 DQ8 =64, DQ9 =64, DQ10 =76, DQ11 =68
1464 17:16:32.268739 DQ12 =84, DQ13 =84, DQ14 =88, DQ15 =84
1465 17:16:32.268967
1466 17:16:32.269147
1467 17:16:32.278528 [DQSOSCAuto] RK1, (LSB)MR18= 0x3d04, (MSB)MR19= 0x606, tDQSOscB0 = 409 ps tDQSOscB1 = 394 ps
1468 17:16:32.278763 CH0 RK1: MR19=606, MR18=3D04
1469 17:16:32.285391 CH0_RK1: MR19=0x606, MR18=0x3D04, DQSOSC=394, MR23=63, INC=95, DEC=63
1470 17:16:32.288687 [RxdqsGatingPostProcess] freq 800
1471 17:16:32.295112 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1472 17:16:32.298892 Pre-setting of DQS Precalculation
1473 17:16:32.302243 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1474 17:16:32.302510 ==
1475 17:16:32.305193 Dram Type= 6, Freq= 0, CH_1, rank 0
1476 17:16:32.308321 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1477 17:16:32.311538 ==
1478 17:16:32.315117 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1479 17:16:32.321539 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1480 17:16:32.330622 [CA 0] Center 36 (6~67) winsize 62
1481 17:16:32.333743 [CA 1] Center 36 (6~67) winsize 62
1482 17:16:32.337120 [CA 2] Center 34 (4~65) winsize 62
1483 17:16:32.340599 [CA 3] Center 34 (3~65) winsize 63
1484 17:16:32.343634 [CA 4] Center 34 (4~65) winsize 62
1485 17:16:32.347443 [CA 5] Center 34 (4~65) winsize 62
1486 17:16:32.347680
1487 17:16:32.350293 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1488 17:16:32.350531
1489 17:16:32.354100 [CATrainingPosCal] consider 1 rank data
1490 17:16:32.357005 u2DelayCellTimex100 = 270/100 ps
1491 17:16:32.360442 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1492 17:16:32.366864 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1493 17:16:32.370177 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1494 17:16:32.373967 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1495 17:16:32.377234 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1496 17:16:32.380264 CA5 delay=34 (4~65),Diff = 0 PI (0 cell)
1497 17:16:32.380542
1498 17:16:32.383514 CA PerBit enable=1, Macro0, CA PI delay=34
1499 17:16:32.383742
1500 17:16:32.386869 [CBTSetCACLKResult] CA Dly = 34
1501 17:16:32.387128 CS Dly: 5 (0~36)
1502 17:16:32.390007 ==
1503 17:16:32.394067 Dram Type= 6, Freq= 0, CH_1, rank 1
1504 17:16:32.396936 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1505 17:16:32.397194 ==
1506 17:16:32.400385 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1507 17:16:32.407058 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1508 17:16:32.416909 [CA 0] Center 36 (6~67) winsize 62
1509 17:16:32.420000 [CA 1] Center 36 (6~67) winsize 62
1510 17:16:32.423567 [CA 2] Center 34 (4~65) winsize 62
1511 17:16:32.426575 [CA 3] Center 34 (3~65) winsize 63
1512 17:16:32.430338 [CA 4] Center 34 (4~65) winsize 62
1513 17:16:32.433344 [CA 5] Center 34 (4~64) winsize 61
1514 17:16:32.433568
1515 17:16:32.436892 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1516 17:16:32.437128
1517 17:16:32.440137 [CATrainingPosCal] consider 2 rank data
1518 17:16:32.443672 u2DelayCellTimex100 = 270/100 ps
1519 17:16:32.447237 CA0 delay=36 (6~67),Diff = 2 PI (14 cell)
1520 17:16:32.450223 CA1 delay=36 (6~67),Diff = 2 PI (14 cell)
1521 17:16:32.456544 CA2 delay=34 (4~65),Diff = 0 PI (0 cell)
1522 17:16:32.460054 CA3 delay=34 (3~65),Diff = 0 PI (0 cell)
1523 17:16:32.463340 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
1524 17:16:32.466362 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
1525 17:16:32.466631
1526 17:16:32.470002 CA PerBit enable=1, Macro0, CA PI delay=34
1527 17:16:32.470180
1528 17:16:32.473525 [CBTSetCACLKResult] CA Dly = 34
1529 17:16:32.473662 CS Dly: 6 (0~38)
1530 17:16:32.473768
1531 17:16:32.476426 ----->DramcWriteLeveling(PI) begin...
1532 17:16:32.479771 ==
1533 17:16:32.479956 Dram Type= 6, Freq= 0, CH_1, rank 0
1534 17:16:32.483815
1535 17:16:32.486772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1536 17:16:32.487223 ==
1537 17:16:32.490164 Write leveling (Byte 0): 27 => 27
1538 17:16:32.493593 Write leveling (Byte 1): 28 => 28
1539 17:16:32.496709 DramcWriteLeveling(PI) end<-----
1540 17:16:32.497152
1541 17:16:32.497587 ==
1542 17:16:32.500124 Dram Type= 6, Freq= 0, CH_1, rank 0
1543 17:16:32.503091 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1544 17:16:32.503471 ==
1545 17:16:32.506531 [Gating] SW mode calibration
1546 17:16:32.513193 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1547 17:16:32.519867 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1548 17:16:32.522969 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1549 17:16:32.526336 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 1)
1550 17:16:32.529509 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1551 17:16:32.536162 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1552 17:16:32.539670 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1553 17:16:32.542917 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1554 17:16:32.549303 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1555 17:16:32.552859 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1556 17:16:32.556458 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1557 17:16:32.562864 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1558 17:16:32.565970 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1559 17:16:32.569305 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1560 17:16:32.576366 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1561 17:16:32.579378 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1562 17:16:32.582950 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1563 17:16:32.589564 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1564 17:16:32.592601 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1565 17:16:32.596073 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
1566 17:16:32.602618 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1567 17:16:32.606047 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1568 17:16:32.609518 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1569 17:16:32.616196 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1570 17:16:32.619322 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1571 17:16:32.622424 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1572 17:16:32.629645 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1573 17:16:32.633056 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
1574 17:16:32.636066 0 9 8 | B1->B0 | 3232 3030 | 0 1 | (0 0) (1 1)
1575 17:16:32.642587 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1576 17:16:32.646325 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1577 17:16:32.649384 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1578 17:16:32.652811 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1579 17:16:32.655981
1580 17:16:32.659405 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1581 17:16:32.662470 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1582 17:16:32.665945 0 10 4 | B1->B0 | 3434 3434 | 0 1 | (0 1) (1 0)
1583 17:16:32.668827
1584 17:16:32.672332 0 10 8 | B1->B0 | 2e2e 2d2d | 1 0 | (1 0) (0 0)
1585 17:16:32.675572 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1586 17:16:32.679013 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1587 17:16:32.682438
1588 17:16:32.685659 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1589 17:16:32.689073 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1590 17:16:32.692485 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1591 17:16:32.698958 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1592 17:16:32.702361 0 11 4 | B1->B0 | 2727 2827 | 0 1 | (0 0) (0 0)
1593 17:16:32.705815 0 11 8 | B1->B0 | 3939 4343 | 0 0 | (0 0) (0 0)
1594 17:16:32.712073 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1595 17:16:32.715781 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1596 17:16:32.718834 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1597 17:16:32.725593 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1598 17:16:32.728896 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1599 17:16:32.732140 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1600 17:16:32.739098 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1601 17:16:32.742344 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1602 17:16:32.745739 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1603 17:16:32.752003 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1604 17:16:32.755110 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1605 17:16:32.758475 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1606 17:16:32.765019 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1607 17:16:32.768579 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1608 17:16:32.771568 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1609 17:16:32.778518 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1610 17:16:32.782136 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1611 17:16:32.785061 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1612 17:16:32.791976 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1613 17:16:32.794886 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1614 17:16:32.798503 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1615 17:16:32.805134 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1616 17:16:32.808091 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1617 17:16:32.811377 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1618 17:16:32.814623 Total UI for P1: 0, mck2ui 16
1619 17:16:32.818171 best dqsien dly found for B0: ( 0, 14, 4)
1620 17:16:32.824934 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1621 17:16:32.825071 Total UI for P1: 0, mck2ui 16
1622 17:16:32.828020 best dqsien dly found for B1: ( 0, 14, 6)
1623 17:16:32.831509
1624 17:16:32.834746 best DQS0 dly(MCK, UI, PI) = (0, 14, 4)
1625 17:16:32.837781 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1626 17:16:32.837917
1627 17:16:32.841302 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 4)
1628 17:16:32.844711 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1629 17:16:32.847980 [Gating] SW calibration Done
1630 17:16:32.848117 ==
1631 17:16:32.851293 Dram Type= 6, Freq= 0, CH_1, rank 0
1632 17:16:32.854469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1633 17:16:32.854614 ==
1634 17:16:32.858010 RX Vref Scan: 0
1635 17:16:32.858167
1636 17:16:32.858299 RX Vref 0 -> 0, step: 1
1637 17:16:32.858419
1638 17:16:32.861289 RX Delay -130 -> 252, step: 16
1639 17:16:32.864446 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1640 17:16:32.871025 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1641 17:16:32.874503 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
1642 17:16:32.878139 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1643 17:16:32.881307 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1644 17:16:32.884245 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1645 17:16:32.891447 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1646 17:16:32.894464 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1647 17:16:32.897886 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1648 17:16:32.901084 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1649 17:16:32.904161 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1650 17:16:32.910933 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
1651 17:16:32.914064 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
1652 17:16:32.917617 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
1653 17:16:32.921042 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
1654 17:16:32.924465 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
1655 17:16:32.928081 ==
1656 17:16:32.930782 Dram Type= 6, Freq= 0, CH_1, rank 0
1657 17:16:32.934446 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1658 17:16:32.934540 ==
1659 17:16:32.934620 DQS Delay:
1660 17:16:32.937457 DQS0 = 0, DQS1 = 0
1661 17:16:32.937575 DQM Delay:
1662 17:16:32.941186 DQM0 = 89, DQM1 = 79
1663 17:16:32.941317 DQ Delay:
1664 17:16:32.944301 DQ0 =93, DQ1 =85, DQ2 =77, DQ3 =85
1665 17:16:32.947724 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1666 17:16:32.950869 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
1667 17:16:32.954008 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1668 17:16:32.954168
1669 17:16:32.954295
1670 17:16:32.954413 ==
1671 17:16:32.957359 Dram Type= 6, Freq= 0, CH_1, rank 0
1672 17:16:32.961122 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1673 17:16:32.961366 ==
1674 17:16:32.961550
1675 17:16:32.961716
1676 17:16:32.963931 TX Vref Scan disable
1677 17:16:32.967762 == TX Byte 0 ==
1678 17:16:32.971232 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1679 17:16:32.974216 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1680 17:16:32.977493 == TX Byte 1 ==
1681 17:16:32.981262 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1682 17:16:32.984189 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1683 17:16:32.984921 ==
1684 17:16:32.987769 Dram Type= 6, Freq= 0, CH_1, rank 0
1685 17:16:32.993977 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1686 17:16:32.994743 ==
1687 17:16:33.005965 TX Vref=22, minBit 3, minWin=27, winSum=439
1688 17:16:33.009093 TX Vref=24, minBit 8, minWin=26, winSum=445
1689 17:16:33.012086 TX Vref=26, minBit 10, minWin=27, winSum=452
1690 17:16:33.015357 TX Vref=28, minBit 10, minWin=27, winSum=451
1691 17:16:33.018887 TX Vref=30, minBit 8, minWin=27, winSum=447
1692 17:16:33.022114 TX Vref=32, minBit 0, minWin=27, winSum=444
1693 17:16:33.025668
1694 17:16:33.028724 [TxChooseVref] Worse bit 10, Min win 27, Win sum 452, Final Vref 26
1695 17:16:33.028811
1696 17:16:33.032345 Final TX Range 1 Vref 26
1697 17:16:33.032442
1698 17:16:33.032517 ==
1699 17:16:33.035491 Dram Type= 6, Freq= 0, CH_1, rank 0
1700 17:16:33.038749 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1701 17:16:33.038836 ==
1702 17:16:33.042333
1703 17:16:33.042433
1704 17:16:33.042501 TX Vref Scan disable
1705 17:16:33.045795 == TX Byte 0 ==
1706 17:16:33.049080 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
1707 17:16:33.051958 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
1708 17:16:33.055545
1709 17:16:33.055631 == TX Byte 1 ==
1710 17:16:33.059166 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1711 17:16:33.062284 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1712 17:16:33.065807
1713 17:16:33.065897 [DATLAT]
1714 17:16:33.065966 Freq=800, CH1 RK0
1715 17:16:33.066031
1716 17:16:33.068906 DATLAT Default: 0xa
1717 17:16:33.068978 0, 0xFFFF, sum = 0
1718 17:16:33.072500 1, 0xFFFF, sum = 0
1719 17:16:33.072587 2, 0xFFFF, sum = 0
1720 17:16:33.075316 3, 0xFFFF, sum = 0
1721 17:16:33.075405 4, 0xFFFF, sum = 0
1722 17:16:33.079106 5, 0xFFFF, sum = 0
1723 17:16:33.082299 6, 0xFFFF, sum = 0
1724 17:16:33.082383 7, 0xFFFF, sum = 0
1725 17:16:33.085231 8, 0xFFFF, sum = 0
1726 17:16:33.085315 9, 0x0, sum = 1
1727 17:16:33.085427 10, 0x0, sum = 2
1728 17:16:33.088861 11, 0x0, sum = 3
1729 17:16:33.088940 12, 0x0, sum = 4
1730 17:16:33.092216 best_step = 10
1731 17:16:33.092297
1732 17:16:33.092389 ==
1733 17:16:33.095210 Dram Type= 6, Freq= 0, CH_1, rank 0
1734 17:16:33.098748 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1735 17:16:33.098830 ==
1736 17:16:33.102351 RX Vref Scan: 1
1737 17:16:33.102434
1738 17:16:33.102501 Set Vref Range= 32 -> 127
1739 17:16:33.105238
1740 17:16:33.105316
1741 17:16:33.105403 RX Vref 32 -> 127, step: 1
1742 17:16:33.105466
1743 17:16:33.108655 RX Delay -95 -> 252, step: 8
1744 17:16:33.108732
1745 17:16:33.111775 Set Vref, RX VrefLevel [Byte0]: 32
1746 17:16:33.115405 [Byte1]: 32
1747 17:16:33.115485
1748 17:16:33.118506 Set Vref, RX VrefLevel [Byte0]: 33
1749 17:16:33.121577 [Byte1]: 33
1750 17:16:33.125861
1751 17:16:33.125941 Set Vref, RX VrefLevel [Byte0]: 34
1752 17:16:33.129326 [Byte1]: 34
1753 17:16:33.133499
1754 17:16:33.133576 Set Vref, RX VrefLevel [Byte0]: 35
1755 17:16:33.136718 [Byte1]: 35
1756 17:16:33.141236
1757 17:16:33.141315 Set Vref, RX VrefLevel [Byte0]: 36
1758 17:16:33.144287 [Byte1]: 36
1759 17:16:33.148931
1760 17:16:33.149005 Set Vref, RX VrefLevel [Byte0]: 37
1761 17:16:33.152046 [Byte1]: 37
1762 17:16:33.156427
1763 17:16:33.156510 Set Vref, RX VrefLevel [Byte0]: 38
1764 17:16:33.159515 [Byte1]: 38
1765 17:16:33.164144
1766 17:16:33.164226 Set Vref, RX VrefLevel [Byte0]: 39
1767 17:16:33.167068 [Byte1]: 39
1768 17:16:33.171729
1769 17:16:33.171816 Set Vref, RX VrefLevel [Byte0]: 40
1770 17:16:33.174735 [Byte1]: 40
1771 17:16:33.179165
1772 17:16:33.179246 Set Vref, RX VrefLevel [Byte0]: 41
1773 17:16:33.182634 [Byte1]: 41
1774 17:16:33.186887
1775 17:16:33.186966 Set Vref, RX VrefLevel [Byte0]: 42
1776 17:16:33.189887 [Byte1]: 42
1777 17:16:33.194237
1778 17:16:33.194325 Set Vref, RX VrefLevel [Byte0]: 43
1779 17:16:33.197565 [Byte1]: 43
1780 17:16:33.201880
1781 17:16:33.201966 Set Vref, RX VrefLevel [Byte0]: 44
1782 17:16:33.205127 [Byte1]: 44
1783 17:16:33.209608
1784 17:16:33.209696 Set Vref, RX VrefLevel [Byte0]: 45
1785 17:16:33.215683 [Byte1]: 45
1786 17:16:33.215776
1787 17:16:33.218976 Set Vref, RX VrefLevel [Byte0]: 46
1788 17:16:33.222696 [Byte1]: 46
1789 17:16:33.222789
1790 17:16:33.225709 Set Vref, RX VrefLevel [Byte0]: 47
1791 17:16:33.228860 [Byte1]: 47
1792 17:16:33.228942
1793 17:16:33.232567 Set Vref, RX VrefLevel [Byte0]: 48
1794 17:16:33.235866 [Byte1]: 48
1795 17:16:33.239812
1796 17:16:33.239910 Set Vref, RX VrefLevel [Byte0]: 49
1797 17:16:33.243343 [Byte1]: 49
1798 17:16:33.247373
1799 17:16:33.247462 Set Vref, RX VrefLevel [Byte0]: 50
1800 17:16:33.250984 [Byte1]: 50
1801 17:16:33.255035
1802 17:16:33.255128 Set Vref, RX VrefLevel [Byte0]: 51
1803 17:16:33.258413 [Byte1]: 51
1804 17:16:33.262906
1805 17:16:33.262994 Set Vref, RX VrefLevel [Byte0]: 52
1806 17:16:33.265953 [Byte1]: 52
1807 17:16:33.270380
1808 17:16:33.270478 Set Vref, RX VrefLevel [Byte0]: 53
1809 17:16:33.273939 [Byte1]: 53
1810 17:16:33.278188
1811 17:16:33.278305 Set Vref, RX VrefLevel [Byte0]: 54
1812 17:16:33.281224 [Byte1]: 54
1813 17:16:33.285509
1814 17:16:33.285637 Set Vref, RX VrefLevel [Byte0]: 55
1815 17:16:33.288582 [Byte1]: 55
1816 17:16:33.293108
1817 17:16:33.293238 Set Vref, RX VrefLevel [Byte0]: 56
1818 17:16:33.296678 [Byte1]: 56
1819 17:16:33.300673
1820 17:16:33.300853 Set Vref, RX VrefLevel [Byte0]: 57
1821 17:16:33.303916 [Byte1]: 57
1822 17:16:33.308436
1823 17:16:33.308645 Set Vref, RX VrefLevel [Byte0]: 58
1824 17:16:33.311726 [Byte1]: 58
1825 17:16:33.314861
1826 17:16:33.315119
1827 17:16:33.318377 Set Vref, RX VrefLevel [Byte0]: 59
1828 17:16:33.321732 [Byte1]: 59
1829 17:16:33.322132
1830 17:16:33.325389 Set Vref, RX VrefLevel [Byte0]: 60
1831 17:16:33.328375 [Byte1]: 60
1832 17:16:33.328774
1833 17:16:33.331524 Set Vref, RX VrefLevel [Byte0]: 61
1834 17:16:33.335226 [Byte1]: 61
1835 17:16:33.338782
1836 17:16:33.339184 Set Vref, RX VrefLevel [Byte0]: 62
1837 17:16:33.342487 [Byte1]: 62
1838 17:16:33.346542
1839 17:16:33.346941 Set Vref, RX VrefLevel [Byte0]: 63
1840 17:16:33.349805 [Byte1]: 63
1841 17:16:33.353982
1842 17:16:33.354391 Set Vref, RX VrefLevel [Byte0]: 64
1843 17:16:33.357655 [Byte1]: 64
1844 17:16:33.361645
1845 17:16:33.362097 Set Vref, RX VrefLevel [Byte0]: 65
1846 17:16:33.364982 [Byte1]: 65
1847 17:16:33.369563
1848 17:16:33.370108 Set Vref, RX VrefLevel [Byte0]: 66
1849 17:16:33.372955 [Byte1]: 66
1850 17:16:33.376931
1851 17:16:33.377389 Set Vref, RX VrefLevel [Byte0]: 67
1852 17:16:33.380123 [Byte1]: 67
1853 17:16:33.384390
1854 17:16:33.384828 Set Vref, RX VrefLevel [Byte0]: 68
1855 17:16:33.387979 [Byte1]: 68
1856 17:16:33.392160
1857 17:16:33.392586 Set Vref, RX VrefLevel [Byte0]: 69
1858 17:16:33.395178 [Byte1]: 69
1859 17:16:33.399668
1860 17:16:33.400084 Set Vref, RX VrefLevel [Byte0]: 70
1861 17:16:33.402887 [Byte1]: 70
1862 17:16:33.407359
1863 17:16:33.407835 Set Vref, RX VrefLevel [Byte0]: 71
1864 17:16:33.410420 [Byte1]: 71
1865 17:16:33.414991
1866 17:16:33.415402 Set Vref, RX VrefLevel [Byte0]: 72
1867 17:16:33.418025 [Byte1]: 72
1868 17:16:33.422714
1869 17:16:33.423150 Set Vref, RX VrefLevel [Byte0]: 73
1870 17:16:33.425682 [Byte1]: 73
1871 17:16:33.430463
1872 17:16:33.430870 Set Vref, RX VrefLevel [Byte0]: 74
1873 17:16:33.433550 [Byte1]: 74
1874 17:16:33.437619
1875 17:16:33.438129 Set Vref, RX VrefLevel [Byte0]: 75
1876 17:16:33.441151 [Byte1]: 75
1877 17:16:33.445254
1878 17:16:33.445683 Final RX Vref Byte 0 = 56 to rank0
1879 17:16:33.448716 Final RX Vref Byte 1 = 66 to rank0
1880 17:16:33.452093 Final RX Vref Byte 0 = 56 to rank1
1881 17:16:33.455086 Final RX Vref Byte 1 = 66 to rank1==
1882 17:16:33.458665 Dram Type= 6, Freq= 0, CH_1, rank 0
1883 17:16:33.465418 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1884 17:16:33.465884 ==
1885 17:16:33.466234 DQS Delay:
1886 17:16:33.466574 DQS0 = 0, DQS1 = 0
1887 17:16:33.468682 DQM Delay:
1888 17:16:33.469120 DQM0 = 87, DQM1 = 78
1889 17:16:33.472132 DQ Delay:
1890 17:16:33.475421 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1891 17:16:33.478412 DQ4 =84, DQ5 =100, DQ6 =100, DQ7 =80
1892 17:16:33.481778 DQ8 =68, DQ9 =68, DQ10 =80, DQ11 =68
1893 17:16:33.485081 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =88
1894 17:16:33.485574
1895 17:16:33.485973
1896 17:16:33.491781 [DQSOSCAuto] RK0, (LSB)MR18= 0x301c, (MSB)MR19= 0x606, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
1897 17:16:33.495179 CH1 RK0: MR19=606, MR18=301C
1898 17:16:33.501745 CH1_RK0: MR19=0x606, MR18=0x301C, DQSOSC=397, MR23=63, INC=93, DEC=62
1899 17:16:33.502182
1900 17:16:33.505147 ----->DramcWriteLeveling(PI) begin...
1901 17:16:33.505626 ==
1902 17:16:33.508157 Dram Type= 6, Freq= 0, CH_1, rank 1
1903 17:16:33.511581 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1904 17:16:33.512042 ==
1905 17:16:33.515263 Write leveling (Byte 0): 28 => 28
1906 17:16:33.518560 Write leveling (Byte 1): 31 => 31
1907 17:16:33.521660 DramcWriteLeveling(PI) end<-----
1908 17:16:33.522145
1909 17:16:33.522564 ==
1910 17:16:33.525032 Dram Type= 6, Freq= 0, CH_1, rank 1
1911 17:16:33.528471 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1912 17:16:33.528980 ==
1913 17:16:33.531561 [Gating] SW mode calibration
1914 17:16:33.538408 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1915 17:16:33.544684 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1916 17:16:33.548307 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1917 17:16:33.551399 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1918 17:16:33.554704
1919 17:16:33.558165 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (1 0)
1920 17:16:33.561273 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1921 17:16:33.564872 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1922 17:16:33.568034
1923 17:16:33.571441 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1924 17:16:33.574654 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1925 17:16:33.577917 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1926 17:16:33.584804 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1927 17:16:33.587939 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1928 17:16:33.591607 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1929 17:16:33.598217 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1930 17:16:33.601297 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1931 17:16:33.604620 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1932 17:16:33.610820 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1933 17:16:33.614395 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1934 17:16:33.617967 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 0)
1935 17:16:33.624482 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1936 17:16:33.627813 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1937 17:16:33.630808 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1938 17:16:33.637340 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1939 17:16:33.641250 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1940 17:16:33.644079 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1941 17:16:33.650848 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1942 17:16:33.654015 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1943 17:16:33.657616 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1944 17:16:33.664218 0 9 8 | B1->B0 | 3333 2828 | 0 1 | (0 0) (0 0)
1945 17:16:33.667362 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1946 17:16:33.670674 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1947 17:16:33.677495 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1948 17:16:33.680841 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1949 17:16:33.684078 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1950 17:16:33.687801 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1951 17:16:33.690772
1952 17:16:33.694323 0 10 4 | B1->B0 | 3131 3333 | 1 1 | (1 0) (1 0)
1953 17:16:33.697743 0 10 8 | B1->B0 | 2828 2e2e | 1 1 | (1 0) (1 0)
1954 17:16:33.701146 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1955 17:16:33.707800 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1956 17:16:33.711043 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1957 17:16:33.714559 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1958 17:16:33.721183 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1959 17:16:33.724580 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1960 17:16:33.728230 0 11 4 | B1->B0 | 2d2d 2323 | 0 1 | (0 0) (0 0)
1961 17:16:33.735145 0 11 8 | B1->B0 | 403f 3434 | 1 0 | (0 0) (0 0)
1962 17:16:33.738182 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1963 17:16:33.741281 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1964 17:16:33.748002 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1965 17:16:33.751106 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1966 17:16:33.754584 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1967 17:16:33.761218 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1968 17:16:33.764063 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1969 17:16:33.767760 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1970 17:16:33.774310 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1971 17:16:33.777576 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1972 17:16:33.780626 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1973 17:16:33.784025 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1974 17:16:33.787605
1975 17:16:33.791088 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1976 17:16:33.794240 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1977 17:16:33.798009 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1978 17:16:33.804708 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1979 17:16:33.807825 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1980 17:16:33.810776 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1981 17:16:33.817276 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1982 17:16:33.820776 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1983 17:16:33.823829 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1984 17:16:33.830784 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1985 17:16:33.833657 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1986 17:16:33.837185 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
1987 17:16:33.843883 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1988 17:16:33.843971 Total UI for P1: 0, mck2ui 16
1989 17:16:33.847010
1990 17:16:33.850611 best dqsien dly found for B0: ( 0, 14, 6)
1991 17:16:33.850698 Total UI for P1: 0, mck2ui 16
1992 17:16:33.857070 best dqsien dly found for B1: ( 0, 14, 6)
1993 17:16:33.860293 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1994 17:16:33.863791 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1995 17:16:33.863878
1996 17:16:33.867080 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1997 17:16:33.870323 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1998 17:16:33.873757 [Gating] SW calibration Done
1999 17:16:33.873844 ==
2000 17:16:33.877123 Dram Type= 6, Freq= 0, CH_1, rank 1
2001 17:16:33.880271 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2002 17:16:33.880360 ==
2003 17:16:33.883445 RX Vref Scan: 0
2004 17:16:33.883533
2005 17:16:33.883601 RX Vref 0 -> 0, step: 1
2006 17:16:33.883665
2007 17:16:33.887061 RX Delay -130 -> 252, step: 16
2008 17:16:33.890286 iDelay=222, Bit 0, Center 85 (-34 ~ 205) 240
2009 17:16:33.897225 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
2010 17:16:33.900032 iDelay=222, Bit 2, Center 77 (-34 ~ 189) 224
2011 17:16:33.903801 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
2012 17:16:33.906656 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
2013 17:16:33.910144 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
2014 17:16:33.916604 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
2015 17:16:33.920144 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
2016 17:16:33.923069 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
2017 17:16:33.926744 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
2018 17:16:33.930246 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
2019 17:16:33.933255
2020 17:16:33.937084 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
2021 17:16:33.939974 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
2022 17:16:33.943204 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
2023 17:16:33.946683 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
2024 17:16:33.953467 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
2025 17:16:33.953566 ==
2026 17:16:33.957057 Dram Type= 6, Freq= 0, CH_1, rank 1
2027 17:16:33.959944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2028 17:16:33.960036 ==
2029 17:16:33.960109 DQS Delay:
2030 17:16:33.963162 DQS0 = 0, DQS1 = 0
2031 17:16:33.963247 DQM Delay:
2032 17:16:33.966762 DQM0 = 88, DQM1 = 79
2033 17:16:33.966847 DQ Delay:
2034 17:16:33.969940 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
2035 17:16:33.973391 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
2036 17:16:33.976255 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =69
2037 17:16:33.979709 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
2038 17:16:33.979811
2039 17:16:33.979919
2040 17:16:33.980020 ==
2041 17:16:33.983240 Dram Type= 6, Freq= 0, CH_1, rank 1
2042 17:16:33.986673 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2043 17:16:33.986758 ==
2044 17:16:33.989697
2045 17:16:33.989788
2046 17:16:33.989858 TX Vref Scan disable
2047 17:16:33.993199 == TX Byte 0 ==
2048 17:16:33.996340 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2049 17:16:33.999623 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2050 17:16:34.003375 == TX Byte 1 ==
2051 17:16:34.006463 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2052 17:16:34.009910 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2053 17:16:34.010005 ==
2054 17:16:34.012778 Dram Type= 6, Freq= 0, CH_1, rank 1
2055 17:16:34.019551 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2056 17:16:34.019637 ==
2057 17:16:34.031602 TX Vref=22, minBit 8, minWin=26, winSum=443
2058 17:16:34.035158 TX Vref=24, minBit 8, minWin=27, winSum=448
2059 17:16:34.038125 TX Vref=26, minBit 15, minWin=27, winSum=450
2060 17:16:34.041757 TX Vref=28, minBit 15, minWin=27, winSum=453
2061 17:16:34.044991 TX Vref=30, minBit 13, minWin=27, winSum=451
2062 17:16:34.051720 TX Vref=32, minBit 8, minWin=27, winSum=445
2063 17:16:34.054770 [TxChooseVref] Worse bit 15, Min win 27, Win sum 453, Final Vref 28
2064 17:16:34.054857
2065 17:16:34.058310 Final TX Range 1 Vref 28
2066 17:16:34.058415
2067 17:16:34.058484 ==
2068 17:16:34.061448 Dram Type= 6, Freq= 0, CH_1, rank 1
2069 17:16:34.064941 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2070 17:16:34.068067
2071 17:16:34.068154 ==
2072 17:16:34.068222
2073 17:16:34.068286
2074 17:16:34.068346 TX Vref Scan disable
2075 17:16:34.071852 == TX Byte 0 ==
2076 17:16:34.075148 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2077 17:16:34.078840 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2078 17:16:34.081775
2079 17:16:34.081862 == TX Byte 1 ==
2080 17:16:34.085403 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
2081 17:16:34.088824 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
2082 17:16:34.092042
2083 17:16:34.092130 [DATLAT]
2084 17:16:34.092201 Freq=800, CH1 RK1
2085 17:16:34.092265
2086 17:16:34.095484 DATLAT Default: 0xa
2087 17:16:34.095570 0, 0xFFFF, sum = 0
2088 17:16:34.098470 1, 0xFFFF, sum = 0
2089 17:16:34.098556 2, 0xFFFF, sum = 0
2090 17:16:34.102002 3, 0xFFFF, sum = 0
2091 17:16:34.102078 4, 0xFFFF, sum = 0
2092 17:16:34.105870 5, 0xFFFF, sum = 0
2093 17:16:34.105948 6, 0xFFFF, sum = 0
2094 17:16:34.108703
2095 17:16:34.108792 7, 0xFFFF, sum = 0
2096 17:16:34.112021 8, 0xFFFF, sum = 0
2097 17:16:34.112123 9, 0x0, sum = 1
2098 17:16:34.112204 10, 0x0, sum = 2
2099 17:16:34.115424 11, 0x0, sum = 3
2100 17:16:34.115518 12, 0x0, sum = 4
2101 17:16:34.118500 best_step = 10
2102 17:16:34.118663
2103 17:16:34.118789 ==
2104 17:16:34.122075 Dram Type= 6, Freq= 0, CH_1, rank 1
2105 17:16:34.125197 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2106 17:16:34.125290 ==
2107 17:16:34.128520 RX Vref Scan: 0
2108 17:16:34.128632
2109 17:16:34.128700 RX Vref 0 -> 0, step: 1
2110 17:16:34.128762
2111 17:16:34.131663 RX Delay -95 -> 252, step: 8
2112 17:16:34.138537 iDelay=217, Bit 0, Center 92 (-23 ~ 208) 232
2113 17:16:34.142059 iDelay=217, Bit 1, Center 80 (-31 ~ 192) 224
2114 17:16:34.145065 iDelay=217, Bit 2, Center 76 (-39 ~ 192) 232
2115 17:16:34.148282 iDelay=217, Bit 3, Center 88 (-23 ~ 200) 224
2116 17:16:34.151812 iDelay=217, Bit 4, Center 84 (-31 ~ 200) 232
2117 17:16:34.158417 iDelay=217, Bit 5, Center 96 (-15 ~ 208) 224
2118 17:16:34.162271 iDelay=217, Bit 6, Center 100 (-15 ~ 216) 232
2119 17:16:34.165116 iDelay=217, Bit 7, Center 84 (-31 ~ 200) 232
2120 17:16:34.168394 iDelay=217, Bit 8, Center 68 (-47 ~ 184) 232
2121 17:16:34.172034 iDelay=217, Bit 9, Center 68 (-47 ~ 184) 232
2122 17:16:34.178315 iDelay=217, Bit 10, Center 84 (-31 ~ 200) 232
2123 17:16:34.181612 iDelay=217, Bit 11, Center 72 (-39 ~ 184) 224
2124 17:16:34.184968 iDelay=217, Bit 12, Center 88 (-23 ~ 200) 224
2125 17:16:34.188627 iDelay=217, Bit 13, Center 88 (-23 ~ 200) 224
2126 17:16:34.195254 iDelay=217, Bit 14, Center 84 (-31 ~ 200) 232
2127 17:16:34.198460 iDelay=217, Bit 15, Center 92 (-23 ~ 208) 232
2128 17:16:34.198541 ==
2129 17:16:34.201868 Dram Type= 6, Freq= 0, CH_1, rank 1
2130 17:16:34.204875 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2131 17:16:34.204962 ==
2132 17:16:34.208598 DQS Delay:
2133 17:16:34.208673 DQS0 = 0, DQS1 = 0
2134 17:16:34.208737 DQM Delay:
2135 17:16:34.211676 DQM0 = 87, DQM1 = 80
2136 17:16:34.211753 DQ Delay:
2137 17:16:34.215274 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =88
2138 17:16:34.218147 DQ4 =84, DQ5 =96, DQ6 =100, DQ7 =84
2139 17:16:34.221555 DQ8 =68, DQ9 =68, DQ10 =84, DQ11 =72
2140 17:16:34.224734 DQ12 =88, DQ13 =88, DQ14 =84, DQ15 =92
2141 17:16:34.224814
2142 17:16:34.224879
2143 17:16:34.234614 [DQSOSCAuto] RK1, (LSB)MR18= 0x1a12, (MSB)MR19= 0x606, tDQSOscB0 = 405 ps tDQSOscB1 = 403 ps
2144 17:16:34.234708 CH1 RK1: MR19=606, MR18=1A12
2145 17:16:34.241485 CH1_RK1: MR19=0x606, MR18=0x1A12, DQSOSC=403, MR23=63, INC=90, DEC=60
2146 17:16:34.245155 [RxdqsGatingPostProcess] freq 800
2147 17:16:34.251570 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2148 17:16:34.254649 Pre-setting of DQS Precalculation
2149 17:16:34.258174 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2150 17:16:34.264707 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2151 17:16:34.274638 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2152 17:16:34.274720
2153 17:16:34.274786
2154 17:16:34.278304 [Calibration Summary] 1600 Mbps
2155 17:16:34.278382 CH 0, Rank 0
2156 17:16:34.281351 SW Impedance : PASS
2157 17:16:34.281431 DUTY Scan : NO K
2158 17:16:34.284743 ZQ Calibration : PASS
2159 17:16:34.288390 Jitter Meter : NO K
2160 17:16:34.288471 CBT Training : PASS
2161 17:16:34.291153 Write leveling : PASS
2162 17:16:34.291230 RX DQS gating : PASS
2163 17:16:34.294810 RX DQ/DQS(RDDQC) : PASS
2164 17:16:34.297893 TX DQ/DQS : PASS
2165 17:16:34.297980 RX DATLAT : PASS
2166 17:16:34.301586 RX DQ/DQS(Engine): PASS
2167 17:16:34.304626 TX OE : NO K
2168 17:16:34.304708 All Pass.
2169 17:16:34.304774
2170 17:16:34.304837 CH 0, Rank 1
2171 17:16:34.307859 SW Impedance : PASS
2172 17:16:34.311596 DUTY Scan : NO K
2173 17:16:34.311674 ZQ Calibration : PASS
2174 17:16:34.314750 Jitter Meter : NO K
2175 17:16:34.318190 CBT Training : PASS
2176 17:16:34.318278 Write leveling : PASS
2177 17:16:34.321184 RX DQS gating : PASS
2178 17:16:34.324762 RX DQ/DQS(RDDQC) : PASS
2179 17:16:34.324861 TX DQ/DQS : PASS
2180 17:16:34.327810 RX DATLAT : PASS
2181 17:16:34.331163 RX DQ/DQS(Engine): PASS
2182 17:16:34.331272 TX OE : NO K
2183 17:16:34.331366 All Pass.
2184 17:16:34.334815
2185 17:16:34.334922 CH 1, Rank 0
2186 17:16:34.337901 SW Impedance : PASS
2187 17:16:34.338018 DUTY Scan : NO K
2188 17:16:34.341274 ZQ Calibration : PASS
2189 17:16:34.341416 Jitter Meter : NO K
2190 17:16:34.344231
2191 17:16:34.344373 CBT Training : PASS
2192 17:16:34.347799 Write leveling : PASS
2193 17:16:34.347944 RX DQS gating : PASS
2194 17:16:34.350891 RX DQ/DQS(RDDQC) : PASS
2195 17:16:34.354445 TX DQ/DQS : PASS
2196 17:16:34.354615 RX DATLAT : PASS
2197 17:16:34.357545 RX DQ/DQS(Engine): PASS
2198 17:16:34.361228 TX OE : NO K
2199 17:16:34.361534 All Pass.
2200 17:16:34.361910
2201 17:16:34.362240 CH 1, Rank 1
2202 17:16:34.364493 SW Impedance : PASS
2203 17:16:34.367580 DUTY Scan : NO K
2204 17:16:34.367836 ZQ Calibration : PASS
2205 17:16:34.370761 Jitter Meter : NO K
2206 17:16:34.374346 CBT Training : PASS
2207 17:16:34.374631 Write leveling : PASS
2208 17:16:34.377877 RX DQS gating : PASS
2209 17:16:34.380941 RX DQ/DQS(RDDQC) : PASS
2210 17:16:34.381200 TX DQ/DQS : PASS
2211 17:16:34.384481 RX DATLAT : PASS
2212 17:16:34.387553 RX DQ/DQS(Engine): PASS
2213 17:16:34.387833 TX OE : NO K
2214 17:16:34.390613 All Pass.
2215 17:16:34.390865
2216 17:16:34.391070 DramC Write-DBI off
2217 17:16:34.394317 PER_BANK_REFRESH: Hybrid Mode
2218 17:16:34.394625 TX_TRACKING: ON
2219 17:16:34.397443 [GetDramInforAfterCalByMRR] Vendor 6.
2220 17:16:34.404308 [GetDramInforAfterCalByMRR] Revision 606.
2221 17:16:34.407402 [GetDramInforAfterCalByMRR] Revision 2 0.
2222 17:16:34.407490 MR0 0x3b3b
2223 17:16:34.407558 MR8 0x5151
2224 17:16:34.410796 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2225 17:16:34.410882
2226 17:16:34.413891 MR0 0x3b3b
2227 17:16:34.413966 MR8 0x5151
2228 17:16:34.417291 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2229 17:16:34.417416
2230 17:16:34.427120 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2231 17:16:34.430627 [FAST_K] Save calibration result to emmc
2232 17:16:34.433958 [FAST_K] Save calibration result to emmc
2233 17:16:34.437291 dram_init: config_dvfs: 1
2234 17:16:34.440204 dramc_set_vcore_voltage set vcore to 662500
2235 17:16:34.443647 Read voltage for 1200, 2
2236 17:16:34.443736 Vio18 = 0
2237 17:16:34.443807 Vcore = 662500
2238 17:16:34.447274 Vdram = 0
2239 17:16:34.447359 Vddq = 0
2240 17:16:34.447431 Vmddr = 0
2241 17:16:34.453829 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2242 17:16:34.457042 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2243 17:16:34.460493 MEM_TYPE=3, freq_sel=15
2244 17:16:34.463653 sv_algorithm_assistance_LP4_1600
2245 17:16:34.466767 ============ PULL DRAM RESETB DOWN ============
2246 17:16:34.470165 ========== PULL DRAM RESETB DOWN end =========
2247 17:16:34.477063 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2248 17:16:34.480252 ===================================
2249 17:16:34.480386 LPDDR4 DRAM CONFIGURATION
2250 17:16:34.483620 ===================================
2251 17:16:34.486811 EX_ROW_EN[0] = 0x0
2252 17:16:34.490308 EX_ROW_EN[1] = 0x0
2253 17:16:34.490412 LP4Y_EN = 0x0
2254 17:16:34.493479 WORK_FSP = 0x0
2255 17:16:34.493577 WL = 0x4
2256 17:16:34.496884 RL = 0x4
2257 17:16:34.496981 BL = 0x2
2258 17:16:34.500503 RPST = 0x0
2259 17:16:34.500616 RD_PRE = 0x0
2260 17:16:34.503952 WR_PRE = 0x1
2261 17:16:34.504051 WR_PST = 0x0
2262 17:16:34.507042 DBI_WR = 0x0
2263 17:16:34.507141 DBI_RD = 0x0
2264 17:16:34.510253 OTF = 0x1
2265 17:16:34.513386 ===================================
2266 17:16:34.516664 ===================================
2267 17:16:34.516754 ANA top config
2268 17:16:34.520019 ===================================
2269 17:16:34.523592 DLL_ASYNC_EN = 0
2270 17:16:34.526521 ALL_SLAVE_EN = 0
2271 17:16:34.530006 NEW_RANK_MODE = 1
2272 17:16:34.530105 DLL_IDLE_MODE = 1
2273 17:16:34.533423 LP45_APHY_COMB_EN = 1
2274 17:16:34.536717 TX_ODT_DIS = 1
2275 17:16:34.540079 NEW_8X_MODE = 1
2276 17:16:34.543115 ===================================
2277 17:16:34.546812 ===================================
2278 17:16:34.549728 data_rate = 2400
2279 17:16:34.549813 CKR = 1
2280 17:16:34.553252 DQ_P2S_RATIO = 8
2281 17:16:34.556415 ===================================
2282 17:16:34.559586 CA_P2S_RATIO = 8
2283 17:16:34.563351 DQ_CA_OPEN = 0
2284 17:16:34.566446 DQ_SEMI_OPEN = 0
2285 17:16:34.569948 CA_SEMI_OPEN = 0
2286 17:16:34.570037 CA_FULL_RATE = 0
2287 17:16:34.573327 DQ_CKDIV4_EN = 0
2288 17:16:34.576593 CA_CKDIV4_EN = 0
2289 17:16:34.579842 CA_PREDIV_EN = 0
2290 17:16:34.583298 PH8_DLY = 17
2291 17:16:34.586933 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2292 17:16:34.587054 DQ_AAMCK_DIV = 4
2293 17:16:34.589952 CA_AAMCK_DIV = 4
2294 17:16:34.593280 CA_ADMCK_DIV = 4
2295 17:16:34.596274 DQ_TRACK_CA_EN = 0
2296 17:16:34.599807 CA_PICK = 1200
2297 17:16:34.603186 CA_MCKIO = 1200
2298 17:16:34.606384 MCKIO_SEMI = 0
2299 17:16:34.606503 PLL_FREQ = 2366
2300 17:16:34.609903 DQ_UI_PI_RATIO = 32
2301 17:16:34.613006 CA_UI_PI_RATIO = 0
2302 17:16:34.616386 ===================================
2303 17:16:34.620216 ===================================
2304 17:16:34.623008 memory_type:LPDDR4
2305 17:16:34.623097 GP_NUM : 10
2306 17:16:34.626602 SRAM_EN : 1
2307 17:16:34.629509 MD32_EN : 0
2308 17:16:34.632852 ===================================
2309 17:16:34.632942 [ANA_INIT] >>>>>>>>>>>>>>
2310 17:16:34.636368 <<<<<< [CONFIGURE PHASE]: ANA_TX
2311 17:16:34.639848 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2312 17:16:34.642847 ===================================
2313 17:16:34.645851 data_rate = 2400,PCW = 0X5b00
2314 17:16:34.649218 ===================================
2315 17:16:34.652739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2316 17:16:34.659372 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2317 17:16:34.663011 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2318 17:16:34.669574 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2319 17:16:34.672712 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2320 17:16:34.675866 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2321 17:16:34.679465 [ANA_INIT] flow start
2322 17:16:34.679556 [ANA_INIT] PLL >>>>>>>>
2323 17:16:34.682452 [ANA_INIT] PLL <<<<<<<<
2324 17:16:34.686070 [ANA_INIT] MIDPI >>>>>>>>
2325 17:16:34.686161 [ANA_INIT] MIDPI <<<<<<<<
2326 17:16:34.689128 [ANA_INIT] DLL >>>>>>>>
2327 17:16:34.692258 [ANA_INIT] DLL <<<<<<<<
2328 17:16:34.692346 [ANA_INIT] flow end
2329 17:16:34.699208 ============ LP4 DIFF to SE enter ============
2330 17:16:34.702360 ============ LP4 DIFF to SE exit ============
2331 17:16:34.705634 [ANA_INIT] <<<<<<<<<<<<<
2332 17:16:34.705725 [Flow] Enable top DCM control >>>>>
2333 17:16:34.709225
2334 17:16:34.709311 [Flow] Enable top DCM control <<<<<
2335 17:16:34.712101
2336 17:16:34.712188 Enable DLL master slave shuffle
2337 17:16:34.719156 ==============================================================
2338 17:16:34.722314 Gating Mode config
2339 17:16:34.725710 ==============================================================
2340 17:16:34.728790 Config description:
2341 17:16:34.738779 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2342 17:16:34.745270 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2343 17:16:34.748922 SELPH_MODE 0: By rank 1: By Phase
2344 17:16:34.755846 ==============================================================
2345 17:16:34.758821 GAT_TRACK_EN = 1
2346 17:16:34.762060 RX_GATING_MODE = 2
2347 17:16:34.765718 RX_GATING_TRACK_MODE = 2
2348 17:16:34.765824 SELPH_MODE = 1
2349 17:16:34.768490 PICG_EARLY_EN = 1
2350 17:16:34.772155 VALID_LAT_VALUE = 1
2351 17:16:34.778708 ==============================================================
2352 17:16:34.781868 Enter into Gating configuration >>>>
2353 17:16:34.784945 Exit from Gating configuration <<<<
2354 17:16:34.788396 Enter into DVFS_PRE_config >>>>>
2355 17:16:34.798825 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2356 17:16:34.801827 Exit from DVFS_PRE_config <<<<<
2357 17:16:34.805325 Enter into PICG configuration >>>>
2358 17:16:34.808219 Exit from PICG configuration <<<<
2359 17:16:34.811800 [RX_INPUT] configuration >>>>>
2360 17:16:34.814772 [RX_INPUT] configuration <<<<<
2361 17:16:34.818161 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2362 17:16:34.825197 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2363 17:16:34.831719 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2364 17:16:34.838395 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2365 17:16:34.844532 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2366 17:16:34.847970 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2367 17:16:34.854959 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2368 17:16:34.857774 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2369 17:16:34.861301 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2370 17:16:34.864467 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2371 17:16:34.870895 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2372 17:16:34.874205 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2373 17:16:34.878013 ===================================
2374 17:16:34.881066 LPDDR4 DRAM CONFIGURATION
2375 17:16:34.884358 ===================================
2376 17:16:34.884441 EX_ROW_EN[0] = 0x0
2377 17:16:34.887908 EX_ROW_EN[1] = 0x0
2378 17:16:34.887991 LP4Y_EN = 0x0
2379 17:16:34.890898 WORK_FSP = 0x0
2380 17:16:34.890982 WL = 0x4
2381 17:16:34.894382 RL = 0x4
2382 17:16:34.894465 BL = 0x2
2383 17:16:34.897852 RPST = 0x0
2384 17:16:34.897935 RD_PRE = 0x0
2385 17:16:34.901340
2386 17:16:34.901437 WR_PRE = 0x1
2387 17:16:34.904093 WR_PST = 0x0
2388 17:16:34.904177 DBI_WR = 0x0
2389 17:16:34.907717 DBI_RD = 0x0
2390 17:16:34.907802 OTF = 0x1
2391 17:16:34.910935 ===================================
2392 17:16:34.914590 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2393 17:16:34.917495 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2394 17:16:34.920698
2395 17:16:34.924294 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2396 17:16:34.927330 ===================================
2397 17:16:34.930928 LPDDR4 DRAM CONFIGURATION
2398 17:16:34.934253 ===================================
2399 17:16:34.934342 EX_ROW_EN[0] = 0x10
2400 17:16:34.937758 EX_ROW_EN[1] = 0x0
2401 17:16:34.937847 LP4Y_EN = 0x0
2402 17:16:34.940699 WORK_FSP = 0x0
2403 17:16:34.940784 WL = 0x4
2404 17:16:34.944301 RL = 0x4
2405 17:16:34.944386 BL = 0x2
2406 17:16:34.947803 RPST = 0x0
2407 17:16:34.947886 RD_PRE = 0x0
2408 17:16:34.950557 WR_PRE = 0x1
2409 17:16:34.950641 WR_PST = 0x0
2410 17:16:34.954143
2411 17:16:34.954227 DBI_WR = 0x0
2412 17:16:34.957585 DBI_RD = 0x0
2413 17:16:34.957669 OTF = 0x1
2414 17:16:34.960539 ===================================
2415 17:16:34.967301 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2416 17:16:34.967388 ==
2417 17:16:34.970403 Dram Type= 6, Freq= 0, CH_0, rank 0
2418 17:16:34.974002 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2419 17:16:34.974092 ==
2420 17:16:34.977173 [Duty_Offset_Calibration]
2421 17:16:34.977257 B0:1 B1:-1 CA:0
2422 17:16:34.980269
2423 17:16:34.980353
2424 17:16:34.983955 [DutyScan_Calibration_Flow] k_type=0
2425 17:16:34.991720
2426 17:16:34.991805 ==CLK 0==
2427 17:16:34.994793 Final CLK duty delay cell = 0
2428 17:16:34.998390 [0] MAX Duty = 5094%(X100), DQS PI = 14
2429 17:16:35.001882 [0] MIN Duty = 4906%(X100), DQS PI = 8
2430 17:16:35.001967 [0] AVG Duty = 5000%(X100)
2431 17:16:35.004853
2432 17:16:35.008487 CH0 CLK Duty spec in!! Max-Min= 188%
2433 17:16:35.011535 [DutyScan_Calibration_Flow] ====Done====
2434 17:16:35.011623
2435 17:16:35.014656 [DutyScan_Calibration_Flow] k_type=1
2436 17:16:35.029304
2437 17:16:35.029399 ==DQS 0 ==
2438 17:16:35.032677 Final DQS duty delay cell = -4
2439 17:16:35.036391 [-4] MAX Duty = 5062%(X100), DQS PI = 16
2440 17:16:35.039287 [-4] MIN Duty = 4875%(X100), DQS PI = 56
2441 17:16:35.042887 [-4] AVG Duty = 4968%(X100)
2442 17:16:35.042973
2443 17:16:35.043040 ==DQS 1 ==
2444 17:16:35.045899 Final DQS duty delay cell = -4
2445 17:16:35.049558 [-4] MAX Duty = 5000%(X100), DQS PI = 6
2446 17:16:35.052469 [-4] MIN Duty = 4876%(X100), DQS PI = 20
2447 17:16:35.056071 [-4] AVG Duty = 4938%(X100)
2448 17:16:35.056157
2449 17:16:35.058923 CH0 DQS 0 Duty spec in!! Max-Min= 187%
2450 17:16:35.059009
2451 17:16:35.062373 CH0 DQS 1 Duty spec in!! Max-Min= 124%
2452 17:16:35.065611 [DutyScan_Calibration_Flow] ====Done====
2453 17:16:35.065696
2454 17:16:35.069218 [DutyScan_Calibration_Flow] k_type=3
2455 17:16:35.087241
2456 17:16:35.087328 ==DQM 0 ==
2457 17:16:35.090890 Final DQM duty delay cell = 0
2458 17:16:35.093926 [0] MAX Duty = 5062%(X100), DQS PI = 18
2459 17:16:35.097565 [0] MIN Duty = 4875%(X100), DQS PI = 6
2460 17:16:35.097652 [0] AVG Duty = 4968%(X100)
2461 17:16:35.100495
2462 17:16:35.100581
2463 17:16:35.100648 ==DQM 1 ==
2464 17:16:35.103807 Final DQM duty delay cell = 4
2465 17:16:35.107371 [4] MAX Duty = 5187%(X100), DQS PI = 14
2466 17:16:35.110262 [4] MIN Duty = 5000%(X100), DQS PI = 24
2467 17:16:35.113864 [4] AVG Duty = 5093%(X100)
2468 17:16:35.113950
2469 17:16:35.117083 CH0 DQM 0 Duty spec in!! Max-Min= 187%
2470 17:16:35.117186
2471 17:16:35.120599 CH0 DQM 1 Duty spec in!! Max-Min= 187%
2472 17:16:35.124112 [DutyScan_Calibration_Flow] ====Done====
2473 17:16:35.124197
2474 17:16:35.127391 [DutyScan_Calibration_Flow] k_type=2
2475 17:16:35.142568
2476 17:16:35.142655 ==DQ 0 ==
2477 17:16:35.145614 Final DQ duty delay cell = -4
2478 17:16:35.149088 [-4] MAX Duty = 5031%(X100), DQS PI = 22
2479 17:16:35.152479 [-4] MIN Duty = 4907%(X100), DQS PI = 0
2480 17:16:35.155483 [-4] AVG Duty = 4969%(X100)
2481 17:16:35.155568
2482 17:16:35.155636 ==DQ 1 ==
2483 17:16:35.158984 Final DQ duty delay cell = -4
2484 17:16:35.162099 [-4] MAX Duty = 5000%(X100), DQS PI = 54
2485 17:16:35.165600 [-4] MIN Duty = 4876%(X100), DQS PI = 16
2486 17:16:35.168737 [-4] AVG Duty = 4938%(X100)
2487 17:16:35.168823
2488 17:16:35.172267 CH0 DQ 0 Duty spec in!! Max-Min= 124%
2489 17:16:35.172353
2490 17:16:35.175351 CH0 DQ 1 Duty spec in!! Max-Min= 124%
2491 17:16:35.179278 [DutyScan_Calibration_Flow] ====Done====
2492 17:16:35.179364 ==
2493 17:16:35.182275 Dram Type= 6, Freq= 0, CH_1, rank 0
2494 17:16:35.185289 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2495 17:16:35.185413 ==
2496 17:16:35.188834 [Duty_Offset_Calibration]
2497 17:16:35.188919 B0:-1 B1:1 CA:1
2498 17:16:35.188986
2499 17:16:35.192563 [DutyScan_Calibration_Flow] k_type=0
2500 17:16:35.202866
2501 17:16:35.202952 ==CLK 0==
2502 17:16:35.206279 Final CLK duty delay cell = 0
2503 17:16:35.209442 [0] MAX Duty = 5187%(X100), DQS PI = 22
2504 17:16:35.212777 [0] MIN Duty = 4969%(X100), DQS PI = 60
2505 17:16:35.212862 [0] AVG Duty = 5078%(X100)
2506 17:16:35.216270
2507 17:16:35.219556 CH1 CLK Duty spec in!! Max-Min= 218%
2508 17:16:35.222947 [DutyScan_Calibration_Flow] ====Done====
2509 17:16:35.223033
2510 17:16:35.225879 [DutyScan_Calibration_Flow] k_type=1
2511 17:16:35.242454
2512 17:16:35.242589 ==DQS 0 ==
2513 17:16:35.245609 Final DQS duty delay cell = 0
2514 17:16:35.249222 [0] MAX Duty = 5156%(X100), DQS PI = 48
2515 17:16:35.252088 [0] MIN Duty = 4907%(X100), DQS PI = 6
2516 17:16:35.252238 [0] AVG Duty = 5031%(X100)
2517 17:16:35.255599
2518 17:16:35.255694 ==DQS 1 ==
2519 17:16:35.258692 Final DQS duty delay cell = 0
2520 17:16:35.261965 [0] MAX Duty = 5094%(X100), DQS PI = 12
2521 17:16:35.265273 [0] MIN Duty = 4969%(X100), DQS PI = 58
2522 17:16:35.268704 [0] AVG Duty = 5031%(X100)
2523 17:16:35.268791
2524 17:16:35.271885 CH1 DQS 0 Duty spec in!! Max-Min= 249%
2525 17:16:35.271971
2526 17:16:35.275345 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2527 17:16:35.278713 [DutyScan_Calibration_Flow] ====Done====
2528 17:16:35.278810
2529 17:16:35.281692 [DutyScan_Calibration_Flow] k_type=3
2530 17:16:35.298042
2531 17:16:35.298136 ==DQM 0 ==
2532 17:16:35.301366 Final DQM duty delay cell = -4
2533 17:16:35.304640 [-4] MAX Duty = 5062%(X100), DQS PI = 36
2534 17:16:35.308062 [-4] MIN Duty = 4876%(X100), DQS PI = 6
2535 17:16:35.311117 [-4] AVG Duty = 4969%(X100)
2536 17:16:35.311202
2537 17:16:35.311270 ==DQM 1 ==
2538 17:16:35.314594 Final DQM duty delay cell = 0
2539 17:16:35.318184 [0] MAX Duty = 5187%(X100), DQS PI = 6
2540 17:16:35.321248 [0] MIN Duty = 5000%(X100), DQS PI = 28
2541 17:16:35.324208 [0] AVG Duty = 5093%(X100)
2542 17:16:35.324294
2543 17:16:35.327878 CH1 DQM 0 Duty spec in!! Max-Min= 186%
2544 17:16:35.327964
2545 17:16:35.331256 CH1 DQM 1 Duty spec in!! Max-Min= 187%
2546 17:16:35.334262 [DutyScan_Calibration_Flow] ====Done====
2547 17:16:35.334357
2548 17:16:35.337918 [DutyScan_Calibration_Flow] k_type=2
2549 17:16:35.354673
2550 17:16:35.354760 ==DQ 0 ==
2551 17:16:35.358111 Final DQ duty delay cell = 0
2552 17:16:35.361300 [0] MAX Duty = 5187%(X100), DQS PI = 30
2553 17:16:35.364597 [0] MIN Duty = 4907%(X100), DQS PI = 8
2554 17:16:35.364684 [0] AVG Duty = 5047%(X100)
2555 17:16:35.367567
2556 17:16:35.367664 ==DQ 1 ==
2557 17:16:35.371149 Final DQ duty delay cell = 0
2558 17:16:35.374336 [0] MAX Duty = 5124%(X100), DQS PI = 10
2559 17:16:35.377895 [0] MIN Duty = 4969%(X100), DQS PI = 0
2560 17:16:35.377974 [0] AVG Duty = 5046%(X100)
2561 17:16:35.378039
2562 17:16:35.381143 CH1 DQ 0 Duty spec in!! Max-Min= 280%
2563 17:16:35.384112
2564 17:16:35.387868 CH1 DQ 1 Duty spec in!! Max-Min= 155%
2565 17:16:35.390850 [DutyScan_Calibration_Flow] ====Done====
2566 17:16:35.394594 nWR fixed to 30
2567 17:16:35.394680 [ModeRegInit_LP4] CH0 RK0
2568 17:16:35.397580 [ModeRegInit_LP4] CH0 RK1
2569 17:16:35.401183 [ModeRegInit_LP4] CH1 RK0
2570 17:16:35.401268 [ModeRegInit_LP4] CH1 RK1
2571 17:16:35.404198
2572 17:16:35.404283 match AC timing 7
2573 17:16:35.407582 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2574 17:16:35.411192 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2575 17:16:35.417760 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2576 17:16:35.420833 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2577 17:16:35.427796 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2578 17:16:35.427882 ==
2579 17:16:35.430952 Dram Type= 6, Freq= 0, CH_0, rank 0
2580 17:16:35.434147 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2581 17:16:35.434233 ==
2582 17:16:35.441174 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2583 17:16:35.444222 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=25, u1VrefScanEnd=35
2584 17:16:35.447626
2585 17:16:35.454735 [CA 0] Center 39 (9~70) winsize 62
2586 17:16:35.457690 [CA 1] Center 39 (9~69) winsize 61
2587 17:16:35.461068 [CA 2] Center 35 (5~66) winsize 62
2588 17:16:35.464587 [CA 3] Center 35 (5~66) winsize 62
2589 17:16:35.467640 [CA 4] Center 33 (4~63) winsize 60
2590 17:16:35.471052 [CA 5] Center 33 (3~63) winsize 61
2591 17:16:35.471138
2592 17:16:35.474314 [CmdBusTrainingLP45] Vref(ca) range 1: 33
2593 17:16:35.474399
2594 17:16:35.478185 [CATrainingPosCal] consider 1 rank data
2595 17:16:35.480836 u2DelayCellTimex100 = 270/100 ps
2596 17:16:35.484237 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2597 17:16:35.488046 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2598 17:16:35.494447 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2599 17:16:35.497491 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2600 17:16:35.501068 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2601 17:16:35.504788 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2602 17:16:35.504873
2603 17:16:35.507830 CA PerBit enable=1, Macro0, CA PI delay=33
2604 17:16:35.507916
2605 17:16:35.510948 [CBTSetCACLKResult] CA Dly = 33
2606 17:16:35.511034 CS Dly: 8 (0~39)
2607 17:16:35.511101 ==
2608 17:16:35.514601
2609 17:16:35.514686 Dram Type= 6, Freq= 0, CH_0, rank 1
2610 17:16:35.520985 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2611 17:16:35.521071 ==
2612 17:16:35.524374 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2613 17:16:35.530792 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
2614 17:16:35.540244 [CA 0] Center 39 (9~70) winsize 62
2615 17:16:35.543701 [CA 1] Center 39 (9~70) winsize 62
2616 17:16:35.547156 [CA 2] Center 35 (5~66) winsize 62
2617 17:16:35.550050 [CA 3] Center 34 (4~65) winsize 62
2618 17:16:35.553582 [CA 4] Center 33 (3~64) winsize 62
2619 17:16:35.557286 [CA 5] Center 33 (3~63) winsize 61
2620 17:16:35.557393
2621 17:16:35.560303 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2622 17:16:35.560390
2623 17:16:35.563230 [CATrainingPosCal] consider 2 rank data
2624 17:16:35.566751 u2DelayCellTimex100 = 270/100 ps
2625 17:16:35.569846 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2626 17:16:35.573295 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2627 17:16:35.580278 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2628 17:16:35.583361 CA3 delay=35 (5~65),Diff = 2 PI (9 cell)
2629 17:16:35.586903 CA4 delay=33 (4~63),Diff = 0 PI (0 cell)
2630 17:16:35.589869 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
2631 17:16:35.589954
2632 17:16:35.593527 CA PerBit enable=1, Macro0, CA PI delay=33
2633 17:16:35.593612
2634 17:16:35.596507 [CBTSetCACLKResult] CA Dly = 33
2635 17:16:35.596593 CS Dly: 9 (0~41)
2636 17:16:35.596660
2637 17:16:35.600269 ----->DramcWriteLeveling(PI) begin...
2638 17:16:35.603307 ==
2639 17:16:35.606446 Dram Type= 6, Freq= 0, CH_0, rank 0
2640 17:16:35.609914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2641 17:16:35.610000 ==
2642 17:16:35.613051 Write leveling (Byte 0): 33 => 33
2643 17:16:35.616556 Write leveling (Byte 1): 29 => 29
2644 17:16:35.620100 DramcWriteLeveling(PI) end<-----
2645 17:16:35.620185
2646 17:16:35.620252 ==
2647 17:16:35.623142 Dram Type= 6, Freq= 0, CH_0, rank 0
2648 17:16:35.626469 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2649 17:16:35.626554 ==
2650 17:16:35.629615 [Gating] SW mode calibration
2651 17:16:35.636667 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2652 17:16:35.643206 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2653 17:16:35.646672 0 15 0 | B1->B0 | 2323 3333 | 0 0 | (0 0) (0 0)
2654 17:16:35.649707 0 15 4 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
2655 17:16:35.653209 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2656 17:16:35.656311
2657 17:16:35.659845 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2658 17:16:35.663135 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2659 17:16:35.666275 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2660 17:16:35.673205 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2661 17:16:35.676214 0 15 28 | B1->B0 | 3434 3030 | 1 0 | (1 1) (0 1)
2662 17:16:35.679854 1 0 0 | B1->B0 | 3333 2323 | 0 0 | (0 0) (0 0)
2663 17:16:35.686523 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2664 17:16:35.689565 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2665 17:16:35.693169 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2666 17:16:35.699895 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2667 17:16:35.703243 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2668 17:16:35.706312 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2669 17:16:35.713175 1 0 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
2670 17:16:35.716128 1 1 0 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2671 17:16:35.719613 1 1 4 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
2672 17:16:35.726185 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2673 17:16:35.729822 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2674 17:16:35.733065 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2675 17:16:35.739308 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2676 17:16:35.742596 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2677 17:16:35.746176 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2678 17:16:35.752556 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2679 17:16:35.756040 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2680 17:16:35.759516 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2681 17:16:35.765824 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2682 17:16:35.769205 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2683 17:16:35.772359 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2684 17:16:35.779218 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2685 17:16:35.782395 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2686 17:16:35.786005 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2687 17:16:35.792850 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2688 17:16:35.796027 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2689 17:16:35.799149 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2690 17:16:35.802749 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2691 17:16:35.809472 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2692 17:16:35.812959 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2693 17:16:35.815818 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
2694 17:16:35.822867 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2695 17:16:35.825770 Total UI for P1: 0, mck2ui 16
2696 17:16:35.829521 best dqsien dly found for B0: ( 1, 3, 28)
2697 17:16:35.832479 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2698 17:16:35.835903 1 4 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2699 17:16:35.839551 Total UI for P1: 0, mck2ui 16
2700 17:16:35.842542 best dqsien dly found for B1: ( 1, 4, 0)
2701 17:16:35.845746 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
2702 17:16:35.849199 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2703 17:16:35.849284
2704 17:16:35.856251 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
2705 17:16:35.859114 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2706 17:16:35.859200 [Gating] SW calibration Done
2707 17:16:35.862843 ==
2708 17:16:35.862928 Dram Type= 6, Freq= 0, CH_0, rank 0
2709 17:16:35.865621
2710 17:16:35.869245 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2711 17:16:35.869372 ==
2712 17:16:35.869443 RX Vref Scan: 0
2713 17:16:35.869506
2714 17:16:35.872181 RX Vref 0 -> 0, step: 1
2715 17:16:35.872266
2716 17:16:35.875670 RX Delay -40 -> 252, step: 8
2717 17:16:35.879208 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
2718 17:16:35.882370 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2719 17:16:35.886025 iDelay=200, Bit 2, Center 115 (40 ~ 191) 152
2720 17:16:35.892457 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
2721 17:16:35.895502 iDelay=200, Bit 4, Center 123 (48 ~ 199) 152
2722 17:16:35.899136 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2723 17:16:35.902352 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2724 17:16:35.905855 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2725 17:16:35.912300 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2726 17:16:35.915969 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2727 17:16:35.918884 iDelay=200, Bit 10, Center 107 (32 ~ 183) 152
2728 17:16:35.922308 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2729 17:16:35.925843 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
2730 17:16:35.932566 iDelay=200, Bit 13, Center 111 (40 ~ 183) 144
2731 17:16:35.935590 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2732 17:16:35.939133 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
2733 17:16:35.939218 ==
2734 17:16:35.942391 Dram Type= 6, Freq= 0, CH_0, rank 0
2735 17:16:35.945303 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2736 17:16:35.948876 ==
2737 17:16:35.948961 DQS Delay:
2738 17:16:35.949028 DQS0 = 0, DQS1 = 0
2739 17:16:35.952151 DQM Delay:
2740 17:16:35.952236 DQM0 = 119, DQM1 = 106
2741 17:16:35.955807 DQ Delay:
2742 17:16:35.958692 DQ0 =119, DQ1 =119, DQ2 =115, DQ3 =115
2743 17:16:35.962142 DQ4 =123, DQ5 =111, DQ6 =127, DQ7 =127
2744 17:16:35.965586 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2745 17:16:35.968643 DQ12 =111, DQ13 =111, DQ14 =119, DQ15 =111
2746 17:16:35.968728
2747 17:16:35.968796
2748 17:16:35.968858 ==
2749 17:16:35.972149 Dram Type= 6, Freq= 0, CH_0, rank 0
2750 17:16:35.975257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2751 17:16:35.975343 ==
2752 17:16:35.975410
2753 17:16:35.975472
2754 17:16:35.978831 TX Vref Scan disable
2755 17:16:35.981884 == TX Byte 0 ==
2756 17:16:35.985571 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2757 17:16:35.988689 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2758 17:16:35.991790 == TX Byte 1 ==
2759 17:16:35.995347 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2760 17:16:35.998484 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2761 17:16:35.998569 ==
2762 17:16:36.002182 Dram Type= 6, Freq= 0, CH_0, rank 0
2763 17:16:36.005219 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2764 17:16:36.008395
2765 17:16:36.008481 ==
2766 17:16:36.019206 TX Vref=22, minBit 5, minWin=25, winSum=418
2767 17:16:36.022233 TX Vref=24, minBit 13, minWin=25, winSum=423
2768 17:16:36.025778 TX Vref=26, minBit 4, minWin=26, winSum=428
2769 17:16:36.028724 TX Vref=28, minBit 10, minWin=26, winSum=434
2770 17:16:36.032216 TX Vref=30, minBit 1, minWin=26, winSum=430
2771 17:16:36.038819 TX Vref=32, minBit 4, minWin=26, winSum=430
2772 17:16:36.042405 [TxChooseVref] Worse bit 10, Min win 26, Win sum 434, Final Vref 28
2773 17:16:36.042491
2774 17:16:36.045303 Final TX Range 1 Vref 28
2775 17:16:36.045426
2776 17:16:36.045494 ==
2777 17:16:36.048643 Dram Type= 6, Freq= 0, CH_0, rank 0
2778 17:16:36.052092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2779 17:16:36.055679 ==
2780 17:16:36.055764
2781 17:16:36.055832
2782 17:16:36.055893 TX Vref Scan disable
2783 17:16:36.058952 == TX Byte 0 ==
2784 17:16:36.062566 Update DQ dly =851 (3 ,2, 19) DQ OEN =(2 ,7)
2785 17:16:36.065953 Update DQM dly =851 (3 ,2, 19) DQM OEN =(2 ,7)
2786 17:16:36.068827
2787 17:16:36.068912 == TX Byte 1 ==
2788 17:16:36.072259 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
2789 17:16:36.078906 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
2790 17:16:36.078992
2791 17:16:36.079059 [DATLAT]
2792 17:16:36.079122 Freq=1200, CH0 RK0
2793 17:16:36.079183
2794 17:16:36.082228 DATLAT Default: 0xd
2795 17:16:36.082313 0, 0xFFFF, sum = 0
2796 17:16:36.085937 1, 0xFFFF, sum = 0
2797 17:16:36.086024 2, 0xFFFF, sum = 0
2798 17:16:36.089124 3, 0xFFFF, sum = 0
2799 17:16:36.092129 4, 0xFFFF, sum = 0
2800 17:16:36.092215 5, 0xFFFF, sum = 0
2801 17:16:36.095610 6, 0xFFFF, sum = 0
2802 17:16:36.095697 7, 0xFFFF, sum = 0
2803 17:16:36.098854 8, 0xFFFF, sum = 0
2804 17:16:36.098941 9, 0xFFFF, sum = 0
2805 17:16:36.102016 10, 0xFFFF, sum = 0
2806 17:16:36.102133 11, 0xFFFF, sum = 0
2807 17:16:36.105524 12, 0x0, sum = 1
2808 17:16:36.105610 13, 0x0, sum = 2
2809 17:16:36.108541 14, 0x0, sum = 3
2810 17:16:36.108628 15, 0x0, sum = 4
2811 17:16:36.112282 best_step = 13
2812 17:16:36.112367
2813 17:16:36.112435 ==
2814 17:16:36.115416 Dram Type= 6, Freq= 0, CH_0, rank 0
2815 17:16:36.118836 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2816 17:16:36.118924 ==
2817 17:16:36.118990 RX Vref Scan: 1
2818 17:16:36.119053
2819 17:16:36.121922
2820 17:16:36.122007 Set Vref Range= 32 -> 127
2821 17:16:36.122074
2822 17:16:36.124821 RX Vref 32 -> 127, step: 1
2823 17:16:36.124906
2824 17:16:36.128299 RX Delay -21 -> 252, step: 4
2825 17:16:36.128384
2826 17:16:36.131843 Set Vref, RX VrefLevel [Byte0]: 32
2827 17:16:36.134924 [Byte1]: 32
2828 17:16:36.135009
2829 17:16:36.138474 Set Vref, RX VrefLevel [Byte0]: 33
2830 17:16:36.141434 [Byte1]: 33
2831 17:16:36.145449
2832 17:16:36.145535 Set Vref, RX VrefLevel [Byte0]: 34
2833 17:16:36.149089 [Byte1]: 34
2834 17:16:36.153761
2835 17:16:36.153846 Set Vref, RX VrefLevel [Byte0]: 35
2836 17:16:36.157193 [Byte1]: 35
2837 17:16:36.161253
2838 17:16:36.161354 Set Vref, RX VrefLevel [Byte0]: 36
2839 17:16:36.164755 [Byte1]: 36
2840 17:16:36.169237
2841 17:16:36.169328 Set Vref, RX VrefLevel [Byte0]: 37
2842 17:16:36.172706 [Byte1]: 37
2843 17:16:36.177265
2844 17:16:36.177390 Set Vref, RX VrefLevel [Byte0]: 38
2845 17:16:36.180941 [Byte1]: 38
2846 17:16:36.185446
2847 17:16:36.185539 Set Vref, RX VrefLevel [Byte0]: 39
2848 17:16:36.188687 [Byte1]: 39
2849 17:16:36.193223
2850 17:16:36.193317 Set Vref, RX VrefLevel [Byte0]: 40
2851 17:16:36.196290 [Byte1]: 40
2852 17:16:36.201055
2853 17:16:36.201141 Set Vref, RX VrefLevel [Byte0]: 41
2854 17:16:36.204136 [Byte1]: 41
2855 17:16:36.208825
2856 17:16:36.208910 Set Vref, RX VrefLevel [Byte0]: 42
2857 17:16:36.212435 [Byte1]: 42
2858 17:16:36.217110
2859 17:16:36.217198 Set Vref, RX VrefLevel [Byte0]: 43
2860 17:16:36.220375 [Byte1]: 43
2861 17:16:36.224598
2862 17:16:36.224684 Set Vref, RX VrefLevel [Byte0]: 44
2863 17:16:36.228129 [Byte1]: 44
2864 17:16:36.232738
2865 17:16:36.232823 Set Vref, RX VrefLevel [Byte0]: 45
2866 17:16:36.236367 [Byte1]: 45
2867 17:16:36.240404
2868 17:16:36.240518 Set Vref, RX VrefLevel [Byte0]: 46
2869 17:16:36.243888 [Byte1]: 46
2870 17:16:36.248615
2871 17:16:36.248700 Set Vref, RX VrefLevel [Byte0]: 47
2872 17:16:36.252048 [Byte1]: 47
2873 17:16:36.256711
2874 17:16:36.256848 Set Vref, RX VrefLevel [Byte0]: 48
2875 17:16:36.259639 [Byte1]: 48
2876 17:16:36.264732
2877 17:16:36.264842 Set Vref, RX VrefLevel [Byte0]: 49
2878 17:16:36.267690 [Byte1]: 49
2879 17:16:36.272629
2880 17:16:36.272735 Set Vref, RX VrefLevel [Byte0]: 50
2881 17:16:36.275848 [Byte1]: 50
2882 17:16:36.280291
2883 17:16:36.280383 Set Vref, RX VrefLevel [Byte0]: 51
2884 17:16:36.283668 [Byte1]: 51
2885 17:16:36.288263
2886 17:16:36.288360 Set Vref, RX VrefLevel [Byte0]: 52
2887 17:16:36.291317 [Byte1]: 52
2888 17:16:36.295990
2889 17:16:36.296079 Set Vref, RX VrefLevel [Byte0]: 53
2890 17:16:36.299675 [Byte1]: 53
2891 17:16:36.304411
2892 17:16:36.304501 Set Vref, RX VrefLevel [Byte0]: 54
2893 17:16:36.307493 [Byte1]: 54
2894 17:16:36.312155
2895 17:16:36.312255 Set Vref, RX VrefLevel [Byte0]: 55
2896 17:16:36.315226 [Byte1]: 55
2897 17:16:36.319814
2898 17:16:36.319922 Set Vref, RX VrefLevel [Byte0]: 56
2899 17:16:36.323295 [Byte1]: 56
2900 17:16:36.326371
2901 17:16:36.326482
2902 17:16:36.329887 Set Vref, RX VrefLevel [Byte0]: 57
2903 17:16:36.332869 [Byte1]: 57
2904 17:16:36.332974
2905 17:16:36.336313 Set Vref, RX VrefLevel [Byte0]: 58
2906 17:16:36.339444 [Byte1]: 58
2907 17:16:36.343774
2908 17:16:36.343866 Set Vref, RX VrefLevel [Byte0]: 59
2909 17:16:36.346824 [Byte1]: 59
2910 17:16:36.351907
2911 17:16:36.351986 Set Vref, RX VrefLevel [Byte0]: 60
2912 17:16:36.354942 [Byte1]: 60
2913 17:16:36.359416
2914 17:16:36.359559 Set Vref, RX VrefLevel [Byte0]: 61
2915 17:16:36.366974 [Byte1]: 61
2916 17:16:36.367574
2917 17:16:36.367655 Set Vref, RX VrefLevel [Byte0]: 62
2918 17:16:36.370810 [Byte1]: 62
2919 17:16:36.375625
2920 17:16:36.375709 Set Vref, RX VrefLevel [Byte0]: 63
2921 17:16:36.378707 [Byte1]: 63
2922 17:16:36.383150
2923 17:16:36.383231 Set Vref, RX VrefLevel [Byte0]: 64
2924 17:16:36.386790 [Byte1]: 64
2925 17:16:36.391150
2926 17:16:36.391229 Set Vref, RX VrefLevel [Byte0]: 65
2927 17:16:36.394523 [Byte1]: 65
2928 17:16:36.399149
2929 17:16:36.399315 Set Vref, RX VrefLevel [Byte0]: 66
2930 17:16:36.402211 [Byte1]: 66
2931 17:16:36.406841
2932 17:16:36.406977 Set Vref, RX VrefLevel [Byte0]: 67
2933 17:16:36.410311 [Byte1]: 67
2934 17:16:36.414805
2935 17:16:36.414914 Set Vref, RX VrefLevel [Byte0]: 68
2936 17:16:36.418219 [Byte1]: 68
2937 17:16:36.423053
2938 17:16:36.423164 Set Vref, RX VrefLevel [Byte0]: 69
2939 17:16:36.426121 [Byte1]: 69
2940 17:16:36.430777
2941 17:16:36.430882 Set Vref, RX VrefLevel [Byte0]: 70
2942 17:16:36.434015 [Byte1]: 70
2943 17:16:36.438827
2944 17:16:36.438929 Set Vref, RX VrefLevel [Byte0]: 71
2945 17:16:36.441863 [Byte1]: 71
2946 17:16:36.446665
2947 17:16:36.446770 Set Vref, RX VrefLevel [Byte0]: 72
2948 17:16:36.449879 [Byte1]: 72
2949 17:16:36.454978
2950 17:16:36.455088 Set Vref, RX VrefLevel [Byte0]: 73
2951 17:16:36.458235 [Byte1]: 73
2952 17:16:36.462482
2953 17:16:36.462599 Set Vref, RX VrefLevel [Byte0]: 74
2954 17:16:36.465850 [Byte1]: 74
2955 17:16:36.470603
2956 17:16:36.470717 Set Vref, RX VrefLevel [Byte0]: 75
2957 17:16:36.473990 [Byte1]: 75
2958 17:16:36.478358
2959 17:16:36.478465 Set Vref, RX VrefLevel [Byte0]: 76
2960 17:16:36.481875 [Byte1]: 76
2961 17:16:36.486551
2962 17:16:36.486659 Set Vref, RX VrefLevel [Byte0]: 77
2963 17:16:36.489434 [Byte1]: 77
2964 17:16:36.494389
2965 17:16:36.494498 Set Vref, RX VrefLevel [Byte0]: 78
2966 17:16:36.497254 [Byte1]: 78
2967 17:16:36.502339
2968 17:16:36.502446 Set Vref, RX VrefLevel [Byte0]: 79
2969 17:16:36.505802 [Byte1]: 79
2970 17:16:36.509890
2971 17:16:36.510004 Final RX Vref Byte 0 = 57 to rank0
2972 17:16:36.513460 Final RX Vref Byte 1 = 47 to rank0
2973 17:16:36.516825 Final RX Vref Byte 0 = 57 to rank1
2974 17:16:36.519863 Final RX Vref Byte 1 = 47 to rank1==
2975 17:16:36.523480 Dram Type= 6, Freq= 0, CH_0, rank 0
2976 17:16:36.530027 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2977 17:16:36.530138 ==
2978 17:16:36.530233 DQS Delay:
2979 17:16:36.530326 DQS0 = 0, DQS1 = 0
2980 17:16:36.533151
2981 17:16:36.533257 DQM Delay:
2982 17:16:36.533355 DQM0 = 119, DQM1 = 105
2983 17:16:36.536465 DQ Delay:
2984 17:16:36.539787 DQ0 =118, DQ1 =120, DQ2 =116, DQ3 =114
2985 17:16:36.543444 DQ4 =120, DQ5 =110, DQ6 =126, DQ7 =128
2986 17:16:36.546330 DQ8 =94, DQ9 =92, DQ10 =108, DQ11 =98
2987 17:16:36.549623 DQ12 =112, DQ13 =108, DQ14 =118, DQ15 =116
2988 17:16:36.549726
2989 17:16:36.549818
2990 17:16:36.559549 [DQSOSCAuto] RK0, (LSB)MR18= 0xdf9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 405 ps
2991 17:16:36.559661 CH0 RK0: MR19=403, MR18=DF9
2992 17:16:36.566345 CH0_RK0: MR19=0x403, MR18=0xDF9, DQSOSC=405, MR23=63, INC=39, DEC=26
2993 17:16:36.566459
2994 17:16:36.569715 ----->DramcWriteLeveling(PI) begin...
2995 17:16:36.569829 ==
2996 17:16:36.572825 Dram Type= 6, Freq= 0, CH_0, rank 1
2997 17:16:36.576135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2998 17:16:36.579556 ==
2999 17:16:36.579666 Write leveling (Byte 0): 33 => 33
3000 17:16:36.582990 Write leveling (Byte 1): 30 => 30
3001 17:16:36.586480 DramcWriteLeveling(PI) end<-----
3002 17:16:36.586592
3003 17:16:36.586687 ==
3004 17:16:36.589467 Dram Type= 6, Freq= 0, CH_0, rank 1
3005 17:16:36.596526 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3006 17:16:36.596639 ==
3007 17:16:36.596735 [Gating] SW mode calibration
3008 17:16:36.599437
3009 17:16:36.606166 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3010 17:16:36.609843 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3011 17:16:36.616409 0 15 0 | B1->B0 | 2323 3131 | 0 0 | (0 0) (0 0)
3012 17:16:36.619886 0 15 4 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3013 17:16:36.622741 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3014 17:16:36.626057 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3015 17:16:36.629695
3016 17:16:36.632652 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3017 17:16:36.636264 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3018 17:16:36.639281 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3019 17:16:36.642610
3020 17:16:36.646331 0 15 28 | B1->B0 | 3434 3333 | 1 0 | (1 1) (0 1)
3021 17:16:36.649592 1 0 0 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
3022 17:16:36.652619 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3023 17:16:36.659555 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3024 17:16:36.662671 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3025 17:16:36.665760 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3026 17:16:36.672976 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3027 17:16:36.675932 1 0 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3028 17:16:36.679548 1 0 28 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
3029 17:16:36.685623 1 1 0 | B1->B0 | 3232 4545 | 0 0 | (0 0) (0 0)
3030 17:16:36.689301 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3031 17:16:36.692532 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3032 17:16:36.698899 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3033 17:16:36.702605 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3034 17:16:36.706006 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3035 17:16:36.712235 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3036 17:16:36.715759 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3037 17:16:36.718900 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3038 17:16:36.725390 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3039 17:16:36.728722 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3040 17:16:36.732193 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3041 17:16:36.738842 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3042 17:16:36.742008 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3043 17:16:36.745412 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3044 17:16:36.752024 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3045 17:16:36.755253 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3046 17:16:36.758861 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3047 17:16:36.765528 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3048 17:16:36.768646 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3049 17:16:36.771914 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3050 17:16:36.778793 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3051 17:16:36.782086 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3052 17:16:36.785319 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3053 17:16:36.791999 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3054 17:16:36.795011 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3055 17:16:36.798826 Total UI for P1: 0, mck2ui 16
3056 17:16:36.802151 best dqsien dly found for B0: ( 1, 3, 28)
3057 17:16:36.805327 Total UI for P1: 0, mck2ui 16
3058 17:16:36.808710 best dqsien dly found for B1: ( 1, 4, 0)
3059 17:16:36.811866 best DQS0 dly(MCK, UI, PI) = (1, 3, 28)
3060 17:16:36.815418 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
3061 17:16:36.815529
3062 17:16:36.818464 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 28)
3063 17:16:36.821875 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
3064 17:16:36.825259 [Gating] SW calibration Done
3065 17:16:36.825404 ==
3066 17:16:36.828457 Dram Type= 6, Freq= 0, CH_0, rank 1
3067 17:16:36.831849 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3068 17:16:36.831962 ==
3069 17:16:36.835308 RX Vref Scan: 0
3070 17:16:36.835418
3071 17:16:36.835516 RX Vref 0 -> 0, step: 1
3072 17:16:36.838864
3073 17:16:36.838975 RX Delay -40 -> 252, step: 8
3074 17:16:36.845311 iDelay=200, Bit 0, Center 115 (48 ~ 183) 136
3075 17:16:36.848442 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
3076 17:16:36.851765 iDelay=200, Bit 2, Center 111 (40 ~ 183) 144
3077 17:16:36.855132 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3078 17:16:36.858216 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
3079 17:16:36.865192 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
3080 17:16:36.868243 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
3081 17:16:36.871526 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
3082 17:16:36.874908 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
3083 17:16:36.878391 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
3084 17:16:36.881647 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3085 17:16:36.888264 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
3086 17:16:36.891640 iDelay=200, Bit 12, Center 111 (40 ~ 183) 144
3087 17:16:36.894742 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3088 17:16:36.898006 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3089 17:16:36.904560 iDelay=200, Bit 15, Center 111 (40 ~ 183) 144
3090 17:16:36.904665 ==
3091 17:16:36.907951 Dram Type= 6, Freq= 0, CH_0, rank 1
3092 17:16:36.911116 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3093 17:16:36.911223 ==
3094 17:16:36.911315 DQS Delay:
3095 17:16:36.914665 DQS0 = 0, DQS1 = 0
3096 17:16:36.914773 DQM Delay:
3097 17:16:36.917743 DQM0 = 118, DQM1 = 108
3098 17:16:36.917849 DQ Delay:
3099 17:16:36.921295 DQ0 =115, DQ1 =119, DQ2 =111, DQ3 =115
3100 17:16:36.924381 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =127
3101 17:16:36.927964 DQ8 =95, DQ9 =95, DQ10 =111, DQ11 =103
3102 17:16:36.931339 DQ12 =111, DQ13 =119, DQ14 =119, DQ15 =111
3103 17:16:36.931449
3104 17:16:36.931543
3105 17:16:36.934645 ==
3106 17:16:36.937775 Dram Type= 6, Freq= 0, CH_0, rank 1
3107 17:16:36.941058 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3108 17:16:36.941169 ==
3109 17:16:36.941264
3110 17:16:36.941398
3111 17:16:36.944298 TX Vref Scan disable
3112 17:16:36.944405 == TX Byte 0 ==
3113 17:16:36.947675 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3114 17:16:36.954117 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3115 17:16:36.954222 == TX Byte 1 ==
3116 17:16:36.957916 Update DQ dly =846 (3 ,2, 14) DQ OEN =(2 ,7)
3117 17:16:36.961360
3118 17:16:36.964174 Update DQM dly =846 (3 ,2, 14) DQM OEN =(2 ,7)
3119 17:16:36.964277 ==
3120 17:16:36.967763 Dram Type= 6, Freq= 0, CH_0, rank 1
3121 17:16:36.971253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3122 17:16:36.971358 ==
3123 17:16:36.983491 TX Vref=22, minBit 14, minWin=25, winSum=420
3124 17:16:36.987339 TX Vref=24, minBit 1, minWin=26, winSum=424
3125 17:16:36.989877 TX Vref=26, minBit 1, minWin=26, winSum=430
3126 17:16:36.993262 TX Vref=28, minBit 13, minWin=25, winSum=431
3127 17:16:36.996964 TX Vref=30, minBit 10, minWin=26, winSum=432
3128 17:16:37.003299 TX Vref=32, minBit 10, minWin=26, winSum=430
3129 17:16:37.006766 [TxChooseVref] Worse bit 10, Min win 26, Win sum 432, Final Vref 30
3130 17:16:37.006913
3131 17:16:37.009827 Final TX Range 1 Vref 30
3132 17:16:37.009937
3133 17:16:37.010029 ==
3134 17:16:37.013227 Dram Type= 6, Freq= 0, CH_0, rank 1
3135 17:16:37.016793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3136 17:16:37.019797 ==
3137 17:16:37.019910
3138 17:16:37.020013
3139 17:16:37.020117 TX Vref Scan disable
3140 17:16:37.023407 == TX Byte 0 ==
3141 17:16:37.026744 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3142 17:16:37.030397 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3143 17:16:37.033644 == TX Byte 1 ==
3144 17:16:37.036822 Update DQ dly =847 (3 ,2, 15) DQ OEN =(2 ,7)
3145 17:16:37.040069 Update DQM dly =847 (3 ,2, 15) DQM OEN =(2 ,7)
3146 17:16:37.043702
3147 17:16:37.043815 [DATLAT]
3148 17:16:37.043914 Freq=1200, CH0 RK1
3149 17:16:37.044010
3150 17:16:37.047349 DATLAT Default: 0xd
3151 17:16:37.047460 0, 0xFFFF, sum = 0
3152 17:16:37.050118 1, 0xFFFF, sum = 0
3153 17:16:37.050231 2, 0xFFFF, sum = 0
3154 17:16:37.053631 3, 0xFFFF, sum = 0
3155 17:16:37.053746 4, 0xFFFF, sum = 0
3156 17:16:37.056631 5, 0xFFFF, sum = 0
3157 17:16:37.056745 6, 0xFFFF, sum = 0
3158 17:16:37.060047
3159 17:16:37.060178 7, 0xFFFF, sum = 0
3160 17:16:37.063470 8, 0xFFFF, sum = 0
3161 17:16:37.063580 9, 0xFFFF, sum = 0
3162 17:16:37.066764 10, 0xFFFF, sum = 0
3163 17:16:37.066869 11, 0xFFFF, sum = 0
3164 17:16:37.069995 12, 0x0, sum = 1
3165 17:16:37.070098 13, 0x0, sum = 2
3166 17:16:37.073459 14, 0x0, sum = 3
3167 17:16:37.073561 15, 0x0, sum = 4
3168 17:16:37.073651 best_step = 13
3169 17:16:37.073736
3170 17:16:37.076826
3171 17:16:37.076927 ==
3172 17:16:37.079879 Dram Type= 6, Freq= 0, CH_0, rank 1
3173 17:16:37.083301 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3174 17:16:37.083407 ==
3175 17:16:37.083498 RX Vref Scan: 0
3176 17:16:37.083586
3177 17:16:37.086989 RX Vref 0 -> 0, step: 1
3178 17:16:37.087096
3179 17:16:37.090017 RX Delay -21 -> 252, step: 4
3180 17:16:37.093125 iDelay=199, Bit 0, Center 112 (47 ~ 178) 132
3181 17:16:37.100005 iDelay=199, Bit 1, Center 118 (47 ~ 190) 144
3182 17:16:37.103251 iDelay=199, Bit 2, Center 110 (43 ~ 178) 136
3183 17:16:37.106431 iDelay=199, Bit 3, Center 114 (43 ~ 186) 144
3184 17:16:37.110243 iDelay=199, Bit 4, Center 118 (51 ~ 186) 136
3185 17:16:37.113118 iDelay=199, Bit 5, Center 110 (43 ~ 178) 136
3186 17:16:37.119720 iDelay=199, Bit 6, Center 128 (59 ~ 198) 140
3187 17:16:37.123217 iDelay=199, Bit 7, Center 124 (55 ~ 194) 140
3188 17:16:37.126383 iDelay=199, Bit 8, Center 96 (27 ~ 166) 140
3189 17:16:37.129836 iDelay=199, Bit 9, Center 92 (23 ~ 162) 140
3190 17:16:37.133281 iDelay=199, Bit 10, Center 110 (43 ~ 178) 136
3191 17:16:37.140297 iDelay=199, Bit 11, Center 100 (35 ~ 166) 132
3192 17:16:37.143216 iDelay=199, Bit 12, Center 110 (43 ~ 178) 136
3193 17:16:37.146452 iDelay=199, Bit 13, Center 114 (47 ~ 182) 136
3194 17:16:37.149675 iDelay=199, Bit 14, Center 118 (55 ~ 182) 128
3195 17:16:37.153205 iDelay=199, Bit 15, Center 116 (51 ~ 182) 132
3196 17:16:37.156566 ==
3197 17:16:37.156674 Dram Type= 6, Freq= 0, CH_0, rank 1
3198 17:16:37.159571
3199 17:16:37.162927 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3200 17:16:37.163040 ==
3201 17:16:37.163136 DQS Delay:
3202 17:16:37.166275 DQS0 = 0, DQS1 = 0
3203 17:16:37.166386 DQM Delay:
3204 17:16:37.169774 DQM0 = 116, DQM1 = 107
3205 17:16:37.169895 DQ Delay:
3206 17:16:37.172752 DQ0 =112, DQ1 =118, DQ2 =110, DQ3 =114
3207 17:16:37.176260 DQ4 =118, DQ5 =110, DQ6 =128, DQ7 =124
3208 17:16:37.179765 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3209 17:16:37.182651 DQ12 =110, DQ13 =114, DQ14 =118, DQ15 =116
3210 17:16:37.182807
3211 17:16:37.182906
3212 17:16:37.192531 [DQSOSCAuto] RK1, (LSB)MR18= 0xde7, (MSB)MR19= 0x403, tDQSOscB0 = 420 ps tDQSOscB1 = 405 ps
3213 17:16:37.192691 CH0 RK1: MR19=403, MR18=DE7
3214 17:16:37.199789 CH0_RK1: MR19=0x403, MR18=0xDE7, DQSOSC=405, MR23=63, INC=39, DEC=26
3215 17:16:37.202912 [RxdqsGatingPostProcess] freq 1200
3216 17:16:37.209305 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3217 17:16:37.212425 best DQS0 dly(2T, 0.5T) = (0, 11)
3218 17:16:37.215959 best DQS1 dly(2T, 0.5T) = (0, 12)
3219 17:16:37.219002 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3220 17:16:37.222436 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3221 17:16:37.226099 best DQS0 dly(2T, 0.5T) = (0, 11)
3222 17:16:37.226200 best DQS1 dly(2T, 0.5T) = (0, 12)
3223 17:16:37.229473
3224 17:16:37.229577 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3225 17:16:37.232563
3226 17:16:37.232667 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3227 17:16:37.235854 Pre-setting of DQS Precalculation
3228 17:16:37.242910 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3229 17:16:37.243017 ==
3230 17:16:37.246035 Dram Type= 6, Freq= 0, CH_1, rank 0
3231 17:16:37.249297 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3232 17:16:37.249439 ==
3233 17:16:37.255665 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3234 17:16:37.262196 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3235 17:16:37.269519 [CA 0] Center 37 (7~67) winsize 61
3236 17:16:37.273167 [CA 1] Center 37 (7~68) winsize 62
3237 17:16:37.276306 [CA 2] Center 34 (4~64) winsize 61
3238 17:16:37.279509 [CA 3] Center 33 (3~64) winsize 62
3239 17:16:37.282505 [CA 4] Center 34 (4~64) winsize 61
3240 17:16:37.286086 [CA 5] Center 33 (3~64) winsize 62
3241 17:16:37.286190
3242 17:16:37.289285 [CmdBusTrainingLP45] Vref(ca) range 1: 33
3243 17:16:37.289421
3244 17:16:37.292745 [CATrainingPosCal] consider 1 rank data
3245 17:16:37.296297 u2DelayCellTimex100 = 270/100 ps
3246 17:16:37.299686 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3247 17:16:37.306007 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3248 17:16:37.309076 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3249 17:16:37.312510 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3250 17:16:37.315451 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3251 17:16:37.319154 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3252 17:16:37.319265
3253 17:16:37.322669 CA PerBit enable=1, Macro0, CA PI delay=33
3254 17:16:37.322779
3255 17:16:37.325827 [CBTSetCACLKResult] CA Dly = 33
3256 17:16:37.329062 CS Dly: 5 (0~36)
3257 17:16:37.329169 ==
3258 17:16:37.332262 Dram Type= 6, Freq= 0, CH_1, rank 1
3259 17:16:37.335592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3260 17:16:37.335703 ==
3261 17:16:37.341866 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3262 17:16:37.345213 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3263 17:16:37.355172 [CA 0] Center 37 (7~68) winsize 62
3264 17:16:37.358444 [CA 1] Center 38 (8~68) winsize 61
3265 17:16:37.361563 [CA 2] Center 34 (4~65) winsize 62
3266 17:16:37.365124 [CA 3] Center 33 (3~64) winsize 62
3267 17:16:37.368247 [CA 4] Center 34 (3~65) winsize 63
3268 17:16:37.371775 [CA 5] Center 33 (3~64) winsize 62
3269 17:16:37.371886
3270 17:16:37.374764 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3271 17:16:37.374870
3272 17:16:37.378222 [CATrainingPosCal] consider 2 rank data
3273 17:16:37.381474 u2DelayCellTimex100 = 270/100 ps
3274 17:16:37.384930 CA0 delay=37 (7~67),Diff = 4 PI (19 cell)
3275 17:16:37.391386 CA1 delay=38 (8~68),Diff = 5 PI (24 cell)
3276 17:16:37.394628 CA2 delay=34 (4~64),Diff = 1 PI (4 cell)
3277 17:16:37.398470 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
3278 17:16:37.401514 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3279 17:16:37.404796 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3280 17:16:37.404905
3281 17:16:37.408012 CA PerBit enable=1, Macro0, CA PI delay=33
3282 17:16:37.408124
3283 17:16:37.411467 [CBTSetCACLKResult] CA Dly = 33
3284 17:16:37.411574 CS Dly: 7 (0~40)
3285 17:16:37.411675
3286 17:16:37.415016
3287 17:16:37.417963 ----->DramcWriteLeveling(PI) begin...
3288 17:16:37.418077 ==
3289 17:16:37.421282 Dram Type= 6, Freq= 0, CH_1, rank 0
3290 17:16:37.424648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3291 17:16:37.424759 ==
3292 17:16:37.427955 Write leveling (Byte 0): 25 => 25
3293 17:16:37.431486 Write leveling (Byte 1): 26 => 26
3294 17:16:37.434979 DramcWriteLeveling(PI) end<-----
3295 17:16:37.435088
3296 17:16:37.435185 ==
3297 17:16:37.437890 Dram Type= 6, Freq= 0, CH_1, rank 0
3298 17:16:37.441556 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3299 17:16:37.441670 ==
3300 17:16:37.444452 [Gating] SW mode calibration
3301 17:16:37.451082 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3302 17:16:37.457638 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3303 17:16:37.460791 0 15 0 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
3304 17:16:37.464177 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3305 17:16:37.471012 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3306 17:16:37.474211 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3307 17:16:37.477696 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3308 17:16:37.484050 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3309 17:16:37.487313 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
3310 17:16:37.490412 0 15 28 | B1->B0 | 2626 2323 | 0 0 | (1 0) (0 0)
3311 17:16:37.497028 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3312 17:16:37.500685 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3313 17:16:37.503604 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3314 17:16:37.510711 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3315 17:16:37.513755 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3316 17:16:37.517057 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3317 17:16:37.523507 1 0 24 | B1->B0 | 2c2c 3c3b | 0 1 | (0 0) (0 0)
3318 17:16:37.527124 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3319 17:16:37.530164 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3320 17:16:37.536955 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3321 17:16:37.540269 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3322 17:16:37.543322 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3323 17:16:37.550126 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3324 17:16:37.553734 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3325 17:16:37.556739 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3326 17:16:37.563141 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3327 17:16:37.566666 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3328 17:16:37.569908 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3329 17:16:37.576483 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3330 17:16:37.579778 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3331 17:16:37.583041 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3332 17:16:37.589917 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3333 17:16:37.593212 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3334 17:16:37.596523 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3335 17:16:37.603475 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3336 17:16:37.606412 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3337 17:16:37.609875 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3338 17:16:37.616192 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3339 17:16:37.619561 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3340 17:16:37.623094 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3341 17:16:37.626233 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3342 17:16:37.629307
3343 17:16:37.632873 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3344 17:16:37.636070 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3345 17:16:37.639592 Total UI for P1: 0, mck2ui 16
3346 17:16:37.642950 best dqsien dly found for B0: ( 1, 3, 26)
3347 17:16:37.645950 Total UI for P1: 0, mck2ui 16
3348 17:16:37.649269 best dqsien dly found for B1: ( 1, 3, 28)
3349 17:16:37.653010 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3350 17:16:37.656338 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3351 17:16:37.656443
3352 17:16:37.659221 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3353 17:16:37.665916 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3354 17:16:37.666024 [Gating] SW calibration Done
3355 17:16:37.666114 ==
3356 17:16:37.669068 Dram Type= 6, Freq= 0, CH_1, rank 0
3357 17:16:37.675661 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3358 17:16:37.675772 ==
3359 17:16:37.675863 RX Vref Scan: 0
3360 17:16:37.675952
3361 17:16:37.679029 RX Vref 0 -> 0, step: 1
3362 17:16:37.679131
3363 17:16:37.682674 RX Delay -40 -> 252, step: 8
3364 17:16:37.685857 iDelay=208, Bit 0, Center 123 (48 ~ 199) 152
3365 17:16:37.689014 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3366 17:16:37.692344 iDelay=208, Bit 2, Center 111 (40 ~ 183) 144
3367 17:16:37.699260 iDelay=208, Bit 3, Center 115 (40 ~ 191) 152
3368 17:16:37.702331 iDelay=208, Bit 4, Center 111 (40 ~ 183) 144
3369 17:16:37.705767 iDelay=208, Bit 5, Center 131 (56 ~ 207) 152
3370 17:16:37.709249 iDelay=208, Bit 6, Center 123 (48 ~ 199) 152
3371 17:16:37.712675 iDelay=208, Bit 7, Center 115 (48 ~ 183) 136
3372 17:16:37.719183 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3373 17:16:37.722647 iDelay=208, Bit 9, Center 99 (24 ~ 175) 152
3374 17:16:37.725593 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3375 17:16:37.729032 iDelay=208, Bit 11, Center 95 (24 ~ 167) 144
3376 17:16:37.732641 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3377 17:16:37.738938 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3378 17:16:37.742738 iDelay=208, Bit 14, Center 119 (48 ~ 191) 144
3379 17:16:37.745266 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3380 17:16:37.745406 ==
3381 17:16:37.749026 Dram Type= 6, Freq= 0, CH_1, rank 0
3382 17:16:37.752225 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3383 17:16:37.752333 ==
3384 17:16:37.755256 DQS Delay:
3385 17:16:37.755362 DQS0 = 0, DQS1 = 0
3386 17:16:37.758654 DQM Delay:
3387 17:16:37.758762 DQM0 = 117, DQM1 = 109
3388 17:16:37.758857 DQ Delay:
3389 17:16:37.765127 DQ0 =123, DQ1 =111, DQ2 =111, DQ3 =115
3390 17:16:37.768684 DQ4 =111, DQ5 =131, DQ6 =123, DQ7 =115
3391 17:16:37.772012 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =95
3392 17:16:37.775244 DQ12 =119, DQ13 =119, DQ14 =119, DQ15 =119
3393 17:16:37.775344
3394 17:16:37.775431
3395 17:16:37.775513 ==
3396 17:16:37.778548 Dram Type= 6, Freq= 0, CH_1, rank 0
3397 17:16:37.781854 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3398 17:16:37.781956 ==
3399 17:16:37.782043
3400 17:16:37.782125
3401 17:16:37.785208 TX Vref Scan disable
3402 17:16:37.788855 == TX Byte 0 ==
3403 17:16:37.791634 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3404 17:16:37.795317 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3405 17:16:37.798798 == TX Byte 1 ==
3406 17:16:37.801939 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3407 17:16:37.805210 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3408 17:16:37.805318 ==
3409 17:16:37.808628 Dram Type= 6, Freq= 0, CH_1, rank 0
3410 17:16:37.812005 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3411 17:16:37.814865 ==
3412 17:16:37.824911 TX Vref=22, minBit 9, minWin=25, winSum=416
3413 17:16:37.828204 TX Vref=24, minBit 9, minWin=25, winSum=422
3414 17:16:37.831266 TX Vref=26, minBit 10, minWin=25, winSum=427
3415 17:16:37.834646 TX Vref=28, minBit 2, minWin=26, winSum=432
3416 17:16:37.837866 TX Vref=30, minBit 9, minWin=26, winSum=431
3417 17:16:37.844753 TX Vref=32, minBit 9, minWin=25, winSum=423
3418 17:16:37.848239 [TxChooseVref] Worse bit 2, Min win 26, Win sum 432, Final Vref 28
3419 17:16:37.848339
3420 17:16:37.851480 Final TX Range 1 Vref 28
3421 17:16:37.851581
3422 17:16:37.851667 ==
3423 17:16:37.854809 Dram Type= 6, Freq= 0, CH_1, rank 0
3424 17:16:37.858038 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3425 17:16:37.858143 ==
3426 17:16:37.861260
3427 17:16:37.861397
3428 17:16:37.861485 TX Vref Scan disable
3429 17:16:37.864806 == TX Byte 0 ==
3430 17:16:37.868014 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3431 17:16:37.871570 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3432 17:16:37.874539
3433 17:16:37.874644 == TX Byte 1 ==
3434 17:16:37.877909 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3435 17:16:37.881328 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3436 17:16:37.884382
3437 17:16:37.884493
3438 17:16:37.884590 [DATLAT]
3439 17:16:37.884697 Freq=1200, CH1 RK0
3440 17:16:37.884797
3441 17:16:37.888043 DATLAT Default: 0xd
3442 17:16:37.888156 0, 0xFFFF, sum = 0
3443 17:16:37.891087 1, 0xFFFF, sum = 0
3444 17:16:37.891207 2, 0xFFFF, sum = 0
3445 17:16:37.894579
3446 17:16:37.894687 3, 0xFFFF, sum = 0
3447 17:16:37.897902 4, 0xFFFF, sum = 0
3448 17:16:37.898014 5, 0xFFFF, sum = 0
3449 17:16:37.901016 6, 0xFFFF, sum = 0
3450 17:16:37.901125 7, 0xFFFF, sum = 0
3451 17:16:37.904802 8, 0xFFFF, sum = 0
3452 17:16:37.904914 9, 0xFFFF, sum = 0
3453 17:16:37.907937 10, 0xFFFF, sum = 0
3454 17:16:37.908047 11, 0xFFFF, sum = 0
3455 17:16:37.911301 12, 0x0, sum = 1
3456 17:16:37.911413 13, 0x0, sum = 2
3457 17:16:37.914293 14, 0x0, sum = 3
3458 17:16:37.914401 15, 0x0, sum = 4
3459 17:16:37.914498 best_step = 13
3460 17:16:37.917641
3461 17:16:37.917746
3462 17:16:37.917837 ==
3463 17:16:37.921189 Dram Type= 6, Freq= 0, CH_1, rank 0
3464 17:16:37.924610 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3465 17:16:37.924711 ==
3466 17:16:37.924798 RX Vref Scan: 1
3467 17:16:37.924882
3468 17:16:37.927607 Set Vref Range= 32 -> 127
3469 17:16:37.927705
3470 17:16:37.930989 RX Vref 32 -> 127, step: 1
3471 17:16:37.931085
3472 17:16:37.934650 RX Delay -21 -> 252, step: 4
3473 17:16:37.934751
3474 17:16:37.937703 Set Vref, RX VrefLevel [Byte0]: 32
3475 17:16:37.940722 [Byte1]: 32
3476 17:16:37.940823
3477 17:16:37.944264 Set Vref, RX VrefLevel [Byte0]: 33
3478 17:16:37.947808 [Byte1]: 33
3479 17:16:37.951266
3480 17:16:37.951369 Set Vref, RX VrefLevel [Byte0]: 34
3481 17:16:37.954285 [Byte1]: 34
3482 17:16:37.958925
3483 17:16:37.959028 Set Vref, RX VrefLevel [Byte0]: 35
3484 17:16:37.962447 [Byte1]: 35
3485 17:16:37.966743
3486 17:16:37.966857 Set Vref, RX VrefLevel [Byte0]: 36
3487 17:16:37.970337 [Byte1]: 36
3488 17:16:37.974680
3489 17:16:37.974791 Set Vref, RX VrefLevel [Byte0]: 37
3490 17:16:37.978143 [Byte1]: 37
3491 17:16:37.983045
3492 17:16:37.983146 Set Vref, RX VrefLevel [Byte0]: 38
3493 17:16:37.985903 [Byte1]: 38
3494 17:16:37.990645
3495 17:16:37.990748 Set Vref, RX VrefLevel [Byte0]: 39
3496 17:16:37.993966 [Byte1]: 39
3497 17:16:37.998861
3498 17:16:37.998963 Set Vref, RX VrefLevel [Byte0]: 40
3499 17:16:38.001839 [Byte1]: 40
3500 17:16:38.006715
3501 17:16:38.006805 Set Vref, RX VrefLevel [Byte0]: 41
3502 17:16:38.009700 [Byte1]: 41
3503 17:16:38.014669
3504 17:16:38.014753 Set Vref, RX VrefLevel [Byte0]: 42
3505 17:16:38.018144 [Byte1]: 42
3506 17:16:38.022464
3507 17:16:38.022547 Set Vref, RX VrefLevel [Byte0]: 43
3508 17:16:38.025745 [Byte1]: 43
3509 17:16:38.030336
3510 17:16:38.030419 Set Vref, RX VrefLevel [Byte0]: 44
3511 17:16:38.033653 [Byte1]: 44
3512 17:16:38.038361
3513 17:16:38.038445 Set Vref, RX VrefLevel [Byte0]: 45
3514 17:16:38.041548 [Byte1]: 45
3515 17:16:38.046161
3516 17:16:38.046244 Set Vref, RX VrefLevel [Byte0]: 46
3517 17:16:38.049332 [Byte1]: 46
3518 17:16:38.054584
3519 17:16:38.054668 Set Vref, RX VrefLevel [Byte0]: 47
3520 17:16:38.057775 [Byte1]: 47
3521 17:16:38.062001
3522 17:16:38.062084 Set Vref, RX VrefLevel [Byte0]: 48
3523 17:16:38.065245 [Byte1]: 48
3524 17:16:38.069687
3525 17:16:38.069770 Set Vref, RX VrefLevel [Byte0]: 49
3526 17:16:38.073365 [Byte1]: 49
3527 17:16:38.077661
3528 17:16:38.077746 Set Vref, RX VrefLevel [Byte0]: 50
3529 17:16:38.080884 [Byte1]: 50
3530 17:16:38.085589
3531 17:16:38.085672 Set Vref, RX VrefLevel [Byte0]: 51
3532 17:16:38.088969 [Byte1]: 51
3533 17:16:38.093613
3534 17:16:38.093697 Set Vref, RX VrefLevel [Byte0]: 52
3535 17:16:38.096953 [Byte1]: 52
3536 17:16:38.101844
3537 17:16:38.101928 Set Vref, RX VrefLevel [Byte0]: 53
3538 17:16:38.104727 [Byte1]: 53
3539 17:16:38.109342
3540 17:16:38.109441 Set Vref, RX VrefLevel [Byte0]: 54
3541 17:16:38.112745 [Byte1]: 54
3542 17:16:38.117238
3543 17:16:38.117342 Set Vref, RX VrefLevel [Byte0]: 55
3544 17:16:38.120743 [Byte1]: 55
3545 17:16:38.125238
3546 17:16:38.125326 Set Vref, RX VrefLevel [Byte0]: 56
3547 17:16:38.128803 [Byte1]: 56
3548 17:16:38.133355
3549 17:16:38.133439 Set Vref, RX VrefLevel [Byte0]: 57
3550 17:16:38.136536 [Byte1]: 57
3551 17:16:38.141346
3552 17:16:38.141443 Set Vref, RX VrefLevel [Byte0]: 58
3553 17:16:38.144329 [Byte1]: 58
3554 17:16:38.149390
3555 17:16:38.149473 Set Vref, RX VrefLevel [Byte0]: 59
3556 17:16:38.152432 [Byte1]: 59
3557 17:16:38.157314
3558 17:16:38.157430 Set Vref, RX VrefLevel [Byte0]: 60
3559 17:16:38.160342 [Byte1]: 60
3560 17:16:38.165023
3561 17:16:38.165106 Set Vref, RX VrefLevel [Byte0]: 61
3562 17:16:38.168489 [Byte1]: 61
3563 17:16:38.172716
3564 17:16:38.172800 Set Vref, RX VrefLevel [Byte0]: 62
3565 17:16:38.176448 [Byte1]: 62
3566 17:16:38.180729
3567 17:16:38.180812 Set Vref, RX VrefLevel [Byte0]: 63
3568 17:16:38.184258 [Byte1]: 63
3569 17:16:38.188730
3570 17:16:38.188814 Set Vref, RX VrefLevel [Byte0]: 64
3571 17:16:38.191912 [Byte1]: 64
3572 17:16:38.196874
3573 17:16:38.196957 Set Vref, RX VrefLevel [Byte0]: 65
3574 17:16:38.200251 [Byte1]: 65
3575 17:16:38.204660
3576 17:16:38.204744 Set Vref, RX VrefLevel [Byte0]: 66
3577 17:16:38.208026 [Byte1]: 66
3578 17:16:38.212373
3579 17:16:38.212456 Set Vref, RX VrefLevel [Byte0]: 67
3580 17:16:38.215659 [Byte1]: 67
3581 17:16:38.220767
3582 17:16:38.220851 Set Vref, RX VrefLevel [Byte0]: 68
3583 17:16:38.223944 [Byte1]: 68
3584 17:16:38.228201
3585 17:16:38.228284 Final RX Vref Byte 0 = 47 to rank0
3586 17:16:38.231743 Final RX Vref Byte 1 = 60 to rank0
3587 17:16:38.234869 Final RX Vref Byte 0 = 47 to rank1
3588 17:16:38.238408 Final RX Vref Byte 1 = 60 to rank1==
3589 17:16:38.241602 Dram Type= 6, Freq= 0, CH_1, rank 0
3590 17:16:38.248204 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3591 17:16:38.248288 ==
3592 17:16:38.248353 DQS Delay:
3593 17:16:38.248414 DQS0 = 0, DQS1 = 0
3594 17:16:38.251545 DQM Delay:
3595 17:16:38.251627 DQM0 = 116, DQM1 = 112
3596 17:16:38.255244 DQ Delay:
3597 17:16:38.258249 DQ0 =118, DQ1 =112, DQ2 =108, DQ3 =112
3598 17:16:38.261564 DQ4 =112, DQ5 =126, DQ6 =126, DQ7 =114
3599 17:16:38.264680 DQ8 =100, DQ9 =102, DQ10 =116, DQ11 =102
3600 17:16:38.268340 DQ12 =118, DQ13 =118, DQ14 =124, DQ15 =120
3601 17:16:38.268423
3602 17:16:38.268490
3603 17:16:38.274665 [DQSOSCAuto] RK0, (LSB)MR18= 0x6f9, (MSB)MR19= 0x403, tDQSOscB0 = 412 ps tDQSOscB1 = 407 ps
3604 17:16:38.278250 CH1 RK0: MR19=403, MR18=6F9
3605 17:16:38.285220 CH1_RK0: MR19=0x403, MR18=0x6F9, DQSOSC=407, MR23=63, INC=39, DEC=26
3606 17:16:38.285304
3607 17:16:38.288210 ----->DramcWriteLeveling(PI) begin...
3608 17:16:38.288297 ==
3609 17:16:38.291219 Dram Type= 6, Freq= 0, CH_1, rank 1
3610 17:16:38.294862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3611 17:16:38.297935 ==
3612 17:16:38.298011 Write leveling (Byte 0): 25 => 25
3613 17:16:38.301093 Write leveling (Byte 1): 28 => 28
3614 17:16:38.304710 DramcWriteLeveling(PI) end<-----
3615 17:16:38.304794
3616 17:16:38.304860 ==
3617 17:16:38.307699 Dram Type= 6, Freq= 0, CH_1, rank 1
3618 17:16:38.314257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3619 17:16:38.314350 ==
3620 17:16:38.317848 [Gating] SW mode calibration
3621 17:16:38.324515 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3622 17:16:38.327468 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3623 17:16:38.333981 0 15 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3624 17:16:38.337555 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3625 17:16:38.340579 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3626 17:16:38.347488 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3627 17:16:38.350562 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3628 17:16:38.354088 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3629 17:16:38.360650 0 15 24 | B1->B0 | 2f2f 3434 | 1 0 | (1 0) (0 1)
3630 17:16:38.363969 0 15 28 | B1->B0 | 2525 2727 | 0 0 | (0 0) (1 0)
3631 17:16:38.366956 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3632 17:16:38.373626 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3633 17:16:38.377025 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3634 17:16:38.380188 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3635 17:16:38.386642 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3636 17:16:38.390482 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3637 17:16:38.393298 1 0 24 | B1->B0 | 3535 2d2c | 0 1 | (0 0) (0 0)
3638 17:16:38.400216 1 0 28 | B1->B0 | 4646 4141 | 0 1 | (0 0) (0 0)
3639 17:16:38.403658 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3640 17:16:38.406667 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3641 17:16:38.413120 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3642 17:16:38.416869 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3643 17:16:38.419674 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3644 17:16:38.426581 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3645 17:16:38.429687 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3646 17:16:38.432823 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
3647 17:16:38.439888 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3648 17:16:38.443316 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3649 17:16:38.446494 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3650 17:16:38.452988 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3651 17:16:38.456108 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3652 17:16:38.459703 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3653 17:16:38.466175 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3654 17:16:38.469303 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3655 17:16:38.472811 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3656 17:16:38.479384 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3657 17:16:38.482306 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3658 17:16:38.485729 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3659 17:16:38.492316 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3660 17:16:38.495738 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3661 17:16:38.498808 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3662 17:16:38.505550 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
3663 17:16:38.508861 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3664 17:16:38.511953 Total UI for P1: 0, mck2ui 16
3665 17:16:38.515886 best dqsien dly found for B0: ( 1, 3, 26)
3666 17:16:38.518809 Total UI for P1: 0, mck2ui 16
3667 17:16:38.522154 best dqsien dly found for B1: ( 1, 3, 26)
3668 17:16:38.525638 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
3669 17:16:38.528836 best DQS1 dly(MCK, UI, PI) = (1, 3, 26)
3670 17:16:38.528921
3671 17:16:38.532423 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
3672 17:16:38.535319 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 26)
3673 17:16:38.538465 [Gating] SW calibration Done
3674 17:16:38.538551 ==
3675 17:16:38.541971 Dram Type= 6, Freq= 0, CH_1, rank 1
3676 17:16:38.545285 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3677 17:16:38.548399 ==
3678 17:16:38.548494 RX Vref Scan: 0
3679 17:16:38.548562
3680 17:16:38.551790 RX Vref 0 -> 0, step: 1
3681 17:16:38.551875
3682 17:16:38.554834 RX Delay -40 -> 252, step: 8
3683 17:16:38.558225 iDelay=208, Bit 0, Center 123 (56 ~ 191) 136
3684 17:16:38.561496 iDelay=208, Bit 1, Center 111 (40 ~ 183) 144
3685 17:16:38.564936 iDelay=208, Bit 2, Center 103 (32 ~ 175) 144
3686 17:16:38.568522 iDelay=208, Bit 3, Center 111 (40 ~ 183) 144
3687 17:16:38.575158 iDelay=208, Bit 4, Center 115 (40 ~ 191) 152
3688 17:16:38.578236 iDelay=208, Bit 5, Center 127 (56 ~ 199) 144
3689 17:16:38.581632 iDelay=208, Bit 6, Center 131 (56 ~ 207) 152
3690 17:16:38.584732 iDelay=208, Bit 7, Center 115 (40 ~ 191) 152
3691 17:16:38.588142 iDelay=208, Bit 8, Center 95 (24 ~ 167) 144
3692 17:16:38.594923 iDelay=208, Bit 9, Center 99 (32 ~ 167) 136
3693 17:16:38.597761 iDelay=208, Bit 10, Center 111 (40 ~ 183) 144
3694 17:16:38.601460 iDelay=208, Bit 11, Center 103 (32 ~ 175) 144
3695 17:16:38.604539 iDelay=208, Bit 12, Center 119 (48 ~ 191) 144
3696 17:16:38.611135 iDelay=208, Bit 13, Center 119 (48 ~ 191) 144
3697 17:16:38.614473 iDelay=208, Bit 14, Center 115 (40 ~ 191) 152
3698 17:16:38.617524 iDelay=208, Bit 15, Center 119 (48 ~ 191) 144
3699 17:16:38.617609 ==
3700 17:16:38.620743 Dram Type= 6, Freq= 0, CH_1, rank 1
3701 17:16:38.624343 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3702 17:16:38.624429 ==
3703 17:16:38.627417 DQS Delay:
3704 17:16:38.627502 DQS0 = 0, DQS1 = 0
3705 17:16:38.630681 DQM Delay:
3706 17:16:38.630766 DQM0 = 117, DQM1 = 110
3707 17:16:38.630833 DQ Delay:
3708 17:16:38.634353 DQ0 =123, DQ1 =111, DQ2 =103, DQ3 =111
3709 17:16:38.640910 DQ4 =115, DQ5 =127, DQ6 =131, DQ7 =115
3710 17:16:38.644046 DQ8 =95, DQ9 =99, DQ10 =111, DQ11 =103
3711 17:16:38.647366 DQ12 =119, DQ13 =119, DQ14 =115, DQ15 =119
3712 17:16:38.647451
3713 17:16:38.647519
3714 17:16:38.647580 ==
3715 17:16:38.650679 Dram Type= 6, Freq= 0, CH_1, rank 1
3716 17:16:38.653915 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3717 17:16:38.654000 ==
3718 17:16:38.654067
3719 17:16:38.654128
3720 17:16:38.657271 TX Vref Scan disable
3721 17:16:38.660415 == TX Byte 0 ==
3722 17:16:38.663886 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3723 17:16:38.667230 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3724 17:16:38.670371 == TX Byte 1 ==
3725 17:16:38.673763 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3726 17:16:38.677071 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3727 17:16:38.677156 ==
3728 17:16:38.680128 Dram Type= 6, Freq= 0, CH_1, rank 1
3729 17:16:38.687083 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3730 17:16:38.687169 ==
3731 17:16:38.697106 TX Vref=22, minBit 8, minWin=25, winSum=421
3732 17:16:38.700516 TX Vref=24, minBit 8, minWin=25, winSum=426
3733 17:16:38.703661 TX Vref=26, minBit 8, minWin=25, winSum=430
3734 17:16:38.707137 TX Vref=28, minBit 9, minWin=26, winSum=431
3735 17:16:38.710716 TX Vref=30, minBit 8, minWin=26, winSum=432
3736 17:16:38.717078 TX Vref=32, minBit 9, minWin=25, winSum=427
3737 17:16:38.720416 [TxChooseVref] Worse bit 8, Min win 26, Win sum 432, Final Vref 30
3738 17:16:38.720502
3739 17:16:38.723727 Final TX Range 1 Vref 30
3740 17:16:38.723812
3741 17:16:38.723880 ==
3742 17:16:38.727140 Dram Type= 6, Freq= 0, CH_1, rank 1
3743 17:16:38.730239 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3744 17:16:38.730324 ==
3745 17:16:38.733592
3746 17:16:38.733677
3747 17:16:38.733744
3748 17:16:38.733804 TX Vref Scan disable
3749 17:16:38.737272 == TX Byte 0 ==
3750 17:16:38.740085 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3751 17:16:38.746674 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3752 17:16:38.746759 == TX Byte 1 ==
3753 17:16:38.750308 Update DQ dly =845 (3 ,2, 13) DQ OEN =(2 ,7)
3754 17:16:38.756771 Update DQM dly =845 (3 ,2, 13) DQM OEN =(2 ,7)
3755 17:16:38.756856
3756 17:16:38.756923 [DATLAT]
3757 17:16:38.756983 Freq=1200, CH1 RK1
3758 17:16:38.757042
3759 17:16:38.759842 DATLAT Default: 0xd
3760 17:16:38.759927 0, 0xFFFF, sum = 0
3761 17:16:38.763357
3762 17:16:38.763442 1, 0xFFFF, sum = 0
3763 17:16:38.766431 2, 0xFFFF, sum = 0
3764 17:16:38.766517 3, 0xFFFF, sum = 0
3765 17:16:38.770001 4, 0xFFFF, sum = 0
3766 17:16:38.770098 5, 0xFFFF, sum = 0
3767 17:16:38.773471 6, 0xFFFF, sum = 0
3768 17:16:38.773558 7, 0xFFFF, sum = 0
3769 17:16:38.776562 8, 0xFFFF, sum = 0
3770 17:16:38.776649 9, 0xFFFF, sum = 0
3771 17:16:38.779833 10, 0xFFFF, sum = 0
3772 17:16:38.779919 11, 0xFFFF, sum = 0
3773 17:16:38.783096 12, 0x0, sum = 1
3774 17:16:38.783182 13, 0x0, sum = 2
3775 17:16:38.786684 14, 0x0, sum = 3
3776 17:16:38.786771 15, 0x0, sum = 4
3777 17:16:38.789839 best_step = 13
3778 17:16:38.789924
3779 17:16:38.789991 ==
3780 17:16:38.793244 Dram Type= 6, Freq= 0, CH_1, rank 1
3781 17:16:38.796757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3782 17:16:38.796843 ==
3783 17:16:38.796911 RX Vref Scan: 0
3784 17:16:38.799761
3785 17:16:38.799846
3786 17:16:38.799912 RX Vref 0 -> 0, step: 1
3787 17:16:38.799973
3788 17:16:38.803243 RX Delay -21 -> 252, step: 4
3789 17:16:38.809236 iDelay=199, Bit 0, Center 118 (51 ~ 186) 136
3790 17:16:38.813066 iDelay=199, Bit 1, Center 112 (47 ~ 178) 132
3791 17:16:38.815921 iDelay=199, Bit 2, Center 104 (39 ~ 170) 132
3792 17:16:38.819149 iDelay=199, Bit 3, Center 112 (47 ~ 178) 132
3793 17:16:38.822602 iDelay=199, Bit 4, Center 114 (47 ~ 182) 136
3794 17:16:38.829281 iDelay=199, Bit 5, Center 126 (59 ~ 194) 136
3795 17:16:38.832659 iDelay=199, Bit 6, Center 130 (63 ~ 198) 136
3796 17:16:38.835919 iDelay=199, Bit 7, Center 116 (51 ~ 182) 132
3797 17:16:38.839099 iDelay=199, Bit 8, Center 98 (31 ~ 166) 136
3798 17:16:38.842258 iDelay=199, Bit 9, Center 100 (35 ~ 166) 132
3799 17:16:38.849065 iDelay=199, Bit 10, Center 112 (47 ~ 178) 132
3800 17:16:38.852711 iDelay=199, Bit 11, Center 102 (35 ~ 170) 136
3801 17:16:38.855623 iDelay=199, Bit 12, Center 120 (55 ~ 186) 132
3802 17:16:38.859159 iDelay=199, Bit 13, Center 116 (51 ~ 182) 132
3803 17:16:38.862326 iDelay=199, Bit 14, Center 118 (51 ~ 186) 136
3804 17:16:38.869293 iDelay=199, Bit 15, Center 120 (51 ~ 190) 140
3805 17:16:38.869422 ==
3806 17:16:38.872753 Dram Type= 6, Freq= 0, CH_1, rank 1
3807 17:16:38.875599 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3808 17:16:38.875684 ==
3809 17:16:38.875751 DQS Delay:
3810 17:16:38.878994 DQS0 = 0, DQS1 = 0
3811 17:16:38.879084 DQM Delay:
3812 17:16:38.882225 DQM0 = 116, DQM1 = 110
3813 17:16:38.882310 DQ Delay:
3814 17:16:38.885567 DQ0 =118, DQ1 =112, DQ2 =104, DQ3 =112
3815 17:16:38.888865 DQ4 =114, DQ5 =126, DQ6 =130, DQ7 =116
3816 17:16:38.892496 DQ8 =98, DQ9 =100, DQ10 =112, DQ11 =102
3817 17:16:38.895685 DQ12 =120, DQ13 =116, DQ14 =118, DQ15 =120
3818 17:16:38.895777
3819 17:16:38.898766
3820 17:16:38.905516 [DQSOSCAuto] RK1, (LSB)MR18= 0xf1ec, (MSB)MR19= 0x303, tDQSOscB0 = 418 ps tDQSOscB1 = 416 ps
3821 17:16:38.908968 CH1 RK1: MR19=303, MR18=F1EC
3822 17:16:38.915435 CH1_RK1: MR19=0x303, MR18=0xF1EC, DQSOSC=416, MR23=63, INC=37, DEC=25
3823 17:16:38.918782 [RxdqsGatingPostProcess] freq 1200
3824 17:16:38.922221 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3825 17:16:38.925660 best DQS0 dly(2T, 0.5T) = (0, 11)
3826 17:16:38.928410 best DQS1 dly(2T, 0.5T) = (0, 11)
3827 17:16:38.931952 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3828 17:16:38.935378 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3829 17:16:38.938267 best DQS0 dly(2T, 0.5T) = (0, 11)
3830 17:16:38.941830 best DQS1 dly(2T, 0.5T) = (0, 11)
3831 17:16:38.944805 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3832 17:16:38.948265 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3833 17:16:38.951425 Pre-setting of DQS Precalculation
3834 17:16:38.954886 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3835 17:16:38.964860 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3836 17:16:38.971325 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3837 17:16:38.971413
3838 17:16:38.971481
3839 17:16:38.974571 [Calibration Summary] 2400 Mbps
3840 17:16:38.974654 CH 0, Rank 0
3841 17:16:38.977726 SW Impedance : PASS
3842 17:16:38.977807 DUTY Scan : NO K
3843 17:16:38.981155 ZQ Calibration : PASS
3844 17:16:38.984667 Jitter Meter : NO K
3845 17:16:38.984745 CBT Training : PASS
3846 17:16:38.988066 Write leveling : PASS
3847 17:16:38.990872 RX DQS gating : PASS
3848 17:16:38.990949 RX DQ/DQS(RDDQC) : PASS
3849 17:16:38.994345 TX DQ/DQS : PASS
3850 17:16:38.997627 RX DATLAT : PASS
3851 17:16:38.997716 RX DQ/DQS(Engine): PASS
3852 17:16:39.000693 TX OE : NO K
3853 17:16:39.000778 All Pass.
3854 17:16:39.000844
3855 17:16:39.004314 CH 0, Rank 1
3856 17:16:39.004398 SW Impedance : PASS
3857 17:16:39.007616 DUTY Scan : NO K
3858 17:16:39.010754 ZQ Calibration : PASS
3859 17:16:39.010838 Jitter Meter : NO K
3860 17:16:39.014000 CBT Training : PASS
3861 17:16:39.017437 Write leveling : PASS
3862 17:16:39.017517 RX DQS gating : PASS
3863 17:16:39.020560 RX DQ/DQS(RDDQC) : PASS
3864 17:16:39.023792 TX DQ/DQS : PASS
3865 17:16:39.023877 RX DATLAT : PASS
3866 17:16:39.027603 RX DQ/DQS(Engine): PASS
3867 17:16:39.027688 TX OE : NO K
3868 17:16:39.030454
3869 17:16:39.030542 All Pass.
3870 17:16:39.030610
3871 17:16:39.030672 CH 1, Rank 0
3872 17:16:39.033637 SW Impedance : PASS
3873 17:16:39.033726 DUTY Scan : NO K
3874 17:16:39.037191
3875 17:16:39.037274 ZQ Calibration : PASS
3876 17:16:39.040711 Jitter Meter : NO K
3877 17:16:39.040790 CBT Training : PASS
3878 17:16:39.043814 Write leveling : PASS
3879 17:16:39.046844 RX DQS gating : PASS
3880 17:16:39.046919 RX DQ/DQS(RDDQC) : PASS
3881 17:16:39.050428 TX DQ/DQS : PASS
3882 17:16:39.053492 RX DATLAT : PASS
3883 17:16:39.053577 RX DQ/DQS(Engine): PASS
3884 17:16:39.056829 TX OE : NO K
3885 17:16:39.056913 All Pass.
3886 17:16:39.056979
3887 17:16:39.060068 CH 1, Rank 1
3888 17:16:39.060152 SW Impedance : PASS
3889 17:16:39.063521 DUTY Scan : NO K
3890 17:16:39.066536 ZQ Calibration : PASS
3891 17:16:39.066624 Jitter Meter : NO K
3892 17:16:39.070153 CBT Training : PASS
3893 17:16:39.073561 Write leveling : PASS
3894 17:16:39.073646 RX DQS gating : PASS
3895 17:16:39.076561 RX DQ/DQS(RDDQC) : PASS
3896 17:16:39.080177 TX DQ/DQS : PASS
3897 17:16:39.080257 RX DATLAT : PASS
3898 17:16:39.083610 RX DQ/DQS(Engine): PASS
3899 17:16:39.086413 TX OE : NO K
3900 17:16:39.086498 All Pass.
3901 17:16:39.086578
3902 17:16:39.086643 DramC Write-DBI off
3903 17:16:39.089623
3904 17:16:39.089707 PER_BANK_REFRESH: Hybrid Mode
3905 17:16:39.093026 TX_TRACKING: ON
3906 17:16:39.099598 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3907 17:16:39.106113 [FAST_K] Save calibration result to emmc
3908 17:16:39.109943 dramc_set_vcore_voltage set vcore to 650000
3909 17:16:39.110027 Read voltage for 600, 5
3910 17:16:39.113030 Vio18 = 0
3911 17:16:39.113115 Vcore = 650000
3912 17:16:39.113181 Vdram = 0
3913 17:16:39.116306 Vddq = 0
3914 17:16:39.116390 Vmddr = 0
3915 17:16:39.119687 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3916 17:16:39.125938 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3917 17:16:39.129237 MEM_TYPE=3, freq_sel=19
3918 17:16:39.133350 sv_algorithm_assistance_LP4_1600
3919 17:16:39.136178 ============ PULL DRAM RESETB DOWN ============
3920 17:16:39.139210 ========== PULL DRAM RESETB DOWN end =========
3921 17:16:39.145917 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3922 17:16:39.149244 ===================================
3923 17:16:39.149340 LPDDR4 DRAM CONFIGURATION
3924 17:16:39.152146 ===================================
3925 17:16:39.155821 EX_ROW_EN[0] = 0x0
3926 17:16:39.155909 EX_ROW_EN[1] = 0x0
3927 17:16:39.158850
3928 17:16:39.158926 LP4Y_EN = 0x0
3929 17:16:39.162201 WORK_FSP = 0x0
3930 17:16:39.162278 WL = 0x2
3931 17:16:39.165874 RL = 0x2
3932 17:16:39.165954 BL = 0x2
3933 17:16:39.168807 RPST = 0x0
3934 17:16:39.168883 RD_PRE = 0x0
3935 17:16:39.172363 WR_PRE = 0x1
3936 17:16:39.172441 WR_PST = 0x0
3937 17:16:39.175257 DBI_WR = 0x0
3938 17:16:39.175333 DBI_RD = 0x0
3939 17:16:39.178609 OTF = 0x1
3940 17:16:39.182624 ===================================
3941 17:16:39.185216 ===================================
3942 17:16:39.185301 ANA top config
3943 17:16:39.188608 ===================================
3944 17:16:39.191866 DLL_ASYNC_EN = 0
3945 17:16:39.195497 ALL_SLAVE_EN = 1
3946 17:16:39.198941 NEW_RANK_MODE = 1
3947 17:16:39.199026 DLL_IDLE_MODE = 1
3948 17:16:39.201871 LP45_APHY_COMB_EN = 1
3949 17:16:39.205137 TX_ODT_DIS = 1
3950 17:16:39.208623 NEW_8X_MODE = 1
3951 17:16:39.211763 ===================================
3952 17:16:39.215227 ===================================
3953 17:16:39.218154 data_rate = 1200
3954 17:16:39.218238 CKR = 1
3955 17:16:39.221802 DQ_P2S_RATIO = 8
3956 17:16:39.224901 ===================================
3957 17:16:39.228424 CA_P2S_RATIO = 8
3958 17:16:39.231145 DQ_CA_OPEN = 0
3959 17:16:39.234753 DQ_SEMI_OPEN = 0
3960 17:16:39.237894 CA_SEMI_OPEN = 0
3961 17:16:39.237978 CA_FULL_RATE = 0
3962 17:16:39.241034 DQ_CKDIV4_EN = 1
3963 17:16:39.244652 CA_CKDIV4_EN = 1
3964 17:16:39.247976 CA_PREDIV_EN = 0
3965 17:16:39.251379 PH8_DLY = 0
3966 17:16:39.254380 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3967 17:16:39.254464 DQ_AAMCK_DIV = 4
3968 17:16:39.258164 CA_AAMCK_DIV = 4
3969 17:16:39.260923 CA_ADMCK_DIV = 4
3970 17:16:39.264352 DQ_TRACK_CA_EN = 0
3971 17:16:39.267880 CA_PICK = 600
3972 17:16:39.271263 CA_MCKIO = 600
3973 17:16:39.274462 MCKIO_SEMI = 0
3974 17:16:39.274546 PLL_FREQ = 2288
3975 17:16:39.277469
3976 17:16:39.277553 DQ_UI_PI_RATIO = 32
3977 17:16:39.280615 CA_UI_PI_RATIO = 0
3978 17:16:39.284197 ===================================
3979 17:16:39.287292 ===================================
3980 17:16:39.290950 memory_type:LPDDR4
3981 17:16:39.294192 GP_NUM : 10
3982 17:16:39.294277 SRAM_EN : 1
3983 17:16:39.297273 MD32_EN : 0
3984 17:16:39.300870 ===================================
3985 17:16:39.300956 [ANA_INIT] >>>>>>>>>>>>>>
3986 17:16:39.304299
3987 17:16:39.304384 <<<<<< [CONFIGURE PHASE]: ANA_TX
3988 17:16:39.307102 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3989 17:16:39.310478 ===================================
3990 17:16:39.313764 data_rate = 1200,PCW = 0X5800
3991 17:16:39.317240 ===================================
3992 17:16:39.320861 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3993 17:16:39.327041 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3994 17:16:39.333676 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3995 17:16:39.337147 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3996 17:16:39.340374 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3997 17:16:39.343398 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3998 17:16:39.346858 [ANA_INIT] flow start
3999 17:16:39.346943 [ANA_INIT] PLL >>>>>>>>
4000 17:16:39.350001 [ANA_INIT] PLL <<<<<<<<
4001 17:16:39.353506 [ANA_INIT] MIDPI >>>>>>>>
4002 17:16:39.356930 [ANA_INIT] MIDPI <<<<<<<<
4003 17:16:39.357014 [ANA_INIT] DLL >>>>>>>>
4004 17:16:39.359975 [ANA_INIT] flow end
4005 17:16:39.363506 ============ LP4 DIFF to SE enter ============
4006 17:16:39.366390 ============ LP4 DIFF to SE exit ============
4007 17:16:39.369689 [ANA_INIT] <<<<<<<<<<<<<
4008 17:16:39.373256 [Flow] Enable top DCM control >>>>>
4009 17:16:39.376427 [Flow] Enable top DCM control <<<<<
4010 17:16:39.379426 Enable DLL master slave shuffle
4011 17:16:39.386176 ==============================================================
4012 17:16:39.386263 Gating Mode config
4013 17:16:39.393422 ==============================================================
4014 17:16:39.393508 Config description:
4015 17:16:39.403002 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
4016 17:16:39.409200 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
4017 17:16:39.416117 SELPH_MODE 0: By rank 1: By Phase
4018 17:16:39.419294 ==============================================================
4019 17:16:39.422719 GAT_TRACK_EN = 1
4020 17:16:39.425882 RX_GATING_MODE = 2
4021 17:16:39.429267 RX_GATING_TRACK_MODE = 2
4022 17:16:39.432957 SELPH_MODE = 1
4023 17:16:39.435733 PICG_EARLY_EN = 1
4024 17:16:39.439364 VALID_LAT_VALUE = 1
4025 17:16:39.446256 ==============================================================
4026 17:16:39.448782 Enter into Gating configuration >>>>
4027 17:16:39.452341 Exit from Gating configuration <<<<
4028 17:16:39.455400 Enter into DVFS_PRE_config >>>>>
4029 17:16:39.465532 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
4030 17:16:39.468922 Exit from DVFS_PRE_config <<<<<
4031 17:16:39.471883 Enter into PICG configuration >>>>
4032 17:16:39.475297 Exit from PICG configuration <<<<
4033 17:16:39.478790 [RX_INPUT] configuration >>>>>
4034 17:16:39.478875 [RX_INPUT] configuration <<<<<
4035 17:16:39.481764
4036 17:16:39.485219 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
4037 17:16:39.492184 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
4038 17:16:39.498731 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
4039 17:16:39.501634 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
4040 17:16:39.508198 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
4041 17:16:39.514865 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
4042 17:16:39.518542 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
4043 17:16:39.525007 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
4044 17:16:39.528611 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
4045 17:16:39.531692 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
4046 17:16:39.534667 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
4047 17:16:39.541242 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
4048 17:16:39.544696 ===================================
4049 17:16:39.544787 LPDDR4 DRAM CONFIGURATION
4050 17:16:39.547793 ===================================
4051 17:16:39.551190 EX_ROW_EN[0] = 0x0
4052 17:16:39.554701 EX_ROW_EN[1] = 0x0
4053 17:16:39.554786 LP4Y_EN = 0x0
4054 17:16:39.557984 WORK_FSP = 0x0
4055 17:16:39.558069 WL = 0x2
4056 17:16:39.561020 RL = 0x2
4057 17:16:39.561105 BL = 0x2
4058 17:16:39.564557 RPST = 0x0
4059 17:16:39.564642 RD_PRE = 0x0
4060 17:16:39.567424 WR_PRE = 0x1
4061 17:16:39.567509 WR_PST = 0x0
4062 17:16:39.570996 DBI_WR = 0x0
4063 17:16:39.571080 DBI_RD = 0x0
4064 17:16:39.574069 OTF = 0x1
4065 17:16:39.577690 ===================================
4066 17:16:39.580843 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
4067 17:16:39.584285 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
4068 17:16:39.590879 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
4069 17:16:39.594245 ===================================
4070 17:16:39.594331 LPDDR4 DRAM CONFIGURATION
4071 17:16:39.597155 ===================================
4072 17:16:39.600530 EX_ROW_EN[0] = 0x10
4073 17:16:39.604227 EX_ROW_EN[1] = 0x0
4074 17:16:39.604313 LP4Y_EN = 0x0
4075 17:16:39.607498 WORK_FSP = 0x0
4076 17:16:39.607583 WL = 0x2
4077 17:16:39.610349 RL = 0x2
4078 17:16:39.610434 BL = 0x2
4079 17:16:39.613943 RPST = 0x0
4080 17:16:39.614028 RD_PRE = 0x0
4081 17:16:39.617140 WR_PRE = 0x1
4082 17:16:39.617224 WR_PST = 0x0
4083 17:16:39.620815 DBI_WR = 0x0
4084 17:16:39.620900 DBI_RD = 0x0
4085 17:16:39.624249 OTF = 0x1
4086 17:16:39.627095 ===================================
4087 17:16:39.633746 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
4088 17:16:39.636909 nWR fixed to 30
4089 17:16:39.640802 [ModeRegInit_LP4] CH0 RK0
4090 17:16:39.640888 [ModeRegInit_LP4] CH0 RK1
4091 17:16:39.643448 [ModeRegInit_LP4] CH1 RK0
4092 17:16:39.646946 [ModeRegInit_LP4] CH1 RK1
4093 17:16:39.647030 match AC timing 17
4094 17:16:39.653569 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
4095 17:16:39.657463 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
4096 17:16:39.660251 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
4097 17:16:39.666837 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
4098 17:16:39.670235 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
4099 17:16:39.670320 ==
4100 17:16:39.673775 Dram Type= 6, Freq= 0, CH_0, rank 0
4101 17:16:39.676894 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4102 17:16:39.676979 ==
4103 17:16:39.683474 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4104 17:16:39.689832 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4105 17:16:39.693254 [CA 0] Center 36 (6~66) winsize 61
4106 17:16:39.696380 [CA 1] Center 36 (6~66) winsize 61
4107 17:16:39.699714 [CA 2] Center 34 (4~64) winsize 61
4108 17:16:39.703340 [CA 3] Center 34 (4~65) winsize 62
4109 17:16:39.706734 [CA 4] Center 33 (3~64) winsize 62
4110 17:16:39.709697 [CA 5] Center 33 (3~64) winsize 62
4111 17:16:39.709783
4112 17:16:39.712742 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4113 17:16:39.712828
4114 17:16:39.716378 [CATrainingPosCal] consider 1 rank data
4115 17:16:39.719793 u2DelayCellTimex100 = 270/100 ps
4116 17:16:39.722771 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4117 17:16:39.726355 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4118 17:16:39.729265 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4119 17:16:39.733195 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4120 17:16:39.736164 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4121 17:16:39.739199
4122 17:16:39.742734 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4123 17:16:39.742820
4124 17:16:39.746617 CA PerBit enable=1, Macro0, CA PI delay=33
4125 17:16:39.746703
4126 17:16:39.749610 [CBTSetCACLKResult] CA Dly = 33
4127 17:16:39.749699 CS Dly: 4 (0~35)
4128 17:16:39.749767 ==
4129 17:16:39.752492 Dram Type= 6, Freq= 0, CH_0, rank 1
4130 17:16:39.759012 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4131 17:16:39.759098 ==
4132 17:16:39.762352 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4133 17:16:39.769227 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4134 17:16:39.772273 [CA 0] Center 36 (6~66) winsize 61
4135 17:16:39.775393 [CA 1] Center 36 (6~66) winsize 61
4136 17:16:39.778713 [CA 2] Center 34 (4~64) winsize 61
4137 17:16:39.782352 [CA 3] Center 34 (4~64) winsize 61
4138 17:16:39.785206 [CA 4] Center 33 (2~64) winsize 63
4139 17:16:39.788844 [CA 5] Center 33 (2~64) winsize 63
4140 17:16:39.788930
4141 17:16:39.792047 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4142 17:16:39.792133
4143 17:16:39.795563 [CATrainingPosCal] consider 2 rank data
4144 17:16:39.798502 u2DelayCellTimex100 = 270/100 ps
4145 17:16:39.802355 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4146 17:16:39.805445 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4147 17:16:39.808760
4148 17:16:39.811874 CA2 delay=34 (4~64),Diff = 1 PI (9 cell)
4149 17:16:39.815320 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4150 17:16:39.818348 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
4151 17:16:39.821739 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4152 17:16:39.821825
4153 17:16:39.825096 CA PerBit enable=1, Macro0, CA PI delay=33
4154 17:16:39.825183
4155 17:16:39.828087 [CBTSetCACLKResult] CA Dly = 33
4156 17:16:39.831502 CS Dly: 4 (0~36)
4157 17:16:39.831587
4158 17:16:39.834846 ----->DramcWriteLeveling(PI) begin...
4159 17:16:39.834933 ==
4160 17:16:39.838277 Dram Type= 6, Freq= 0, CH_0, rank 0
4161 17:16:39.841558 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4162 17:16:39.841645 ==
4163 17:16:39.844971 Write leveling (Byte 0): 33 => 33
4164 17:16:39.848572 Write leveling (Byte 1): 30 => 30
4165 17:16:39.851690 DramcWriteLeveling(PI) end<-----
4166 17:16:39.851776
4167 17:16:39.851843 ==
4168 17:16:39.854563 Dram Type= 6, Freq= 0, CH_0, rank 0
4169 17:16:39.858567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4170 17:16:39.858653 ==
4171 17:16:39.861502 [Gating] SW mode calibration
4172 17:16:39.868078 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4173 17:16:39.874259 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4174 17:16:39.877841 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4175 17:16:39.880855 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4176 17:16:39.887409 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4177 17:16:39.890709 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 0) (0 1)
4178 17:16:39.893713 0 9 16 | B1->B0 | 2f2f 2828 | 1 0 | (0 0) (0 0)
4179 17:16:39.900521 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4180 17:16:39.903447 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4181 17:16:39.906710 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4182 17:16:39.910182
4183 17:16:39.913294 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4184 17:16:39.916635 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4185 17:16:39.919946 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4186 17:16:39.923479
4187 17:16:39.926460 0 10 12 | B1->B0 | 2323 2d2d | 0 0 | (0 0) (0 0)
4188 17:16:39.930095 0 10 16 | B1->B0 | 3535 4242 | 0 0 | (0 0) (0 0)
4189 17:16:39.933436 0 10 20 | B1->B0 | 4545 4646 | 1 0 | (0 0) (0 0)
4190 17:16:39.940073 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4191 17:16:39.943069 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4192 17:16:39.946847 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4193 17:16:39.953162 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4194 17:16:39.956453 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4195 17:16:39.960002 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4196 17:16:39.966635 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
4197 17:16:39.970025 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4198 17:16:39.973191 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4199 17:16:39.979954 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4200 17:16:39.983027 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4201 17:16:39.986531 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4202 17:16:39.993015 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4203 17:16:39.996404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4204 17:16:39.999850 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4205 17:16:40.006375 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4206 17:16:40.009743 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4207 17:16:40.012950 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4208 17:16:40.019382 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4209 17:16:40.022877 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4210 17:16:40.026310 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4211 17:16:40.032889 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4212 17:16:40.036077 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4213 17:16:40.039233 Total UI for P1: 0, mck2ui 16
4214 17:16:40.042377 best dqsien dly found for B0: ( 0, 13, 14)
4215 17:16:40.046192 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4216 17:16:40.049152 Total UI for P1: 0, mck2ui 16
4217 17:16:40.052433 best dqsien dly found for B1: ( 0, 13, 16)
4218 17:16:40.055499 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4219 17:16:40.059127 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4220 17:16:40.062170
4221 17:16:40.065773 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4222 17:16:40.068868 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4223 17:16:40.072321 [Gating] SW calibration Done
4224 17:16:40.072409 ==
4225 17:16:40.075316 Dram Type= 6, Freq= 0, CH_0, rank 0
4226 17:16:40.078905 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4227 17:16:40.079000 ==
4228 17:16:40.079104 RX Vref Scan: 0
4229 17:16:40.082053
4230 17:16:40.082129
4231 17:16:40.082194 RX Vref 0 -> 0, step: 1
4232 17:16:40.082254
4233 17:16:40.085255 RX Delay -230 -> 252, step: 16
4234 17:16:40.088473 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4235 17:16:40.095592 iDelay=218, Bit 1, Center 49 (-102 ~ 201) 304
4236 17:16:40.098465 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4237 17:16:40.102057 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4238 17:16:40.105196 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4239 17:16:40.111905 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4240 17:16:40.114966 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4241 17:16:40.118402 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4242 17:16:40.121871 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4243 17:16:40.125033 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4244 17:16:40.131880 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4245 17:16:40.134925 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4246 17:16:40.138251 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4247 17:16:40.141872 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4248 17:16:40.148082 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4249 17:16:40.151637 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4250 17:16:40.151724 ==
4251 17:16:40.154936 Dram Type= 6, Freq= 0, CH_0, rank 0
4252 17:16:40.157835 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4253 17:16:40.157921 ==
4254 17:16:40.161494 DQS Delay:
4255 17:16:40.161579 DQS0 = 0, DQS1 = 0
4256 17:16:40.161646 DQM Delay:
4257 17:16:40.164472 DQM0 = 43, DQM1 = 31
4258 17:16:40.164557 DQ Delay:
4259 17:16:40.167819 DQ0 =41, DQ1 =49, DQ2 =41, DQ3 =33
4260 17:16:40.171339 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =49
4261 17:16:40.174376 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =25
4262 17:16:40.177853 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4263 17:16:40.177939
4264 17:16:40.178007
4265 17:16:40.178069 ==
4266 17:16:40.180917
4267 17:16:40.181003 Dram Type= 6, Freq= 0, CH_0, rank 0
4268 17:16:40.188023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4269 17:16:40.188114 ==
4270 17:16:40.188181
4271 17:16:40.188243
4272 17:16:40.188303 TX Vref Scan disable
4273 17:16:40.190928
4274 17:16:40.191014 == TX Byte 0 ==
4275 17:16:40.194515 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4276 17:16:40.200815 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4277 17:16:40.200913 == TX Byte 1 ==
4278 17:16:40.204479 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4279 17:16:40.211242 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4280 17:16:40.211328 ==
4281 17:16:40.214318 Dram Type= 6, Freq= 0, CH_0, rank 0
4282 17:16:40.217711 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4283 17:16:40.217797 ==
4284 17:16:40.217863
4285 17:16:40.217926
4286 17:16:40.220773 TX Vref Scan disable
4287 17:16:40.224129 == TX Byte 0 ==
4288 17:16:40.227510 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4289 17:16:40.230864 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4290 17:16:40.233832 == TX Byte 1 ==
4291 17:16:40.237476 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4292 17:16:40.240758 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4293 17:16:40.240843
4294 17:16:40.244264 [DATLAT]
4295 17:16:40.244348 Freq=600, CH0 RK0
4296 17:16:40.244415
4297 17:16:40.247750 DATLAT Default: 0x9
4298 17:16:40.247834 0, 0xFFFF, sum = 0
4299 17:16:40.250458 1, 0xFFFF, sum = 0
4300 17:16:40.250544 2, 0xFFFF, sum = 0
4301 17:16:40.253871 3, 0xFFFF, sum = 0
4302 17:16:40.253958 4, 0xFFFF, sum = 0
4303 17:16:40.257301 5, 0xFFFF, sum = 0
4304 17:16:40.257423 6, 0xFFFF, sum = 0
4305 17:16:40.260894 7, 0xFFFF, sum = 0
4306 17:16:40.260979 8, 0x0, sum = 1
4307 17:16:40.263614 9, 0x0, sum = 2
4308 17:16:40.263701 10, 0x0, sum = 3
4309 17:16:40.267116 11, 0x0, sum = 4
4310 17:16:40.267205 best_step = 9
4311 17:16:40.267272
4312 17:16:40.267334 ==
4313 17:16:40.270192 Dram Type= 6, Freq= 0, CH_0, rank 0
4314 17:16:40.276829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4315 17:16:40.276914 ==
4316 17:16:40.276991 RX Vref Scan: 1
4317 17:16:40.277054
4318 17:16:40.280209 RX Vref 0 -> 0, step: 1
4319 17:16:40.280294
4320 17:16:40.283774 RX Delay -195 -> 252, step: 8
4321 17:16:40.283859
4322 17:16:40.286902 Set Vref, RX VrefLevel [Byte0]: 57
4323 17:16:40.290085 [Byte1]: 47
4324 17:16:40.290174
4325 17:16:40.293470 Final RX Vref Byte 0 = 57 to rank0
4326 17:16:40.297036 Final RX Vref Byte 1 = 47 to rank0
4327 17:16:40.300251 Final RX Vref Byte 0 = 57 to rank1
4328 17:16:40.303348 Final RX Vref Byte 1 = 47 to rank1==
4329 17:16:40.307026 Dram Type= 6, Freq= 0, CH_0, rank 0
4330 17:16:40.310231 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4331 17:16:40.310316 ==
4332 17:16:40.313850 DQS Delay:
4333 17:16:40.313934 DQS0 = 0, DQS1 = 0
4334 17:16:40.314000 DQM Delay:
4335 17:16:40.316765 DQM0 = 44, DQM1 = 33
4336 17:16:40.316860 DQ Delay:
4337 17:16:40.319868 DQ0 =44, DQ1 =44, DQ2 =40, DQ3 =44
4338 17:16:40.323387 DQ4 =44, DQ5 =36, DQ6 =52, DQ7 =52
4339 17:16:40.326622 DQ8 =20, DQ9 =20, DQ10 =36, DQ11 =28
4340 17:16:40.330059 DQ12 =40, DQ13 =36, DQ14 =44, DQ15 =44
4341 17:16:40.330144
4342 17:16:40.330212
4343 17:16:40.339884 [DQSOSCAuto] RK0, (LSB)MR18= 0x663e, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 390 ps
4344 17:16:40.343088 CH0 RK0: MR19=808, MR18=663E
4345 17:16:40.346421 CH0_RK0: MR19=0x808, MR18=0x663E, DQSOSC=390, MR23=63, INC=172, DEC=114
4346 17:16:40.346506
4347 17:16:40.349933
4348 17:16:40.350018 ----->DramcWriteLeveling(PI) begin...
4349 17:16:40.352936
4350 17:16:40.353021 ==
4351 17:16:40.356203 Dram Type= 6, Freq= 0, CH_0, rank 1
4352 17:16:40.359532 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4353 17:16:40.359617 ==
4354 17:16:40.362815 Write leveling (Byte 0): 35 => 35
4355 17:16:40.366210 Write leveling (Byte 1): 30 => 30
4356 17:16:40.369470 DramcWriteLeveling(PI) end<-----
4357 17:16:40.369553
4358 17:16:40.369624 ==
4359 17:16:40.372734 Dram Type= 6, Freq= 0, CH_0, rank 1
4360 17:16:40.376522 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4361 17:16:40.376606 ==
4362 17:16:40.379424 [Gating] SW mode calibration
4363 17:16:40.386308 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4364 17:16:40.392415 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4365 17:16:40.396006 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4366 17:16:40.399029 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4367 17:16:40.406094 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4368 17:16:40.409198 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4369 17:16:40.412451 0 9 16 | B1->B0 | 2f2f 2a2a | 1 0 | (1 0) (1 1)
4370 17:16:40.419076 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4371 17:16:40.422483 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4372 17:16:40.425914 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4373 17:16:40.432629 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4374 17:16:40.435910 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4375 17:16:40.439245 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4376 17:16:40.445538 0 10 12 | B1->B0 | 2323 2828 | 1 1 | (0 0) (0 0)
4377 17:16:40.448927 0 10 16 | B1->B0 | 3d3d 4040 | 0 0 | (0 0) (0 0)
4378 17:16:40.452513 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4379 17:16:40.458513 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4380 17:16:40.461946 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4381 17:16:40.465160 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4382 17:16:40.472066 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4383 17:16:40.475062 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4384 17:16:40.478680 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4385 17:16:40.485371 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4386 17:16:40.488424 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4387 17:16:40.492011 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4388 17:16:40.498227 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4389 17:16:40.501648 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4390 17:16:40.504759 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4391 17:16:40.511609 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4392 17:16:40.514727 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4393 17:16:40.518250 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4394 17:16:40.524736 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4395 17:16:40.527834 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4396 17:16:40.531213 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4397 17:16:40.537935 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4398 17:16:40.541433 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4399 17:16:40.544538 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4400 17:16:40.551043 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4401 17:16:40.554391 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4402 17:16:40.557826 Total UI for P1: 0, mck2ui 16
4403 17:16:40.561059 best dqsien dly found for B0: ( 0, 13, 14)
4404 17:16:40.564592 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4405 17:16:40.567440 Total UI for P1: 0, mck2ui 16
4406 17:16:40.570836 best dqsien dly found for B1: ( 0, 13, 16)
4407 17:16:40.574251 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4408 17:16:40.577572 best DQS1 dly(MCK, UI, PI) = (0, 13, 16)
4409 17:16:40.577652
4410 17:16:40.584283 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4411 17:16:40.587280 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 16)
4412 17:16:40.587364 [Gating] SW calibration Done
4413 17:16:40.590340 ==
4414 17:16:40.593956 Dram Type= 6, Freq= 0, CH_0, rank 1
4415 17:16:40.597100 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4416 17:16:40.597190 ==
4417 17:16:40.597256 RX Vref Scan: 0
4418 17:16:40.597318
4419 17:16:40.600601 RX Vref 0 -> 0, step: 1
4420 17:16:40.600684
4421 17:16:40.603800 RX Delay -230 -> 252, step: 16
4422 17:16:40.607233 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4423 17:16:40.610824 iDelay=218, Bit 1, Center 57 (-102 ~ 217) 320
4424 17:16:40.613631
4425 17:16:40.617101 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4426 17:16:40.620444 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4427 17:16:40.623668 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4428 17:16:40.626686 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4429 17:16:40.633618 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4430 17:16:40.636958 iDelay=218, Bit 7, Center 57 (-102 ~ 217) 320
4431 17:16:40.640015 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4432 17:16:40.643375 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4433 17:16:40.650048 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4434 17:16:40.653110 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4435 17:16:40.656462 iDelay=218, Bit 12, Center 49 (-102 ~ 201) 304
4436 17:16:40.659830 iDelay=218, Bit 13, Center 49 (-102 ~ 201) 304
4437 17:16:40.666395 iDelay=218, Bit 14, Center 57 (-102 ~ 217) 320
4438 17:16:40.669922 iDelay=218, Bit 15, Center 49 (-102 ~ 201) 304
4439 17:16:40.670010 ==
4440 17:16:40.672913 Dram Type= 6, Freq= 0, CH_0, rank 1
4441 17:16:40.676306 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 17:16:40.676390 ==
4443 17:16:40.679727 DQS Delay:
4444 17:16:40.679810 DQS0 = 0, DQS1 = 0
4445 17:16:40.679875 DQM Delay:
4446 17:16:40.682824 DQM0 = 46, DQM1 = 39
4447 17:16:40.682907 DQ Delay:
4448 17:16:40.686354 DQ0 =41, DQ1 =57, DQ2 =41, DQ3 =41
4449 17:16:40.689446 DQ4 =41, DQ5 =33, DQ6 =57, DQ7 =57
4450 17:16:40.692841 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =25
4451 17:16:40.695877 DQ12 =49, DQ13 =49, DQ14 =57, DQ15 =49
4452 17:16:40.695960
4453 17:16:40.696025
4454 17:16:40.696085 ==
4455 17:16:40.699332 Dram Type= 6, Freq= 0, CH_0, rank 1
4456 17:16:40.706130 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4457 17:16:40.706215 ==
4458 17:16:40.706281
4459 17:16:40.706342
4460 17:16:40.706401 TX Vref Scan disable
4461 17:16:40.709732 == TX Byte 0 ==
4462 17:16:40.713045 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4463 17:16:40.716250 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4464 17:16:40.719717
4465 17:16:40.719801 == TX Byte 1 ==
4466 17:16:40.723000 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4467 17:16:40.729980 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4468 17:16:40.730064 ==
4469 17:16:40.733255 Dram Type= 6, Freq= 0, CH_0, rank 1
4470 17:16:40.736194 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4471 17:16:40.736277 ==
4472 17:16:40.736342
4473 17:16:40.736402
4474 17:16:40.739465 TX Vref Scan disable
4475 17:16:40.743121 == TX Byte 0 ==
4476 17:16:40.746609 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
4477 17:16:40.749540 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
4478 17:16:40.753111 == TX Byte 1 ==
4479 17:16:40.755769 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4480 17:16:40.759137 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4481 17:16:40.759217
4482 17:16:40.759282 [DATLAT]
4483 17:16:40.762512 Freq=600, CH0 RK1
4484 17:16:40.762586
4485 17:16:40.765744 DATLAT Default: 0x9
4486 17:16:40.765822 0, 0xFFFF, sum = 0
4487 17:16:40.769125 1, 0xFFFF, sum = 0
4488 17:16:40.769212 2, 0xFFFF, sum = 0
4489 17:16:40.772622 3, 0xFFFF, sum = 0
4490 17:16:40.772708 4, 0xFFFF, sum = 0
4491 17:16:40.776201 5, 0xFFFF, sum = 0
4492 17:16:40.776287 6, 0xFFFF, sum = 0
4493 17:16:40.779178 7, 0xFFFF, sum = 0
4494 17:16:40.779264 8, 0x0, sum = 1
4495 17:16:40.782579 9, 0x0, sum = 2
4496 17:16:40.782670 10, 0x0, sum = 3
4497 17:16:40.785632 11, 0x0, sum = 4
4498 17:16:40.785718 best_step = 9
4499 17:16:40.785785
4500 17:16:40.785847 ==
4501 17:16:40.789292 Dram Type= 6, Freq= 0, CH_0, rank 1
4502 17:16:40.792171 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4503 17:16:40.792257 ==
4504 17:16:40.795976 RX Vref Scan: 0
4505 17:16:40.796061
4506 17:16:40.799429 RX Vref 0 -> 0, step: 1
4507 17:16:40.799513
4508 17:16:40.799581 RX Delay -179 -> 252, step: 8
4509 17:16:40.806889 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4510 17:16:40.810425 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4511 17:16:40.813556 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4512 17:16:40.816827 iDelay=205, Bit 3, Center 40 (-115 ~ 196) 312
4513 17:16:40.823536 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4514 17:16:40.826745 iDelay=205, Bit 5, Center 32 (-123 ~ 188) 312
4515 17:16:40.830074 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4516 17:16:40.833247 iDelay=205, Bit 7, Center 52 (-99 ~ 204) 304
4517 17:16:40.836716 iDelay=205, Bit 8, Center 28 (-123 ~ 180) 304
4518 17:16:40.843666 iDelay=205, Bit 9, Center 20 (-131 ~ 172) 304
4519 17:16:40.846963 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4520 17:16:40.850337 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4521 17:16:40.853215 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4522 17:16:40.860229 iDelay=205, Bit 13, Center 44 (-107 ~ 196) 304
4523 17:16:40.863484 iDelay=205, Bit 14, Center 48 (-99 ~ 196) 296
4524 17:16:40.866812 iDelay=205, Bit 15, Center 44 (-107 ~ 196) 304
4525 17:16:40.866898 ==
4526 17:16:40.869998 Dram Type= 6, Freq= 0, CH_0, rank 1
4527 17:16:40.873257 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4528 17:16:40.876372 ==
4529 17:16:40.876457 DQS Delay:
4530 17:16:40.876542 DQS0 = 0, DQS1 = 0
4531 17:16:40.879709 DQM Delay:
4532 17:16:40.879794 DQM0 = 42, DQM1 = 37
4533 17:16:40.882844 DQ Delay:
4534 17:16:40.882929 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =40
4535 17:16:40.886354
4536 17:16:40.886440 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =52
4537 17:16:40.889779 DQ8 =28, DQ9 =20, DQ10 =40, DQ11 =28
4538 17:16:40.892860 DQ12 =44, DQ13 =44, DQ14 =48, DQ15 =44
4539 17:16:40.896447
4540 17:16:40.896532
4541 17:16:40.902774 [DQSOSCAuto] RK1, (LSB)MR18= 0x5c0f, (MSB)MR19= 0x808, tDQSOscB0 = 407 ps tDQSOscB1 = 392 ps
4542 17:16:40.906283 CH0 RK1: MR19=808, MR18=5C0F
4543 17:16:40.912892 CH0_RK1: MR19=0x808, MR18=0x5C0F, DQSOSC=392, MR23=63, INC=170, DEC=113
4544 17:16:40.916336 [RxdqsGatingPostProcess] freq 600
4545 17:16:40.919645 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4546 17:16:40.922798 Pre-setting of DQS Precalculation
4547 17:16:40.929078 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4548 17:16:40.929164 ==
4549 17:16:40.932704 Dram Type= 6, Freq= 0, CH_1, rank 0
4550 17:16:40.936153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4551 17:16:40.936239 ==
4552 17:16:40.942628 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4553 17:16:40.946184 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
4554 17:16:40.950233 [CA 0] Center 35 (5~66) winsize 62
4555 17:16:40.953704 [CA 1] Center 35 (5~66) winsize 62
4556 17:16:40.957251 [CA 2] Center 34 (4~65) winsize 62
4557 17:16:40.960059 [CA 3] Center 33 (3~64) winsize 62
4558 17:16:40.963601 [CA 4] Center 34 (4~65) winsize 62
4559 17:16:40.966949 [CA 5] Center 33 (3~64) winsize 62
4560 17:16:40.967052
4561 17:16:40.970241 [CmdBusTrainingLP45] Vref(ca) range 1: 33
4562 17:16:40.970326
4563 17:16:40.973209 [CATrainingPosCal] consider 1 rank data
4564 17:16:40.976682 u2DelayCellTimex100 = 270/100 ps
4565 17:16:40.980222 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4566 17:16:40.986543 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4567 17:16:40.989783 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4568 17:16:40.993280 CA3 delay=33 (3~64),Diff = 0 PI (0 cell)
4569 17:16:40.996402 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4570 17:16:40.999715 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4571 17:16:40.999800
4572 17:16:41.003173 CA PerBit enable=1, Macro0, CA PI delay=33
4573 17:16:41.003296
4574 17:16:41.006164 [CBTSetCACLKResult] CA Dly = 33
4575 17:16:41.009878 CS Dly: 5 (0~36)
4576 17:16:41.009962 ==
4577 17:16:41.012775 Dram Type= 6, Freq= 0, CH_1, rank 1
4578 17:16:41.016360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4579 17:16:41.016445 ==
4580 17:16:41.022811 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4581 17:16:41.026195 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4582 17:16:41.030371 [CA 0] Center 35 (5~66) winsize 62
4583 17:16:41.033718 [CA 1] Center 36 (6~66) winsize 61
4584 17:16:41.036825 [CA 2] Center 34 (4~65) winsize 62
4585 17:16:41.040361 [CA 3] Center 34 (4~65) winsize 62
4586 17:16:41.043487 [CA 4] Center 34 (4~65) winsize 62
4587 17:16:41.046930 [CA 5] Center 33 (3~64) winsize 62
4588 17:16:41.047014
4589 17:16:41.050295 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4590 17:16:41.050381
4591 17:16:41.053326 [CATrainingPosCal] consider 2 rank data
4592 17:16:41.056703 u2DelayCellTimex100 = 270/100 ps
4593 17:16:41.059907 CA0 delay=35 (5~66),Diff = 2 PI (19 cell)
4594 17:16:41.063105
4595 17:16:41.066530 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4596 17:16:41.069807 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4597 17:16:41.073211 CA3 delay=34 (4~64),Diff = 1 PI (9 cell)
4598 17:16:41.076661 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4599 17:16:41.079649 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4600 17:16:41.079734
4601 17:16:41.082865 CA PerBit enable=1, Macro0, CA PI delay=33
4602 17:16:41.082950
4603 17:16:41.086270 [CBTSetCACLKResult] CA Dly = 33
4604 17:16:41.089491 CS Dly: 5 (0~37)
4605 17:16:41.089576
4606 17:16:41.093119 ----->DramcWriteLeveling(PI) begin...
4607 17:16:41.093205 ==
4608 17:16:41.096093 Dram Type= 6, Freq= 0, CH_1, rank 0
4609 17:16:41.099874 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4610 17:16:41.099960 ==
4611 17:16:41.102731 Write leveling (Byte 0): 29 => 29
4612 17:16:41.106175 Write leveling (Byte 1): 32 => 32
4613 17:16:41.109496 DramcWriteLeveling(PI) end<-----
4614 17:16:41.109581
4615 17:16:41.109647 ==
4616 17:16:41.112840 Dram Type= 6, Freq= 0, CH_1, rank 0
4617 17:16:41.116120 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4618 17:16:41.116205 ==
4619 17:16:41.119078 [Gating] SW mode calibration
4620 17:16:41.125832 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4621 17:16:41.132504 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4622 17:16:41.135850 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4623 17:16:41.139389 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4624 17:16:41.145533 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4625 17:16:41.149247 0 9 12 | B1->B0 | 3131 2e2e | 1 1 | (1 1) (1 0)
4626 17:16:41.152593 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4627 17:16:41.158830 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4628 17:16:41.162073 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4629 17:16:41.165641 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4630 17:16:41.172493 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4631 17:16:41.175282 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4632 17:16:41.178554 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4633 17:16:41.185394 0 10 12 | B1->B0 | 3030 3535 | 1 1 | (0 0) (0 0)
4634 17:16:41.188613 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4635 17:16:41.191863 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4636 17:16:41.198438 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4637 17:16:41.201997 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4638 17:16:41.205283 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4639 17:16:41.212068 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4640 17:16:41.215477 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4641 17:16:41.218463 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
4642 17:16:41.225004 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4643 17:16:41.228490 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4644 17:16:41.231865 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4645 17:16:41.238172 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4646 17:16:41.241828 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4647 17:16:41.244666 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4648 17:16:41.251562 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4649 17:16:41.254516 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4650 17:16:41.258120 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4651 17:16:41.264468 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4652 17:16:41.268143 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4653 17:16:41.270820 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4654 17:16:41.277493 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4655 17:16:41.281204 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4656 17:16:41.284411 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4657 17:16:41.291131 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4658 17:16:41.294201 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4659 17:16:41.297737 Total UI for P1: 0, mck2ui 16
4660 17:16:41.300890 best dqsien dly found for B0: ( 0, 13, 12)
4661 17:16:41.304330 Total UI for P1: 0, mck2ui 16
4662 17:16:41.307312 best dqsien dly found for B1: ( 0, 13, 12)
4663 17:16:41.310944 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4664 17:16:41.313882 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4665 17:16:41.313967
4666 17:16:41.317514 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4667 17:16:41.320694 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4668 17:16:41.323840 [Gating] SW calibration Done
4669 17:16:41.323924 ==
4670 17:16:41.327136 Dram Type= 6, Freq= 0, CH_1, rank 0
4671 17:16:41.334160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4672 17:16:41.334246 ==
4673 17:16:41.334313 RX Vref Scan: 0
4674 17:16:41.334376
4675 17:16:41.337664 RX Vref 0 -> 0, step: 1
4676 17:16:41.337749
4677 17:16:41.340488 RX Delay -230 -> 252, step: 16
4678 17:16:41.344060 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4679 17:16:41.347052 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4680 17:16:41.350397 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4681 17:16:41.357248 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4682 17:16:41.360439 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4683 17:16:41.363389 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4684 17:16:41.366737 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4685 17:16:41.373545 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4686 17:16:41.376659 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4687 17:16:41.380065 iDelay=218, Bit 9, Center 33 (-134 ~ 201) 336
4688 17:16:41.383800 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4689 17:16:41.389906 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4690 17:16:41.393560 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4691 17:16:41.396508 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4692 17:16:41.399697 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4693 17:16:41.406429 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4694 17:16:41.406514 ==
4695 17:16:41.409928 Dram Type= 6, Freq= 0, CH_1, rank 0
4696 17:16:41.413327 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4697 17:16:41.413413 ==
4698 17:16:41.413480 DQS Delay:
4699 17:16:41.416586 DQS0 = 0, DQS1 = 0
4700 17:16:41.416671 DQM Delay:
4701 17:16:41.419921 DQM0 = 45, DQM1 = 38
4702 17:16:41.420006 DQ Delay:
4703 17:16:41.422903 DQ0 =49, DQ1 =41, DQ2 =33, DQ3 =41
4704 17:16:41.426144 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =41
4705 17:16:41.429992 DQ8 =17, DQ9 =33, DQ10 =33, DQ11 =25
4706 17:16:41.433218 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =49
4707 17:16:41.433305
4708 17:16:41.433395
4709 17:16:41.433458 ==
4710 17:16:41.436127 Dram Type= 6, Freq= 0, CH_1, rank 0
4711 17:16:41.439510 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4712 17:16:41.439596 ==
4713 17:16:41.439662
4714 17:16:41.442766
4715 17:16:41.442851
4716 17:16:41.442918 TX Vref Scan disable
4717 17:16:41.446291 == TX Byte 0 ==
4718 17:16:41.449289 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4719 17:16:41.452970 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4720 17:16:41.456425 == TX Byte 1 ==
4721 17:16:41.459345 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4722 17:16:41.462844 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4723 17:16:41.462928 ==
4724 17:16:41.465941 Dram Type= 6, Freq= 0, CH_1, rank 0
4725 17:16:41.472768 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4726 17:16:41.472854 ==
4727 17:16:41.472921
4728 17:16:41.472984
4729 17:16:41.473043 TX Vref Scan disable
4730 17:16:41.477590 == TX Byte 0 ==
4731 17:16:41.480971 Update DQ dly =574 (2 ,1, 30) DQ OEN =(1 ,6)
4732 17:16:41.484302 Update DQM dly =574 (2 ,1, 30) DQM OEN =(1 ,6)
4733 17:16:41.487147
4734 17:16:41.487231 == TX Byte 1 ==
4735 17:16:41.490283 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4736 17:16:41.497164 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4737 17:16:41.497266
4738 17:16:41.497357 [DATLAT]
4739 17:16:41.497422 Freq=600, CH1 RK0
4740 17:16:41.497482
4741 17:16:41.500782 DATLAT Default: 0x9
4742 17:16:41.500866 0, 0xFFFF, sum = 0
4743 17:16:41.503850 1, 0xFFFF, sum = 0
4744 17:16:41.503936 2, 0xFFFF, sum = 0
4745 17:16:41.507240 3, 0xFFFF, sum = 0
4746 17:16:41.510329 4, 0xFFFF, sum = 0
4747 17:16:41.510415 5, 0xFFFF, sum = 0
4748 17:16:41.513888 6, 0xFFFF, sum = 0
4749 17:16:41.513974 7, 0xFFFF, sum = 0
4750 17:16:41.517265 8, 0x0, sum = 1
4751 17:16:41.517394 9, 0x0, sum = 2
4752 17:16:41.517465 10, 0x0, sum = 3
4753 17:16:41.520330 11, 0x0, sum = 4
4754 17:16:41.520418 best_step = 9
4755 17:16:41.520486
4756 17:16:41.520549 ==
4757 17:16:41.523774 Dram Type= 6, Freq= 0, CH_1, rank 0
4758 17:16:41.530348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4759 17:16:41.530435 ==
4760 17:16:41.530502 RX Vref Scan: 1
4761 17:16:41.530563
4762 17:16:41.533701 RX Vref 0 -> 0, step: 1
4763 17:16:41.533786
4764 17:16:41.536969 RX Delay -195 -> 252, step: 8
4765 17:16:41.537054
4766 17:16:41.540218 Set Vref, RX VrefLevel [Byte0]: 47
4767 17:16:41.543432 [Byte1]: 60
4768 17:16:41.543519
4769 17:16:41.546985 Final RX Vref Byte 0 = 47 to rank0
4770 17:16:41.550142 Final RX Vref Byte 1 = 60 to rank0
4771 17:16:41.553742 Final RX Vref Byte 0 = 47 to rank1
4772 17:16:41.556569 Final RX Vref Byte 1 = 60 to rank1==
4773 17:16:41.560142 Dram Type= 6, Freq= 0, CH_1, rank 0
4774 17:16:41.563795 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 17:16:41.563881 ==
4776 17:16:41.566713 DQS Delay:
4777 17:16:41.566799 DQS0 = 0, DQS1 = 0
4778 17:16:41.570140 DQM Delay:
4779 17:16:41.570233 DQM0 = 46, DQM1 = 38
4780 17:16:41.570311 DQ Delay:
4781 17:16:41.573311
4782 17:16:41.573396 DQ0 =52, DQ1 =44, DQ2 =36, DQ3 =44
4783 17:16:41.576385 DQ4 =44, DQ5 =56, DQ6 =56, DQ7 =40
4784 17:16:41.579740 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4785 17:16:41.583374 DQ12 =48, DQ13 =48, DQ14 =44, DQ15 =48
4786 17:16:41.583464
4787 17:16:41.583532
4788 17:16:41.586408
4789 17:16:41.593070 [DQSOSCAuto] RK0, (LSB)MR18= 0x4f33, (MSB)MR19= 0x808, tDQSOscB0 = 400 ps tDQSOscB1 = 394 ps
4790 17:16:41.596209 CH1 RK0: MR19=808, MR18=4F33
4791 17:16:41.603023 CH1_RK0: MR19=0x808, MR18=0x4F33, DQSOSC=394, MR23=63, INC=168, DEC=112
4792 17:16:41.603109
4793 17:16:41.606310 ----->DramcWriteLeveling(PI) begin...
4794 17:16:41.606397 ==
4795 17:16:41.609540 Dram Type= 6, Freq= 0, CH_1, rank 1
4796 17:16:41.613108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4797 17:16:41.613194 ==
4798 17:16:41.616331 Write leveling (Byte 0): 30 => 30
4799 17:16:41.619645 Write leveling (Byte 1): 29 => 29
4800 17:16:41.622967 DramcWriteLeveling(PI) end<-----
4801 17:16:41.623053
4802 17:16:41.623120 ==
4803 17:16:41.625994 Dram Type= 6, Freq= 0, CH_1, rank 1
4804 17:16:41.629662 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4805 17:16:41.629748 ==
4806 17:16:41.632571 [Gating] SW mode calibration
4807 17:16:41.639516 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4808 17:16:41.646153 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4809 17:16:41.649153 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4810 17:16:41.652805 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4811 17:16:41.659528 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4812 17:16:41.662565 0 9 12 | B1->B0 | 3030 3434 | 0 1 | (0 1) (1 0)
4813 17:16:41.665654 0 9 16 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
4814 17:16:41.672387 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4815 17:16:41.675625 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4816 17:16:41.678859 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4817 17:16:41.685562 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4818 17:16:41.689072 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4819 17:16:41.692127 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4820 17:16:41.698541 0 10 12 | B1->B0 | 3232 2525 | 0 0 | (0 0) (0 0)
4821 17:16:41.701865 0 10 16 | B1->B0 | 4646 3c3c | 0 0 | (0 0) (0 0)
4822 17:16:41.705454 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4823 17:16:41.711924 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4824 17:16:41.714982 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4825 17:16:41.718623 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4826 17:16:41.725070 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4827 17:16:41.728233 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4828 17:16:41.731963 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
4829 17:16:41.738518 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4830 17:16:41.741820 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4831 17:16:41.745346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4832 17:16:41.751735 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4833 17:16:41.754887 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4834 17:16:41.758258 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4835 17:16:41.764579 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4836 17:16:41.768142 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4837 17:16:41.771683 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4838 17:16:41.778118 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4839 17:16:41.781098 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4840 17:16:41.784502 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4841 17:16:41.791036 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4842 17:16:41.794477 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4843 17:16:41.797552 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4844 17:16:41.804250 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4845 17:16:41.807454 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4846 17:16:41.810800 Total UI for P1: 0, mck2ui 16
4847 17:16:41.814465 best dqsien dly found for B0: ( 0, 13, 14)
4848 17:16:41.817508 Total UI for P1: 0, mck2ui 16
4849 17:16:41.820944 best dqsien dly found for B1: ( 0, 13, 14)
4850 17:16:41.824036 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4851 17:16:41.827578 best DQS1 dly(MCK, UI, PI) = (0, 13, 14)
4852 17:16:41.827664
4853 17:16:41.830770 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4854 17:16:41.837222 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 14)
4855 17:16:41.837307 [Gating] SW calibration Done
4856 17:16:41.837415 ==
4857 17:16:41.840708 Dram Type= 6, Freq= 0, CH_1, rank 1
4858 17:16:41.847004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4859 17:16:41.847091 ==
4860 17:16:41.847158 RX Vref Scan: 0
4861 17:16:41.847219
4862 17:16:41.850451 RX Vref 0 -> 0, step: 1
4863 17:16:41.850537
4864 17:16:41.854132 RX Delay -230 -> 252, step: 16
4865 17:16:41.857039 iDelay=218, Bit 0, Center 49 (-102 ~ 201) 304
4866 17:16:41.860418 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4867 17:16:41.866867 iDelay=218, Bit 2, Center 25 (-134 ~ 185) 320
4868 17:16:41.870376 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4869 17:16:41.873390 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4870 17:16:41.876921 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4871 17:16:41.880266 iDelay=218, Bit 6, Center 57 (-102 ~ 217) 320
4872 17:16:41.886776 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4873 17:16:41.890142 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4874 17:16:41.893286 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4875 17:16:41.896743 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4876 17:16:41.903222 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4877 17:16:41.906585 iDelay=218, Bit 12, Center 57 (-102 ~ 217) 320
4878 17:16:41.909808 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4879 17:16:41.913407 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4880 17:16:41.919957 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4881 17:16:41.920037 ==
4882 17:16:41.923327 Dram Type= 6, Freq= 0, CH_1, rank 1
4883 17:16:41.926883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4884 17:16:41.926970 ==
4885 17:16:41.927038 DQS Delay:
4886 17:16:41.929810 DQS0 = 0, DQS1 = 0
4887 17:16:41.929895 DQM Delay:
4888 17:16:41.932932 DQM0 = 43, DQM1 = 40
4889 17:16:41.933017 DQ Delay:
4890 17:16:41.936395 DQ0 =49, DQ1 =41, DQ2 =25, DQ3 =41
4891 17:16:41.939701 DQ4 =41, DQ5 =57, DQ6 =57, DQ7 =33
4892 17:16:41.942944 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4893 17:16:41.946155 DQ12 =57, DQ13 =49, DQ14 =49, DQ15 =49
4894 17:16:41.946241
4895 17:16:41.946309
4896 17:16:41.946371 ==
4897 17:16:41.949602 Dram Type= 6, Freq= 0, CH_1, rank 1
4898 17:16:41.953209 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4899 17:16:41.953295 ==
4900 17:16:41.956274
4901 17:16:41.956360
4902 17:16:41.956427
4903 17:16:41.956488 TX Vref Scan disable
4904 17:16:41.959661 == TX Byte 0 ==
4905 17:16:41.962703 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4906 17:16:41.965866 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4907 17:16:41.969124 == TX Byte 1 ==
4908 17:16:41.972807 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4909 17:16:41.975629 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4910 17:16:41.978998
4911 17:16:41.979083 ==
4912 17:16:41.982395 Dram Type= 6, Freq= 0, CH_1, rank 1
4913 17:16:41.985720 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4914 17:16:41.985807 ==
4915 17:16:41.985874
4916 17:16:41.985938
4917 17:16:41.989135 TX Vref Scan disable
4918 17:16:41.989221 == TX Byte 0 ==
4919 17:16:41.992596
4920 17:16:41.995648 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
4921 17:16:41.999400 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
4922 17:16:42.002133 == TX Byte 1 ==
4923 17:16:42.005337 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4924 17:16:42.008994 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4925 17:16:42.009081
4926 17:16:42.009149 [DATLAT]
4927 17:16:42.011976 Freq=600, CH1 RK1
4928 17:16:42.012063
4929 17:16:42.014942 DATLAT Default: 0x9
4930 17:16:42.015028 0, 0xFFFF, sum = 0
4931 17:16:42.018557 1, 0xFFFF, sum = 0
4932 17:16:42.018645 2, 0xFFFF, sum = 0
4933 17:16:42.021989 3, 0xFFFF, sum = 0
4934 17:16:42.022076 4, 0xFFFF, sum = 0
4935 17:16:42.025145 5, 0xFFFF, sum = 0
4936 17:16:42.025233 6, 0xFFFF, sum = 0
4937 17:16:42.028664 7, 0xFFFF, sum = 0
4938 17:16:42.028752 8, 0x0, sum = 1
4939 17:16:42.031822 9, 0x0, sum = 2
4940 17:16:42.031910 10, 0x0, sum = 3
4941 17:16:42.034750 11, 0x0, sum = 4
4942 17:16:42.034837 best_step = 9
4943 17:16:42.034904
4944 17:16:42.034967 ==
4945 17:16:42.038119 Dram Type= 6, Freq= 0, CH_1, rank 1
4946 17:16:42.041567 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4947 17:16:42.044504 ==
4948 17:16:42.044590 RX Vref Scan: 0
4949 17:16:42.044657
4950 17:16:42.048255 RX Vref 0 -> 0, step: 1
4951 17:16:42.048342
4952 17:16:42.051436 RX Delay -179 -> 252, step: 8
4953 17:16:42.054619 iDelay=213, Bit 0, Center 48 (-99 ~ 196) 296
4954 17:16:42.057770 iDelay=213, Bit 1, Center 40 (-107 ~ 188) 296
4955 17:16:42.064364 iDelay=213, Bit 2, Center 32 (-115 ~ 180) 296
4956 17:16:42.067860 iDelay=213, Bit 3, Center 40 (-107 ~ 188) 296
4957 17:16:42.071289 iDelay=213, Bit 4, Center 44 (-107 ~ 196) 304
4958 17:16:42.074239 iDelay=213, Bit 5, Center 56 (-91 ~ 204) 296
4959 17:16:42.077663 iDelay=213, Bit 6, Center 60 (-91 ~ 212) 304
4960 17:16:42.080943
4961 17:16:42.084524 iDelay=213, Bit 7, Center 44 (-107 ~ 196) 304
4962 17:16:42.087491 iDelay=213, Bit 8, Center 24 (-131 ~ 180) 312
4963 17:16:42.090770 iDelay=213, Bit 9, Center 24 (-131 ~ 180) 312
4964 17:16:42.094145 iDelay=213, Bit 10, Center 36 (-123 ~ 196) 320
4965 17:16:42.100903 iDelay=213, Bit 11, Center 28 (-123 ~ 180) 304
4966 17:16:42.104242 iDelay=213, Bit 12, Center 48 (-107 ~ 204) 312
4967 17:16:42.107412 iDelay=213, Bit 13, Center 48 (-107 ~ 204) 312
4968 17:16:42.110879 iDelay=213, Bit 14, Center 48 (-107 ~ 204) 312
4969 17:16:42.117265 iDelay=213, Bit 15, Center 48 (-107 ~ 204) 312
4970 17:16:42.117377 ==
4971 17:16:42.120912 Dram Type= 6, Freq= 0, CH_1, rank 1
4972 17:16:42.123829 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4973 17:16:42.123915 ==
4974 17:16:42.123982 DQS Delay:
4975 17:16:42.127206 DQS0 = 0, DQS1 = 0
4976 17:16:42.127290 DQM Delay:
4977 17:16:42.130876 DQM0 = 45, DQM1 = 38
4978 17:16:42.130961 DQ Delay:
4979 17:16:42.133903 DQ0 =48, DQ1 =40, DQ2 =32, DQ3 =40
4980 17:16:42.136873 DQ4 =44, DQ5 =56, DQ6 =60, DQ7 =44
4981 17:16:42.140310 DQ8 =24, DQ9 =24, DQ10 =36, DQ11 =28
4982 17:16:42.143919 DQ12 =48, DQ13 =48, DQ14 =48, DQ15 =48
4983 17:16:42.144007
4984 17:16:42.144075
4985 17:16:42.153538 [DQSOSCAuto] RK1, (LSB)MR18= 0x2b20, (MSB)MR19= 0x808, tDQSOscB0 = 403 ps tDQSOscB1 = 401 ps
4986 17:16:42.153625 CH1 RK1: MR19=808, MR18=2B20
4987 17:16:42.160266 CH1_RK1: MR19=0x808, MR18=0x2B20, DQSOSC=401, MR23=63, INC=163, DEC=108
4988 17:16:42.163615 [RxdqsGatingPostProcess] freq 600
4989 17:16:42.170116 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4990 17:16:42.173213 Pre-setting of DQS Precalculation
4991 17:16:42.176674 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4992 17:16:42.183646 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4993 17:16:42.193121 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4994 17:16:42.193235
4995 17:16:42.193309
4996 17:16:42.196414 [Calibration Summary] 1200 Mbps
4997 17:16:42.196505 CH 0, Rank 0
4998 17:16:42.200057 SW Impedance : PASS
4999 17:16:42.200143 DUTY Scan : NO K
5000 17:16:42.203274 ZQ Calibration : PASS
5001 17:16:42.203359 Jitter Meter : NO K
5002 17:16:42.206895
5003 17:16:42.206981 CBT Training : PASS
5004 17:16:42.209749 Write leveling : PASS
5005 17:16:42.209834 RX DQS gating : PASS
5006 17:16:42.212877 RX DQ/DQS(RDDQC) : PASS
5007 17:16:42.216400 TX DQ/DQS : PASS
5008 17:16:42.216491 RX DATLAT : PASS
5009 17:16:42.219868 RX DQ/DQS(Engine): PASS
5010 17:16:42.222868 TX OE : NO K
5011 17:16:42.222954 All Pass.
5012 17:16:42.223029
5013 17:16:42.223093 CH 0, Rank 1
5014 17:16:42.226147 SW Impedance : PASS
5015 17:16:42.229508 DUTY Scan : NO K
5016 17:16:42.229598 ZQ Calibration : PASS
5017 17:16:42.233058 Jitter Meter : NO K
5018 17:16:42.236450 CBT Training : PASS
5019 17:16:42.236535 Write leveling : PASS
5020 17:16:42.239495 RX DQS gating : PASS
5021 17:16:42.242998 RX DQ/DQS(RDDQC) : PASS
5022 17:16:42.243086 TX DQ/DQS : PASS
5023 17:16:42.245881 RX DATLAT : PASS
5024 17:16:42.249568 RX DQ/DQS(Engine): PASS
5025 17:16:42.249655 TX OE : NO K
5026 17:16:42.252827 All Pass.
5027 17:16:42.252912
5028 17:16:42.252980 CH 1, Rank 0
5029 17:16:42.255936 SW Impedance : PASS
5030 17:16:42.256021 DUTY Scan : NO K
5031 17:16:42.259381 ZQ Calibration : PASS
5032 17:16:42.262958 Jitter Meter : NO K
5033 17:16:42.263043 CBT Training : PASS
5034 17:16:42.265822 Write leveling : PASS
5035 17:16:42.269239 RX DQS gating : PASS
5036 17:16:42.269349 RX DQ/DQS(RDDQC) : PASS
5037 17:16:42.272606 TX DQ/DQS : PASS
5038 17:16:42.272692 RX DATLAT : PASS
5039 17:16:42.275896 RX DQ/DQS(Engine): PASS
5040 17:16:42.279353 TX OE : NO K
5041 17:16:42.279438 All Pass.
5042 17:16:42.279508
5043 17:16:42.279572 CH 1, Rank 1
5044 17:16:42.282922 SW Impedance : PASS
5045 17:16:42.285735 DUTY Scan : NO K
5046 17:16:42.285821 ZQ Calibration : PASS
5047 17:16:42.289161 Jitter Meter : NO K
5048 17:16:42.292584 CBT Training : PASS
5049 17:16:42.292671 Write leveling : PASS
5050 17:16:42.296017 RX DQS gating : PASS
5051 17:16:42.299242 RX DQ/DQS(RDDQC) : PASS
5052 17:16:42.299328 TX DQ/DQS : PASS
5053 17:16:42.302759 RX DATLAT : PASS
5054 17:16:42.305865 RX DQ/DQS(Engine): PASS
5055 17:16:42.305950 TX OE : NO K
5056 17:16:42.308802 All Pass.
5057 17:16:42.308889
5058 17:16:42.308957 DramC Write-DBI off
5059 17:16:42.312517 PER_BANK_REFRESH: Hybrid Mode
5060 17:16:42.312607 TX_TRACKING: ON
5061 17:16:42.322150 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
5062 17:16:42.325613 [FAST_K] Save calibration result to emmc
5063 17:16:42.328903 dramc_set_vcore_voltage set vcore to 662500
5064 17:16:42.332444 Read voltage for 933, 3
5065 17:16:42.332529 Vio18 = 0
5066 17:16:42.335447 Vcore = 662500
5067 17:16:42.335532 Vdram = 0
5068 17:16:42.335599 Vddq = 0
5069 17:16:42.335660 Vmddr = 0
5070 17:16:42.342496 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
5071 17:16:42.348760 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
5072 17:16:42.348846 MEM_TYPE=3, freq_sel=17
5073 17:16:42.352054 sv_algorithm_assistance_LP4_1600
5074 17:16:42.355488 ============ PULL DRAM RESETB DOWN ============
5075 17:16:42.358731
5076 17:16:42.361865 ========== PULL DRAM RESETB DOWN end =========
5077 17:16:42.365285 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5078 17:16:42.368696 ===================================
5079 17:16:42.372082 LPDDR4 DRAM CONFIGURATION
5080 17:16:42.375492 ===================================
5081 17:16:42.375578 EX_ROW_EN[0] = 0x0
5082 17:16:42.378774 EX_ROW_EN[1] = 0x0
5083 17:16:42.378859 LP4Y_EN = 0x0
5084 17:16:42.382098 WORK_FSP = 0x0
5085 17:16:42.382183 WL = 0x3
5086 17:16:42.385613
5087 17:16:42.385698 RL = 0x3
5088 17:16:42.388600 BL = 0x2
5089 17:16:42.388684 RPST = 0x0
5090 17:16:42.391874 RD_PRE = 0x0
5091 17:16:42.391959 WR_PRE = 0x1
5092 17:16:42.395445 WR_PST = 0x0
5093 17:16:42.395530 DBI_WR = 0x0
5094 17:16:42.398764 DBI_RD = 0x0
5095 17:16:42.398849 OTF = 0x1
5096 17:16:42.402183 ===================================
5097 17:16:42.405098 ===================================
5098 17:16:42.408569 ANA top config
5099 17:16:42.411829 ===================================
5100 17:16:42.411915 DLL_ASYNC_EN = 0
5101 17:16:42.415306 ALL_SLAVE_EN = 1
5102 17:16:42.418368 NEW_RANK_MODE = 1
5103 17:16:42.421804 DLL_IDLE_MODE = 1
5104 17:16:42.424936 LP45_APHY_COMB_EN = 1
5105 17:16:42.425021 TX_ODT_DIS = 1
5106 17:16:42.428423 NEW_8X_MODE = 1
5107 17:16:42.431608 ===================================
5108 17:16:42.434809 ===================================
5109 17:16:42.438304 data_rate = 1866
5110 17:16:42.441182 CKR = 1
5111 17:16:42.444707 DQ_P2S_RATIO = 8
5112 17:16:42.447839 ===================================
5113 17:16:42.451223 CA_P2S_RATIO = 8
5114 17:16:42.451308 DQ_CA_OPEN = 0
5115 17:16:42.454892 DQ_SEMI_OPEN = 0
5116 17:16:42.458218 CA_SEMI_OPEN = 0
5117 17:16:42.461246 CA_FULL_RATE = 0
5118 17:16:42.464337 DQ_CKDIV4_EN = 1
5119 17:16:42.467895 CA_CKDIV4_EN = 1
5120 17:16:42.467982 CA_PREDIV_EN = 0
5121 17:16:42.471165 PH8_DLY = 0
5122 17:16:42.474279 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
5123 17:16:42.478150 DQ_AAMCK_DIV = 4
5124 17:16:42.481222 CA_AAMCK_DIV = 4
5125 17:16:42.484176 CA_ADMCK_DIV = 4
5126 17:16:42.484263 DQ_TRACK_CA_EN = 0
5127 17:16:42.487647 CA_PICK = 933
5128 17:16:42.491146 CA_MCKIO = 933
5129 17:16:42.494336 MCKIO_SEMI = 0
5130 17:16:42.497786 PLL_FREQ = 3732
5131 17:16:42.500778 DQ_UI_PI_RATIO = 32
5132 17:16:42.504244 CA_UI_PI_RATIO = 0
5133 17:16:42.507204 ===================================
5134 17:16:42.510630 ===================================
5135 17:16:42.510716 memory_type:LPDDR4
5136 17:16:42.514085 GP_NUM : 10
5137 17:16:42.517634 SRAM_EN : 1
5138 17:16:42.517720 MD32_EN : 0
5139 17:16:42.520654 ===================================
5140 17:16:42.524034 [ANA_INIT] >>>>>>>>>>>>>>
5141 17:16:42.527128 <<<<<< [CONFIGURE PHASE]: ANA_TX
5142 17:16:42.530851 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5143 17:16:42.533823 ===================================
5144 17:16:42.537309 data_rate = 1866,PCW = 0X8f00
5145 17:16:42.540244 ===================================
5146 17:16:42.543924 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5147 17:16:42.546921 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5148 17:16:42.553596 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5149 17:16:42.557013 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5150 17:16:42.560159 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5151 17:16:42.563491 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5152 17:16:42.567178 [ANA_INIT] flow start
5153 17:16:42.570157 [ANA_INIT] PLL >>>>>>>>
5154 17:16:42.570244 [ANA_INIT] PLL <<<<<<<<
5155 17:16:42.573413 [ANA_INIT] MIDPI >>>>>>>>
5156 17:16:42.576885 [ANA_INIT] MIDPI <<<<<<<<
5157 17:16:42.580219 [ANA_INIT] DLL >>>>>>>>
5158 17:16:42.580297 [ANA_INIT] flow end
5159 17:16:42.583607 ============ LP4 DIFF to SE enter ============
5160 17:16:42.590050 ============ LP4 DIFF to SE exit ============
5161 17:16:42.590132 [ANA_INIT] <<<<<<<<<<<<<
5162 17:16:42.593449 [Flow] Enable top DCM control >>>>>
5163 17:16:42.596900 [Flow] Enable top DCM control <<<<<
5164 17:16:42.600310 Enable DLL master slave shuffle
5165 17:16:42.606932 ==============================================================
5166 17:16:42.607021 Gating Mode config
5167 17:16:42.613612 ==============================================================
5168 17:16:42.616368 Config description:
5169 17:16:42.626334 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5170 17:16:42.632841 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5171 17:16:42.636472 SELPH_MODE 0: By rank 1: By Phase
5172 17:16:42.642623 ==============================================================
5173 17:16:42.646120 GAT_TRACK_EN = 1
5174 17:16:42.649558 RX_GATING_MODE = 2
5175 17:16:42.649644 RX_GATING_TRACK_MODE = 2
5176 17:16:42.652596 SELPH_MODE = 1
5177 17:16:42.655967 PICG_EARLY_EN = 1
5178 17:16:42.659556 VALID_LAT_VALUE = 1
5179 17:16:42.666021 ==============================================================
5180 17:16:42.669182 Enter into Gating configuration >>>>
5181 17:16:42.672569 Exit from Gating configuration <<<<
5182 17:16:42.676094 Enter into DVFS_PRE_config >>>>>
5183 17:16:42.685815 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5184 17:16:42.689177 Exit from DVFS_PRE_config <<<<<
5185 17:16:42.692806 Enter into PICG configuration >>>>
5186 17:16:42.695905 Exit from PICG configuration <<<<
5187 17:16:42.699391 [RX_INPUT] configuration >>>>>
5188 17:16:42.702276 [RX_INPUT] configuration <<<<<
5189 17:16:42.705685 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5190 17:16:42.712485 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5191 17:16:42.719397 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5192 17:16:42.725503 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5193 17:16:42.732177 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5194 17:16:42.735593 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5195 17:16:42.742065 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5196 17:16:42.745679 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5197 17:16:42.748720 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5198 17:16:42.751821 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5199 17:16:42.755620 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5200 17:16:42.761894 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5201 17:16:42.765537 ===================================
5202 17:16:42.768662 LPDDR4 DRAM CONFIGURATION
5203 17:16:42.771988 ===================================
5204 17:16:42.772081 EX_ROW_EN[0] = 0x0
5205 17:16:42.775594 EX_ROW_EN[1] = 0x0
5206 17:16:42.775680 LP4Y_EN = 0x0
5207 17:16:42.778875 WORK_FSP = 0x0
5208 17:16:42.778966 WL = 0x3
5209 17:16:42.782034 RL = 0x3
5210 17:16:42.782113 BL = 0x2
5211 17:16:42.784949 RPST = 0x0
5212 17:16:42.785028 RD_PRE = 0x0
5213 17:16:42.788718 WR_PRE = 0x1
5214 17:16:42.788798 WR_PST = 0x0
5215 17:16:42.791595 DBI_WR = 0x0
5216 17:16:42.791676 DBI_RD = 0x0
5217 17:16:42.794805
5218 17:16:42.794888 OTF = 0x1
5219 17:16:42.798679 ===================================
5220 17:16:42.801651 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5221 17:16:42.805048 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5222 17:16:42.811918 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5223 17:16:42.814733 ===================================
5224 17:16:42.818151 LPDDR4 DRAM CONFIGURATION
5225 17:16:42.821449 ===================================
5226 17:16:42.821530 EX_ROW_EN[0] = 0x10
5227 17:16:42.824903 EX_ROW_EN[1] = 0x0
5228 17:16:42.824986 LP4Y_EN = 0x0
5229 17:16:42.827930 WORK_FSP = 0x0
5230 17:16:42.828008 WL = 0x3
5231 17:16:42.831539 RL = 0x3
5232 17:16:42.831618 BL = 0x2
5233 17:16:42.834657 RPST = 0x0
5234 17:16:42.834742 RD_PRE = 0x0
5235 17:16:42.838046 WR_PRE = 0x1
5236 17:16:42.838125 WR_PST = 0x0
5237 17:16:42.841104 DBI_WR = 0x0
5238 17:16:42.844730 DBI_RD = 0x0
5239 17:16:42.844815 OTF = 0x1
5240 17:16:42.848177 ===================================
5241 17:16:42.854103 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5242 17:16:42.858176 nWR fixed to 30
5243 17:16:42.861293 [ModeRegInit_LP4] CH0 RK0
5244 17:16:42.861414 [ModeRegInit_LP4] CH0 RK1
5245 17:16:42.864763 [ModeRegInit_LP4] CH1 RK0
5246 17:16:42.868276 [ModeRegInit_LP4] CH1 RK1
5247 17:16:42.868390 match AC timing 9
5248 17:16:42.874648 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5249 17:16:42.878127 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5250 17:16:42.881234 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5251 17:16:42.888008 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5252 17:16:42.890965 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5253 17:16:42.891056 ==
5254 17:16:42.894172 Dram Type= 6, Freq= 0, CH_0, rank 0
5255 17:16:42.897573 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5256 17:16:42.897659 ==
5257 17:16:42.904069 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5258 17:16:42.910751 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5259 17:16:42.913969 [CA 0] Center 38 (7~69) winsize 63
5260 17:16:42.917341 [CA 1] Center 37 (7~68) winsize 62
5261 17:16:42.920570 [CA 2] Center 34 (4~65) winsize 62
5262 17:16:42.924087 [CA 3] Center 34 (4~65) winsize 62
5263 17:16:42.927169 [CA 4] Center 33 (3~64) winsize 62
5264 17:16:42.930293 [CA 5] Center 33 (3~64) winsize 62
5265 17:16:42.930379
5266 17:16:42.933861 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5267 17:16:42.933946
5268 17:16:42.937127 [CATrainingPosCal] consider 1 rank data
5269 17:16:42.940103 u2DelayCellTimex100 = 270/100 ps
5270 17:16:42.943523 CA0 delay=38 (7~69),Diff = 5 PI (31 cell)
5271 17:16:42.946683 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5272 17:16:42.950114 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5273 17:16:42.956724 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5274 17:16:42.960155 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5275 17:16:42.963498 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5276 17:16:42.963576
5277 17:16:42.966717 CA PerBit enable=1, Macro0, CA PI delay=33
5278 17:16:42.966795
5279 17:16:42.970007 [CBTSetCACLKResult] CA Dly = 33
5280 17:16:42.970090 CS Dly: 7 (0~38)
5281 17:16:42.970156 ==
5282 17:16:42.973088 Dram Type= 6, Freq= 0, CH_0, rank 1
5283 17:16:42.979713 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5284 17:16:42.979799 ==
5285 17:16:42.983169 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5286 17:16:42.990074 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5287 17:16:42.993192 [CA 0] Center 37 (7~68) winsize 62
5288 17:16:42.996274 [CA 1] Center 37 (7~68) winsize 62
5289 17:16:42.999633 [CA 2] Center 34 (4~65) winsize 62
5290 17:16:43.002882 [CA 3] Center 34 (4~65) winsize 62
5291 17:16:43.006479 [CA 4] Center 33 (3~64) winsize 62
5292 17:16:43.009469 [CA 5] Center 33 (3~63) winsize 61
5293 17:16:43.009555
5294 17:16:43.013052 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5295 17:16:43.013138
5296 17:16:43.016424 [CATrainingPosCal] consider 2 rank data
5297 17:16:43.019478 u2DelayCellTimex100 = 270/100 ps
5298 17:16:43.022835 CA0 delay=37 (7~68),Diff = 4 PI (24 cell)
5299 17:16:43.026071 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5300 17:16:43.029586
5301 17:16:43.032576 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5302 17:16:43.036099 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5303 17:16:43.039218 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
5304 17:16:43.042768 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5305 17:16:43.042854
5306 17:16:43.046344 CA PerBit enable=1, Macro0, CA PI delay=33
5307 17:16:43.046430
5308 17:16:43.049430 [CBTSetCACLKResult] CA Dly = 33
5309 17:16:43.049516 CS Dly: 7 (0~39)
5310 17:16:43.052341
5311 17:16:43.052427
5312 17:16:43.055664 ----->DramcWriteLeveling(PI) begin...
5313 17:16:43.055751 ==
5314 17:16:43.058903 Dram Type= 6, Freq= 0, CH_0, rank 0
5315 17:16:43.062350 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5316 17:16:43.062436 ==
5317 17:16:43.065684 Write leveling (Byte 0): 32 => 32
5318 17:16:43.069109 Write leveling (Byte 1): 30 => 30
5319 17:16:43.072431 DramcWriteLeveling(PI) end<-----
5320 17:16:43.072518
5321 17:16:43.072624 ==
5322 17:16:43.075497 Dram Type= 6, Freq= 0, CH_0, rank 0
5323 17:16:43.079004 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5324 17:16:43.079091 ==
5325 17:16:43.082362 [Gating] SW mode calibration
5326 17:16:43.089073 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5327 17:16:43.095326 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5328 17:16:43.098761 0 14 0 | B1->B0 | 2323 3030 | 0 0 | (0 0) (0 0)
5329 17:16:43.101915 0 14 4 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
5330 17:16:43.108491 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5331 17:16:43.111942 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5332 17:16:43.115450 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5333 17:16:43.121709 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5334 17:16:43.125444 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5335 17:16:43.128333 0 14 28 | B1->B0 | 3434 2e2e | 1 0 | (1 1) (0 1)
5336 17:16:43.134812 0 15 0 | B1->B0 | 3030 2323 | 0 0 | (0 1) (1 0)
5337 17:16:43.138370 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5338 17:16:43.141479 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5339 17:16:43.148528 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5340 17:16:43.151696 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5341 17:16:43.155219 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5342 17:16:43.161658 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5343 17:16:43.165171 0 15 28 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
5344 17:16:43.168286 1 0 0 | B1->B0 | 2d2d 4343 | 0 0 | (0 0) (0 0)
5345 17:16:43.175178 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5346 17:16:43.177955 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5347 17:16:43.181213 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5348 17:16:43.187693 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5349 17:16:43.191175 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5350 17:16:43.194176 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5351 17:16:43.200718 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5352 17:16:43.204344 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5353 17:16:43.207383 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5354 17:16:43.213985 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5355 17:16:43.217492 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5356 17:16:43.221090 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5357 17:16:43.227481 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5358 17:16:43.230584 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5359 17:16:43.234050 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5360 17:16:43.240469 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5361 17:16:43.244145 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5362 17:16:43.247255 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5363 17:16:43.254037 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5364 17:16:43.256878 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5365 17:16:43.260581 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5366 17:16:43.267414 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5367 17:16:43.270381 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5368 17:16:43.273977 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5369 17:16:43.280174 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5370 17:16:43.280261 Total UI for P1: 0, mck2ui 16
5371 17:16:43.286740 best dqsien dly found for B0: ( 1, 2, 30)
5372 17:16:43.286819 Total UI for P1: 0, mck2ui 16
5373 17:16:43.293706 best dqsien dly found for B1: ( 1, 3, 2)
5374 17:16:43.296792 best DQS0 dly(MCK, UI, PI) = (1, 2, 30)
5375 17:16:43.300329 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5376 17:16:43.300403
5377 17:16:43.303312 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 30)
5378 17:16:43.306966 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5379 17:16:43.310032 [Gating] SW calibration Done
5380 17:16:43.310105 ==
5381 17:16:43.313649 Dram Type= 6, Freq= 0, CH_0, rank 0
5382 17:16:43.316565 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5383 17:16:43.316637 ==
5384 17:16:43.319900 RX Vref Scan: 0
5385 17:16:43.319972
5386 17:16:43.320034 RX Vref 0 -> 0, step: 1
5387 17:16:43.320092
5388 17:16:43.323349 RX Delay -80 -> 252, step: 8
5389 17:16:43.326344 iDelay=208, Bit 0, Center 99 (0 ~ 199) 200
5390 17:16:43.332923 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5391 17:16:43.336247 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5392 17:16:43.339842 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5393 17:16:43.342858 iDelay=208, Bit 4, Center 99 (0 ~ 199) 200
5394 17:16:43.346036 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5395 17:16:43.349802 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5396 17:16:43.356279 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5397 17:16:43.359347 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5398 17:16:43.363035 iDelay=208, Bit 9, Center 75 (-24 ~ 175) 200
5399 17:16:43.365968 iDelay=208, Bit 10, Center 87 (-8 ~ 183) 192
5400 17:16:43.369697 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5401 17:16:43.376171 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5402 17:16:43.379527 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5403 17:16:43.382492 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5404 17:16:43.386051 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5405 17:16:43.386126 ==
5406 17:16:43.389047 Dram Type= 6, Freq= 0, CH_0, rank 0
5407 17:16:43.392467 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5408 17:16:43.395576 ==
5409 17:16:43.395649 DQS Delay:
5410 17:16:43.395715 DQS0 = 0, DQS1 = 0
5411 17:16:43.399110 DQM Delay:
5412 17:16:43.399193 DQM0 = 98, DQM1 = 86
5413 17:16:43.402213 DQ Delay:
5414 17:16:43.405763 DQ0 =99, DQ1 =99, DQ2 =95, DQ3 =91
5415 17:16:43.405847 DQ4 =99, DQ5 =87, DQ6 =107, DQ7 =107
5416 17:16:43.409080
5417 17:16:43.409164 DQ8 =79, DQ9 =75, DQ10 =87, DQ11 =83
5418 17:16:43.412201
5419 17:16:43.415592 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5420 17:16:43.415675
5421 17:16:43.415740
5422 17:16:43.415800 ==
5423 17:16:43.419015 Dram Type= 6, Freq= 0, CH_0, rank 0
5424 17:16:43.422119 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5425 17:16:43.422203 ==
5426 17:16:43.422272
5427 17:16:43.422334
5428 17:16:43.425679 TX Vref Scan disable
5429 17:16:43.425763 == TX Byte 0 ==
5430 17:16:43.431992 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5431 17:16:43.435623 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5432 17:16:43.435708 == TX Byte 1 ==
5433 17:16:43.442357 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5434 17:16:43.445188 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5435 17:16:43.445271 ==
5436 17:16:43.448738 Dram Type= 6, Freq= 0, CH_0, rank 0
5437 17:16:43.451707 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5438 17:16:43.451791 ==
5439 17:16:43.451855
5440 17:16:43.451917
5441 17:16:43.455379
5442 17:16:43.455462 TX Vref Scan disable
5443 17:16:43.458558 == TX Byte 0 ==
5444 17:16:43.462115 Update DQ dly =714 (2 ,6, 10) DQ OEN =(2 ,3)
5445 17:16:43.465162 Update DQM dly =714 (2 ,6, 10) DQM OEN =(2 ,3)
5446 17:16:43.468651 == TX Byte 1 ==
5447 17:16:43.471692 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5448 17:16:43.475067 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5449 17:16:43.478047
5450 17:16:43.478130
5451 17:16:43.478195 [DATLAT]
5452 17:16:43.478261 Freq=933, CH0 RK0
5453 17:16:43.478326
5454 17:16:43.481580 DATLAT Default: 0xd
5455 17:16:43.481663 0, 0xFFFF, sum = 0
5456 17:16:43.484865 1, 0xFFFF, sum = 0
5457 17:16:43.484953 2, 0xFFFF, sum = 0
5458 17:16:43.488053
5459 17:16:43.488136 3, 0xFFFF, sum = 0
5460 17:16:43.491766 4, 0xFFFF, sum = 0
5461 17:16:43.491842 5, 0xFFFF, sum = 0
5462 17:16:43.494764 6, 0xFFFF, sum = 0
5463 17:16:43.494842 7, 0xFFFF, sum = 0
5464 17:16:43.498060 8, 0xFFFF, sum = 0
5465 17:16:43.498139 9, 0xFFFF, sum = 0
5466 17:16:43.501185 10, 0x0, sum = 1
5467 17:16:43.501259 11, 0x0, sum = 2
5468 17:16:43.504684 12, 0x0, sum = 3
5469 17:16:43.504768 13, 0x0, sum = 4
5470 17:16:43.504833 best_step = 11
5471 17:16:43.504894
5472 17:16:43.507633
5473 17:16:43.507727 ==
5474 17:16:43.510998 Dram Type= 6, Freq= 0, CH_0, rank 0
5475 17:16:43.514620 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5476 17:16:43.514704 ==
5477 17:16:43.514769 RX Vref Scan: 1
5478 17:16:43.514830
5479 17:16:43.517750 RX Vref 0 -> 0, step: 1
5480 17:16:43.517838
5481 17:16:43.521216 RX Delay -69 -> 252, step: 4
5482 17:16:43.521298
5483 17:16:43.524140 Set Vref, RX VrefLevel [Byte0]: 57
5484 17:16:43.527649 [Byte1]: 47
5485 17:16:43.530798
5486 17:16:43.530881 Final RX Vref Byte 0 = 57 to rank0
5487 17:16:43.534001 Final RX Vref Byte 1 = 47 to rank0
5488 17:16:43.537266 Final RX Vref Byte 0 = 57 to rank1
5489 17:16:43.540757 Final RX Vref Byte 1 = 47 to rank1==
5490 17:16:43.544427 Dram Type= 6, Freq= 0, CH_0, rank 0
5491 17:16:43.550517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5492 17:16:43.550601 ==
5493 17:16:43.550666 DQS Delay:
5494 17:16:43.553752 DQS0 = 0, DQS1 = 0
5495 17:16:43.553835 DQM Delay:
5496 17:16:43.553901 DQM0 = 97, DQM1 = 85
5497 17:16:43.557164 DQ Delay:
5498 17:16:43.560836 DQ0 =96, DQ1 =98, DQ2 =94, DQ3 =92
5499 17:16:43.563942 DQ4 =98, DQ5 =88, DQ6 =104, DQ7 =108
5500 17:16:43.566995 DQ8 =76, DQ9 =74, DQ10 =86, DQ11 =78
5501 17:16:43.570652 DQ12 =90, DQ13 =88, DQ14 =96, DQ15 =94
5502 17:16:43.570740
5503 17:16:43.570807
5504 17:16:43.576752 [DQSOSCAuto] RK0, (LSB)MR18= 0x2c13, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 408 ps
5505 17:16:43.580283 CH0 RK0: MR19=505, MR18=2C13
5506 17:16:43.587187 CH0_RK0: MR19=0x505, MR18=0x2C13, DQSOSC=408, MR23=63, INC=65, DEC=43
5507 17:16:43.587270
5508 17:16:43.590221 ----->DramcWriteLeveling(PI) begin...
5509 17:16:43.590309 ==
5510 17:16:43.593733 Dram Type= 6, Freq= 0, CH_0, rank 1
5511 17:16:43.596757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5512 17:16:43.596841 ==
5513 17:16:43.600099 Write leveling (Byte 0): 33 => 33
5514 17:16:43.603235 Write leveling (Byte 1): 31 => 31
5515 17:16:43.606585 DramcWriteLeveling(PI) end<-----
5516 17:16:43.606669
5517 17:16:43.606734 ==
5518 17:16:43.610191 Dram Type= 6, Freq= 0, CH_0, rank 1
5519 17:16:43.613534 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5520 17:16:43.616743 ==
5521 17:16:43.616825 [Gating] SW mode calibration
5522 17:16:43.626617 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5523 17:16:43.629949 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5524 17:16:43.632965 0 14 0 | B1->B0 | 2a2a 3434 | 1 1 | (0 0) (1 1)
5525 17:16:43.639659 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5526 17:16:43.643151 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5527 17:16:43.646185 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5528 17:16:43.653034 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5529 17:16:43.656032 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5530 17:16:43.659542 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5531 17:16:43.665754 0 14 28 | B1->B0 | 3434 2e2e | 0 0 | (0 0) (0 1)
5532 17:16:43.669239 0 15 0 | B1->B0 | 2f2f 2929 | 0 0 | (1 0) (0 0)
5533 17:16:43.672975 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5534 17:16:43.679040 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5535 17:16:43.682535 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5536 17:16:43.685496 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5537 17:16:43.692248 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5538 17:16:43.695586 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5539 17:16:43.698953 0 15 28 | B1->B0 | 2727 3131 | 0 0 | (0 0) (1 1)
5540 17:16:43.705458 1 0 0 | B1->B0 | 3c3c 4040 | 0 0 | (1 1) (1 1)
5541 17:16:43.709031 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5542 17:16:43.711981 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5543 17:16:43.718973 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5544 17:16:43.721965 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5545 17:16:43.725155 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5546 17:16:43.731787 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5547 17:16:43.735213 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5548 17:16:43.738374 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5549 17:16:43.745353 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5550 17:16:43.748454 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5551 17:16:43.751789 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5552 17:16:43.758377 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5553 17:16:43.761856 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5554 17:16:43.764908 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5555 17:16:43.771579 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5556 17:16:43.774674 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5557 17:16:43.777940 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5558 17:16:43.784549 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5559 17:16:43.787698 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5560 17:16:43.791216 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5561 17:16:43.797677 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5562 17:16:43.801030 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5563 17:16:43.804479 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5564 17:16:43.811095 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5565 17:16:43.814202 Total UI for P1: 0, mck2ui 16
5566 17:16:43.817660 best dqsien dly found for B0: ( 1, 2, 28)
5567 17:16:43.821136 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5568 17:16:43.824560 Total UI for P1: 0, mck2ui 16
5569 17:16:43.827458 best dqsien dly found for B1: ( 1, 3, 0)
5570 17:16:43.830950 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5571 17:16:43.834149 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5572 17:16:43.834225
5573 17:16:43.837430 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5574 17:16:43.840874 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5575 17:16:43.844135 [Gating] SW calibration Done
5576 17:16:43.844211 ==
5577 17:16:43.847669 Dram Type= 6, Freq= 0, CH_0, rank 1
5578 17:16:43.850765 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5579 17:16:43.854276
5580 17:16:43.854350 ==
5581 17:16:43.854413 RX Vref Scan: 0
5582 17:16:43.854478
5583 17:16:43.857305 RX Vref 0 -> 0, step: 1
5584 17:16:43.857384
5585 17:16:43.860833 RX Delay -80 -> 252, step: 8
5586 17:16:43.864075 iDelay=208, Bit 0, Center 95 (0 ~ 191) 192
5587 17:16:43.867102 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5588 17:16:43.870591 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5589 17:16:43.874078 iDelay=208, Bit 3, Center 91 (-8 ~ 191) 200
5590 17:16:43.877002 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5591 17:16:43.883689 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5592 17:16:43.887185 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5593 17:16:43.890238 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5594 17:16:43.893806 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
5595 17:16:43.897356 iDelay=208, Bit 9, Center 71 (-24 ~ 167) 192
5596 17:16:43.903573 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5597 17:16:43.907117 iDelay=208, Bit 11, Center 79 (-16 ~ 175) 192
5598 17:16:43.910118 iDelay=208, Bit 12, Center 91 (-8 ~ 191) 200
5599 17:16:43.913243 iDelay=208, Bit 13, Center 91 (-8 ~ 191) 200
5600 17:16:43.916753 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5601 17:16:43.923211 iDelay=208, Bit 15, Center 91 (-8 ~ 191) 200
5602 17:16:43.923295 ==
5603 17:16:43.926777 Dram Type= 6, Freq= 0, CH_0, rank 1
5604 17:16:43.929726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5605 17:16:43.929810 ==
5606 17:16:43.929876 DQS Delay:
5607 17:16:43.933073 DQS0 = 0, DQS1 = 0
5608 17:16:43.933157 DQM Delay:
5609 17:16:43.936501 DQM0 = 96, DQM1 = 86
5610 17:16:43.936587 DQ Delay:
5611 17:16:43.939619 DQ0 =95, DQ1 =99, DQ2 =91, DQ3 =91
5612 17:16:43.942841 DQ4 =95, DQ5 =87, DQ6 =107, DQ7 =107
5613 17:16:43.946519 DQ8 =79, DQ9 =71, DQ10 =91, DQ11 =79
5614 17:16:43.949780 DQ12 =91, DQ13 =91, DQ14 =95, DQ15 =91
5615 17:16:43.949866
5616 17:16:43.949934
5617 17:16:43.949996 ==
5618 17:16:43.953120 Dram Type= 6, Freq= 0, CH_0, rank 1
5619 17:16:43.956348 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5620 17:16:43.959315 ==
5621 17:16:43.959401
5622 17:16:43.959468
5623 17:16:43.959532 TX Vref Scan disable
5624 17:16:43.962809 == TX Byte 0 ==
5625 17:16:43.966439 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5626 17:16:43.969440 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5627 17:16:43.973143 == TX Byte 1 ==
5628 17:16:43.976010 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5629 17:16:43.979655 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5630 17:16:43.982795 ==
5631 17:16:43.986289 Dram Type= 6, Freq= 0, CH_0, rank 1
5632 17:16:43.989153 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5633 17:16:43.989240 ==
5634 17:16:43.989308
5635 17:16:43.989411
5636 17:16:43.992777 TX Vref Scan disable
5637 17:16:43.992863 == TX Byte 0 ==
5638 17:16:43.999444 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5639 17:16:44.002815 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5640 17:16:44.002902 == TX Byte 1 ==
5641 17:16:44.008975 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5642 17:16:44.012145 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5643 17:16:44.012232
5644 17:16:44.012300 [DATLAT]
5645 17:16:44.015954 Freq=933, CH0 RK1
5646 17:16:44.016041
5647 17:16:44.016109 DATLAT Default: 0xb
5648 17:16:44.019272 0, 0xFFFF, sum = 0
5649 17:16:44.019365 1, 0xFFFF, sum = 0
5650 17:16:44.022287 2, 0xFFFF, sum = 0
5651 17:16:44.022374 3, 0xFFFF, sum = 0
5652 17:16:44.025838 4, 0xFFFF, sum = 0
5653 17:16:44.026185 5, 0xFFFF, sum = 0
5654 17:16:44.029628 6, 0xFFFF, sum = 0
5655 17:16:44.029975 7, 0xFFFF, sum = 0
5656 17:16:44.032445
5657 17:16:44.032789 8, 0xFFFF, sum = 0
5658 17:16:44.035892 9, 0xFFFF, sum = 0
5659 17:16:44.036239 10, 0x0, sum = 1
5660 17:16:44.036520 11, 0x0, sum = 2
5661 17:16:44.039378 12, 0x0, sum = 3
5662 17:16:44.039723 13, 0x0, sum = 4
5663 17:16:44.042930 best_step = 11
5664 17:16:44.043273
5665 17:16:44.043541 ==
5666 17:16:44.046118 Dram Type= 6, Freq= 0, CH_0, rank 1
5667 17:16:44.049371 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5668 17:16:44.049756 ==
5669 17:16:44.052622 RX Vref Scan: 0
5670 17:16:44.052964
5671 17:16:44.053234 RX Vref 0 -> 0, step: 1
5672 17:16:44.055867
5673 17:16:44.056207 RX Delay -69 -> 252, step: 4
5674 17:16:44.063681 iDelay=203, Bit 0, Center 92 (-1 ~ 186) 188
5675 17:16:44.066436 iDelay=203, Bit 1, Center 96 (-1 ~ 194) 196
5676 17:16:44.070222 iDelay=203, Bit 2, Center 90 (-1 ~ 182) 184
5677 17:16:44.073209 iDelay=203, Bit 3, Center 94 (-1 ~ 190) 192
5678 17:16:44.076946 iDelay=203, Bit 4, Center 94 (-1 ~ 190) 192
5679 17:16:44.082920 iDelay=203, Bit 5, Center 88 (-5 ~ 182) 188
5680 17:16:44.086471 iDelay=203, Bit 6, Center 106 (11 ~ 202) 192
5681 17:16:44.089656 iDelay=203, Bit 7, Center 104 (11 ~ 198) 188
5682 17:16:44.093043 iDelay=203, Bit 8, Center 76 (-17 ~ 170) 188
5683 17:16:44.096412 iDelay=203, Bit 9, Center 72 (-21 ~ 166) 188
5684 17:16:44.103015 iDelay=203, Bit 10, Center 88 (-5 ~ 182) 188
5685 17:16:44.106569 iDelay=203, Bit 11, Center 80 (-9 ~ 170) 180
5686 17:16:44.109560 iDelay=203, Bit 12, Center 92 (-1 ~ 186) 188
5687 17:16:44.112868 iDelay=203, Bit 13, Center 92 (-1 ~ 186) 188
5688 17:16:44.116279 iDelay=203, Bit 14, Center 96 (7 ~ 186) 180
5689 17:16:44.123100 iDelay=203, Bit 15, Center 92 (-1 ~ 186) 188
5690 17:16:44.123511 ==
5691 17:16:44.126160 Dram Type= 6, Freq= 0, CH_0, rank 1
5692 17:16:44.129692 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5693 17:16:44.130102 ==
5694 17:16:44.130424 DQS Delay:
5695 17:16:44.132738 DQS0 = 0, DQS1 = 0
5696 17:16:44.133115 DQM Delay:
5697 17:16:44.136229 DQM0 = 95, DQM1 = 86
5698 17:16:44.136636 DQ Delay:
5699 17:16:44.139408 DQ0 =92, DQ1 =96, DQ2 =90, DQ3 =94
5700 17:16:44.142745 DQ4 =94, DQ5 =88, DQ6 =106, DQ7 =104
5701 17:16:44.146436 DQ8 =76, DQ9 =72, DQ10 =88, DQ11 =80
5702 17:16:44.149522 DQ12 =92, DQ13 =92, DQ14 =96, DQ15 =92
5703 17:16:44.149930
5704 17:16:44.150253
5705 17:16:44.155951 [DQSOSCAuto] RK1, (LSB)MR18= 0x26f6, (MSB)MR19= 0x504, tDQSOscB0 = 425 ps tDQSOscB1 = 409 ps
5706 17:16:44.159126 CH0 RK1: MR19=504, MR18=26F6
5707 17:16:44.165806 CH0_RK1: MR19=0x504, MR18=0x26F6, DQSOSC=409, MR23=63, INC=64, DEC=43
5708 17:16:44.169180 [RxdqsGatingPostProcess] freq 933
5709 17:16:44.175955 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5710 17:16:44.179019 best DQS0 dly(2T, 0.5T) = (0, 10)
5711 17:16:44.182564 best DQS1 dly(2T, 0.5T) = (0, 11)
5712 17:16:44.182977 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5713 17:16:44.185720
5714 17:16:44.186098 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5715 17:16:44.189293
5716 17:16:44.189734 best DQS0 dly(2T, 0.5T) = (0, 10)
5717 17:16:44.192363 best DQS1 dly(2T, 0.5T) = (0, 11)
5718 17:16:44.195339 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5719 17:16:44.198974 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5720 17:16:44.202022 Pre-setting of DQS Precalculation
5721 17:16:44.208694 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5722 17:16:44.209107 ==
5723 17:16:44.212122 Dram Type= 6, Freq= 0, CH_1, rank 0
5724 17:16:44.215606 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5725 17:16:44.216016 ==
5726 17:16:44.222301 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5727 17:16:44.228400 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
5728 17:16:44.231470 [CA 0] Center 37 (7~67) winsize 61
5729 17:16:44.234909 [CA 1] Center 37 (7~68) winsize 62
5730 17:16:44.238359 [CA 2] Center 34 (4~65) winsize 62
5731 17:16:44.241859 [CA 3] Center 34 (4~65) winsize 62
5732 17:16:44.244840 [CA 4] Center 34 (4~65) winsize 62
5733 17:16:44.248650 [CA 5] Center 33 (3~64) winsize 62
5734 17:16:44.249028
5735 17:16:44.251602 [CmdBusTrainingLP45] Vref(ca) range 1: 33
5736 17:16:44.251979
5737 17:16:44.254582 [CATrainingPosCal] consider 1 rank data
5738 17:16:44.258079 u2DelayCellTimex100 = 270/100 ps
5739 17:16:44.261025 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5740 17:16:44.264597 CA1 delay=37 (7~68),Diff = 4 PI (24 cell)
5741 17:16:44.268017 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5742 17:16:44.271184 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5743 17:16:44.274666 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5744 17:16:44.277730 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5745 17:16:44.278113
5746 17:16:44.284498 CA PerBit enable=1, Macro0, CA PI delay=33
5747 17:16:44.284888
5748 17:16:44.287592 [CBTSetCACLKResult] CA Dly = 33
5749 17:16:44.287972 CS Dly: 6 (0~37)
5750 17:16:44.288297 ==
5751 17:16:44.291072 Dram Type= 6, Freq= 0, CH_1, rank 1
5752 17:16:44.294582 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5753 17:16:44.294980 ==
5754 17:16:44.301073 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5755 17:16:44.307477 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5756 17:16:44.310559 [CA 0] Center 37 (7~67) winsize 61
5757 17:16:44.313895 [CA 1] Center 37 (7~67) winsize 61
5758 17:16:44.317438 [CA 2] Center 34 (4~65) winsize 62
5759 17:16:44.320909 [CA 3] Center 34 (4~65) winsize 62
5760 17:16:44.323930 [CA 4] Center 34 (4~65) winsize 62
5761 17:16:44.327292 [CA 5] Center 33 (3~64) winsize 62
5762 17:16:44.327425
5763 17:16:44.330626 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5764 17:16:44.330756
5765 17:16:44.333678 [CATrainingPosCal] consider 2 rank data
5766 17:16:44.337245 u2DelayCellTimex100 = 270/100 ps
5767 17:16:44.340639 CA0 delay=37 (7~67),Diff = 4 PI (24 cell)
5768 17:16:44.343930 CA1 delay=37 (7~67),Diff = 4 PI (24 cell)
5769 17:16:44.346867 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5770 17:16:44.350479 CA3 delay=34 (4~65),Diff = 1 PI (6 cell)
5771 17:16:44.353994 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5772 17:16:44.360545 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
5773 17:16:44.360636
5774 17:16:44.363488 CA PerBit enable=1, Macro0, CA PI delay=33
5775 17:16:44.363576
5776 17:16:44.366792 [CBTSetCACLKResult] CA Dly = 33
5777 17:16:44.366881 CS Dly: 7 (0~39)
5778 17:16:44.366949
5779 17:16:44.370199 ----->DramcWriteLeveling(PI) begin...
5780 17:16:44.370292 ==
5781 17:16:44.373326 Dram Type= 6, Freq= 0, CH_1, rank 0
5782 17:16:44.380250 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5783 17:16:44.380375 ==
5784 17:16:44.383461 Write leveling (Byte 0): 25 => 25
5785 17:16:44.383557 Write leveling (Byte 1): 25 => 25
5786 17:16:44.386490 DramcWriteLeveling(PI) end<-----
5787 17:16:44.386581
5788 17:16:44.389884 ==
5789 17:16:44.389976 Dram Type= 6, Freq= 0, CH_1, rank 0
5790 17:16:44.393230
5791 17:16:44.396786 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5792 17:16:44.396881 ==
5793 17:16:44.399800 [Gating] SW mode calibration
5794 17:16:44.406655 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5795 17:16:44.409834 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5796 17:16:44.416328 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5797 17:16:44.419940 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5798 17:16:44.423224 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5799 17:16:44.429871 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5800 17:16:44.433130 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5801 17:16:44.436677 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5802 17:16:44.443199 0 14 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
5803 17:16:44.446181 0 14 28 | B1->B0 | 2d2d 2e2e | 0 0 | (0 0) (0 0)
5804 17:16:44.449484 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5805 17:16:44.456693 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5806 17:16:44.459330 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5807 17:16:44.463047 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5808 17:16:44.469522 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5809 17:16:44.472661 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5810 17:16:44.476286 0 15 24 | B1->B0 | 2525 2929 | 0 1 | (0 0) (0 0)
5811 17:16:44.483110 0 15 28 | B1->B0 | 3636 3939 | 0 0 | (0 0) (0 0)
5812 17:16:44.486019 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5813 17:16:44.489599 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5814 17:16:44.495898 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5815 17:16:44.499495 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5816 17:16:44.502832 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5817 17:16:44.509021 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5818 17:16:44.512428 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5819 17:16:44.516277 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5820 17:16:44.522346 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5821 17:16:44.525609 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5822 17:16:44.529011 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5823 17:16:44.535597 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5824 17:16:44.539157 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5825 17:16:44.542155 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5826 17:16:44.548840 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5827 17:16:44.552251 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5828 17:16:44.555326 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5829 17:16:44.562168 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5830 17:16:44.565586 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5831 17:16:44.568758 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5832 17:16:44.575224 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5833 17:16:44.578905 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5834 17:16:44.581899 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5835 17:16:44.588674 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5836 17:16:44.589203 Total UI for P1: 0, mck2ui 16
5837 17:16:44.592300 best dqsien dly found for B0: ( 1, 2, 24)
5838 17:16:44.595352 Total UI for P1: 0, mck2ui 16
5839 17:16:44.598322 best dqsien dly found for B1: ( 1, 2, 26)
5840 17:16:44.605090 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5841 17:16:44.608555 best DQS1 dly(MCK, UI, PI) = (1, 2, 26)
5842 17:16:44.608995
5843 17:16:44.611773 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5844 17:16:44.614925 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 26)
5845 17:16:44.618307 [Gating] SW calibration Done
5846 17:16:44.618747 ==
5847 17:16:44.621601 Dram Type= 6, Freq= 0, CH_1, rank 0
5848 17:16:44.624746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 17:16:44.625187 ==
5850 17:16:44.628006 RX Vref Scan: 0
5851 17:16:44.628407
5852 17:16:44.628729 RX Vref 0 -> 0, step: 1
5853 17:16:44.629027
5854 17:16:44.631198 RX Delay -80 -> 252, step: 8
5855 17:16:44.634645 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5856 17:16:44.641493 iDelay=208, Bit 1, Center 99 (8 ~ 191) 184
5857 17:16:44.644418 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5858 17:16:44.648315 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
5859 17:16:44.651592 iDelay=208, Bit 4, Center 99 (8 ~ 191) 184
5860 17:16:44.654563 iDelay=208, Bit 5, Center 111 (16 ~ 207) 192
5861 17:16:44.657906 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5862 17:16:44.664540 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5863 17:16:44.667735 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5864 17:16:44.671309 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5865 17:16:44.674156 iDelay=208, Bit 10, Center 91 (-8 ~ 191) 200
5866 17:16:44.677895 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5867 17:16:44.680984 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5868 17:16:44.684362
5869 17:16:44.687538 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5870 17:16:44.690516 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
5871 17:16:44.693987 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5872 17:16:44.694391 ==
5873 17:16:44.697534 Dram Type= 6, Freq= 0, CH_1, rank 0
5874 17:16:44.700592 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5875 17:16:44.703945 ==
5876 17:16:44.704347 DQS Delay:
5877 17:16:44.704705 DQS0 = 0, DQS1 = 0
5878 17:16:44.707365 DQM Delay:
5879 17:16:44.707889 DQM0 = 102, DQM1 = 94
5880 17:16:44.710976 DQ Delay:
5881 17:16:44.714244 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =99
5882 17:16:44.717004 DQ4 =99, DQ5 =111, DQ6 =111, DQ7 =99
5883 17:16:44.720208 DQ8 =83, DQ9 =87, DQ10 =91, DQ11 =83
5884 17:16:44.723752 DQ12 =103, DQ13 =103, DQ14 =99, DQ15 =103
5885 17:16:44.724156
5886 17:16:44.724476
5887 17:16:44.724774 ==
5888 17:16:44.727324 Dram Type= 6, Freq= 0, CH_1, rank 0
5889 17:16:44.730253 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5890 17:16:44.730657 ==
5891 17:16:44.730975
5892 17:16:44.731270
5893 17:16:44.733789 TX Vref Scan disable
5894 17:16:44.734204 == TX Byte 0 ==
5895 17:16:44.740427 Update DQ dly =709 (2 ,5, 37) DQ OEN =(2 ,2)
5896 17:16:44.743741 Update DQM dly =709 (2 ,5, 37) DQM OEN =(2 ,2)
5897 17:16:44.744144 == TX Byte 1 ==
5898 17:16:44.746831
5899 17:16:44.750488 Update DQ dly =707 (2 ,5, 35) DQ OEN =(2 ,2)
5900 17:16:44.753303 Update DQM dly =707 (2 ,5, 35) DQM OEN =(2 ,2)
5901 17:16:44.753750 ==
5902 17:16:44.757014 Dram Type= 6, Freq= 0, CH_1, rank 0
5903 17:16:44.760052 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5904 17:16:44.760480 ==
5905 17:16:44.763493
5906 17:16:44.763898
5907 17:16:44.764213
5908 17:16:44.764508 TX Vref Scan disable
5909 17:16:44.766959 == TX Byte 0 ==
5910 17:16:44.769998 Update DQ dly =708 (2 ,5, 36) DQ OEN =(2 ,2)
5911 17:16:44.773447 Update DQM dly =708 (2 ,5, 36) DQM OEN =(2 ,2)
5912 17:16:44.776694
5913 17:16:44.777138 == TX Byte 1 ==
5914 17:16:44.780156 Update DQ dly =706 (2 ,5, 34) DQ OEN =(2 ,2)
5915 17:16:44.786861 Update DQM dly =706 (2 ,5, 34) DQM OEN =(2 ,2)
5916 17:16:44.787270
5917 17:16:44.787593 [DATLAT]
5918 17:16:44.787891 Freq=933, CH1 RK0
5919 17:16:44.788210
5920 17:16:44.789971 DATLAT Default: 0xd
5921 17:16:44.790414 0, 0xFFFF, sum = 0
5922 17:16:44.792977 1, 0xFFFF, sum = 0
5923 17:16:44.793435 2, 0xFFFF, sum = 0
5924 17:16:44.796547
5925 17:16:44.796953 3, 0xFFFF, sum = 0
5926 17:16:44.800027 4, 0xFFFF, sum = 0
5927 17:16:44.800441 5, 0xFFFF, sum = 0
5928 17:16:44.803444 6, 0xFFFF, sum = 0
5929 17:16:44.803857 7, 0xFFFF, sum = 0
5930 17:16:44.806396 8, 0xFFFF, sum = 0
5931 17:16:44.806811 9, 0xFFFF, sum = 0
5932 17:16:44.809863 10, 0x0, sum = 1
5933 17:16:44.810276 11, 0x0, sum = 2
5934 17:16:44.813256 12, 0x0, sum = 3
5935 17:16:44.813681 13, 0x0, sum = 4
5936 17:16:44.814008 best_step = 11
5937 17:16:44.814305
5938 17:16:44.816414 ==
5939 17:16:44.819895 Dram Type= 6, Freq= 0, CH_1, rank 0
5940 17:16:44.823029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5941 17:16:44.823438 ==
5942 17:16:44.823760 RX Vref Scan: 1
5943 17:16:44.824063
5944 17:16:44.826279 RX Vref 0 -> 0, step: 1
5945 17:16:44.826686
5946 17:16:44.829301 RX Delay -53 -> 252, step: 4
5947 17:16:44.829732
5948 17:16:44.832874 Set Vref, RX VrefLevel [Byte0]: 47
5949 17:16:44.836063 [Byte1]: 60
5950 17:16:44.836471
5951 17:16:44.839363
5952 17:16:44.839768 Final RX Vref Byte 0 = 47 to rank0
5953 17:16:44.843326 Final RX Vref Byte 1 = 60 to rank0
5954 17:16:44.846085 Final RX Vref Byte 0 = 47 to rank1
5955 17:16:44.848913 Final RX Vref Byte 1 = 60 to rank1==
5956 17:16:44.852487 Dram Type= 6, Freq= 0, CH_1, rank 0
5957 17:16:44.858961 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5958 17:16:44.859372 ==
5959 17:16:44.859692 DQS Delay:
5960 17:16:44.862500 DQS0 = 0, DQS1 = 0
5961 17:16:44.862907 DQM Delay:
5962 17:16:44.863231 DQM0 = 101, DQM1 = 96
5963 17:16:44.865360 DQ Delay:
5964 17:16:44.869021 DQ0 =106, DQ1 =96, DQ2 =94, DQ3 =98
5965 17:16:44.872498 DQ4 =100, DQ5 =112, DQ6 =110, DQ7 =98
5966 17:16:44.875710 DQ8 =84, DQ9 =88, DQ10 =98, DQ11 =84
5967 17:16:44.878963 DQ12 =104, DQ13 =104, DQ14 =104, DQ15 =104
5968 17:16:44.879370
5969 17:16:44.879692
5970 17:16:44.885299 [DQSOSCAuto] RK0, (LSB)MR18= 0x1909, (MSB)MR19= 0x505, tDQSOscB0 = 419 ps tDQSOscB1 = 413 ps
5971 17:16:44.888949 CH1 RK0: MR19=505, MR18=1909
5972 17:16:44.895036 CH1_RK0: MR19=0x505, MR18=0x1909, DQSOSC=413, MR23=63, INC=63, DEC=42
5973 17:16:44.895526
5974 17:16:44.898403 ----->DramcWriteLeveling(PI) begin...
5975 17:16:44.898818 ==
5976 17:16:44.901989 Dram Type= 6, Freq= 0, CH_1, rank 1
5977 17:16:44.904868 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5978 17:16:44.908261 ==
5979 17:16:44.908668 Write leveling (Byte 0): 29 => 29
5980 17:16:44.911678 Write leveling (Byte 1): 30 => 30
5981 17:16:44.915050 DramcWriteLeveling(PI) end<-----
5982 17:16:44.915458
5983 17:16:44.915780 ==
5984 17:16:44.918471 Dram Type= 6, Freq= 0, CH_1, rank 1
5985 17:16:44.925094 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5986 17:16:44.925543 ==
5987 17:16:44.928690 [Gating] SW mode calibration
5988 17:16:44.935002 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5989 17:16:44.937959 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5990 17:16:44.945004 0 14 0 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
5991 17:16:44.947928 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5992 17:16:44.951398 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5993 17:16:44.958271 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5994 17:16:44.961013 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5995 17:16:44.964559 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5996 17:16:44.971505 0 14 24 | B1->B0 | 3333 3434 | 1 1 | (1 0) (1 0)
5997 17:16:44.974561 0 14 28 | B1->B0 | 2a2a 2f2f | 0 1 | (1 0) (1 0)
5998 17:16:44.977932 0 15 0 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5999 17:16:44.984676 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6000 17:16:44.987775 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6001 17:16:44.991196 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6002 17:16:44.997975 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6003 17:16:45.001096 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6004 17:16:45.004266 0 15 24 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
6005 17:16:45.010808 0 15 28 | B1->B0 | 3d3d 3130 | 0 1 | (1 1) (0 0)
6006 17:16:45.014342 1 0 0 | B1->B0 | 4646 3f3f | 0 1 | (0 0) (0 0)
6007 17:16:45.017629 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6008 17:16:45.024117 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6009 17:16:45.027155 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6010 17:16:45.030565 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6011 17:16:45.037050 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6012 17:16:45.040352 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6013 17:16:45.043892 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
6014 17:16:45.050435 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6015 17:16:45.054089 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6016 17:16:45.057082 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6017 17:16:45.060508 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6018 17:16:45.063881
6019 17:16:45.067393 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6020 17:16:45.070406 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6021 17:16:45.073551 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6022 17:16:45.080437 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6023 17:16:45.083834 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6024 17:16:45.087235 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6025 17:16:45.093788 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6026 17:16:45.096785 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6027 17:16:45.100474 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6028 17:16:45.107037 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6029 17:16:45.110091 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 1)
6030 17:16:45.113400 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6031 17:16:45.117050 Total UI for P1: 0, mck2ui 16
6032 17:16:45.120081 best dqsien dly found for B0: ( 1, 2, 26)
6033 17:16:45.123388 Total UI for P1: 0, mck2ui 16
6034 17:16:45.126486 best dqsien dly found for B1: ( 1, 2, 24)
6035 17:16:45.129791 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
6036 17:16:45.133220 best DQS1 dly(MCK, UI, PI) = (1, 2, 24)
6037 17:16:45.133694
6038 17:16:45.136664
6039 17:16:45.140220 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
6040 17:16:45.143293 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 24)
6041 17:16:45.146494 [Gating] SW calibration Done
6042 17:16:45.146933 ==
6043 17:16:45.149784 Dram Type= 6, Freq= 0, CH_1, rank 1
6044 17:16:45.153139 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6045 17:16:45.153616 ==
6046 17:16:45.153965 RX Vref Scan: 0
6047 17:16:45.154291
6048 17:16:45.156716
6049 17:16:45.157151 RX Vref 0 -> 0, step: 1
6050 17:16:45.157544
6051 17:16:45.159661 RX Delay -80 -> 252, step: 8
6052 17:16:45.162955 iDelay=208, Bit 0, Center 107 (16 ~ 199) 184
6053 17:16:45.166613 iDelay=208, Bit 1, Center 95 (8 ~ 183) 176
6054 17:16:45.172915 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
6055 17:16:45.176070 iDelay=208, Bit 3, Center 99 (8 ~ 191) 184
6056 17:16:45.179868 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
6057 17:16:45.182818 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
6058 17:16:45.186331 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
6059 17:16:45.189368 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
6060 17:16:45.196082 iDelay=208, Bit 8, Center 79 (-16 ~ 175) 192
6061 17:16:45.199240 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
6062 17:16:45.202788 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
6063 17:16:45.206322 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
6064 17:16:45.209405 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
6065 17:16:45.212658 iDelay=208, Bit 13, Center 99 (0 ~ 199) 200
6066 17:16:45.215979
6067 17:16:45.219722 iDelay=208, Bit 14, Center 99 (0 ~ 199) 200
6068 17:16:45.222539 iDelay=208, Bit 15, Center 99 (0 ~ 199) 200
6069 17:16:45.222979 ==
6070 17:16:45.226017 Dram Type= 6, Freq= 0, CH_1, rank 1
6071 17:16:45.229292 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6072 17:16:45.229731 ==
6073 17:16:45.232608 DQS Delay:
6074 17:16:45.233010 DQS0 = 0, DQS1 = 0
6075 17:16:45.233346 DQM Delay:
6076 17:16:45.235676 DQM0 = 100, DQM1 = 93
6077 17:16:45.236075 DQ Delay:
6078 17:16:45.239257 DQ0 =107, DQ1 =95, DQ2 =91, DQ3 =99
6079 17:16:45.242136 DQ4 =95, DQ5 =107, DQ6 =111, DQ7 =95
6080 17:16:45.245601 DQ8 =79, DQ9 =83, DQ10 =95, DQ11 =87
6081 17:16:45.249044 DQ12 =103, DQ13 =99, DQ14 =99, DQ15 =99
6082 17:16:45.249506
6083 17:16:45.249858
6084 17:16:45.252321
6085 17:16:45.252893 ==
6086 17:16:45.255391 Dram Type= 6, Freq= 0, CH_1, rank 1
6087 17:16:45.259075 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6088 17:16:45.259513 ==
6089 17:16:45.259856
6090 17:16:45.260181
6091 17:16:45.262394 TX Vref Scan disable
6092 17:16:45.262834 == TX Byte 0 ==
6093 17:16:45.268532 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
6094 17:16:45.271974 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
6095 17:16:45.272415 == TX Byte 1 ==
6096 17:16:45.278374 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
6097 17:16:45.282009 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
6098 17:16:45.282473 ==
6099 17:16:45.284932 Dram Type= 6, Freq= 0, CH_1, rank 1
6100 17:16:45.288396 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6101 17:16:45.288853 ==
6102 17:16:45.289204
6103 17:16:45.289573
6104 17:16:45.291414 TX Vref Scan disable
6105 17:16:45.295119 == TX Byte 0 ==
6106 17:16:45.297964 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
6107 17:16:45.301652 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
6108 17:16:45.304718 == TX Byte 1 ==
6109 17:16:45.308121 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
6110 17:16:45.311732 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
6111 17:16:45.312290
6112 17:16:45.314968 [DATLAT]
6113 17:16:45.315412 Freq=933, CH1 RK1
6114 17:16:45.315763
6115 17:16:45.318152 DATLAT Default: 0xb
6116 17:16:45.318595 0, 0xFFFF, sum = 0
6117 17:16:45.321156 1, 0xFFFF, sum = 0
6118 17:16:45.321643 2, 0xFFFF, sum = 0
6119 17:16:45.324689 3, 0xFFFF, sum = 0
6120 17:16:45.325235 4, 0xFFFF, sum = 0
6121 17:16:45.328431 5, 0xFFFF, sum = 0
6122 17:16:45.329009 6, 0xFFFF, sum = 0
6123 17:16:45.331378 7, 0xFFFF, sum = 0
6124 17:16:45.331925 8, 0xFFFF, sum = 0
6125 17:16:45.334576 9, 0xFFFF, sum = 0
6126 17:16:45.335028 10, 0x0, sum = 1
6127 17:16:45.337874 11, 0x0, sum = 2
6128 17:16:45.338324 12, 0x0, sum = 3
6129 17:16:45.341622 13, 0x0, sum = 4
6130 17:16:45.342068 best_step = 11
6131 17:16:45.342412
6132 17:16:45.342735 ==
6133 17:16:45.344715 Dram Type= 6, Freq= 0, CH_1, rank 1
6134 17:16:45.351072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6135 17:16:45.351517 ==
6136 17:16:45.351868 RX Vref Scan: 0
6137 17:16:45.352195
6138 17:16:45.354028 RX Vref 0 -> 0, step: 1
6139 17:16:45.354474
6140 17:16:45.357682 RX Delay -61 -> 252, step: 4
6141 17:16:45.360941 iDelay=207, Bit 0, Center 106 (19 ~ 194) 176
6142 17:16:45.367632 iDelay=207, Bit 1, Center 96 (11 ~ 182) 172
6143 17:16:45.371025 iDelay=207, Bit 2, Center 92 (7 ~ 178) 172
6144 17:16:45.374241 iDelay=207, Bit 3, Center 98 (15 ~ 182) 168
6145 17:16:45.377660 iDelay=207, Bit 4, Center 100 (11 ~ 190) 180
6146 17:16:45.381177 iDelay=207, Bit 5, Center 112 (27 ~ 198) 172
6147 17:16:45.383996 iDelay=207, Bit 6, Center 116 (27 ~ 206) 180
6148 17:16:45.390816 iDelay=207, Bit 7, Center 96 (7 ~ 186) 180
6149 17:16:45.394475 iDelay=207, Bit 8, Center 84 (-5 ~ 174) 180
6150 17:16:45.397776 iDelay=207, Bit 9, Center 84 (-5 ~ 174) 180
6151 17:16:45.400529 iDelay=207, Bit 10, Center 94 (3 ~ 186) 184
6152 17:16:45.404048 iDelay=207, Bit 11, Center 84 (-5 ~ 174) 180
6153 17:16:45.410477 iDelay=207, Bit 12, Center 104 (15 ~ 194) 180
6154 17:16:45.413955 iDelay=207, Bit 13, Center 104 (15 ~ 194) 180
6155 17:16:45.417555 iDelay=207, Bit 14, Center 102 (15 ~ 190) 176
6156 17:16:45.420473 iDelay=207, Bit 15, Center 104 (15 ~ 194) 180
6157 17:16:45.420917 ==
6158 17:16:45.424097 Dram Type= 6, Freq= 0, CH_1, rank 1
6159 17:16:45.430453 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6160 17:16:45.430927 ==
6161 17:16:45.431276 DQS Delay:
6162 17:16:45.433657 DQS0 = 0, DQS1 = 0
6163 17:16:45.434097 DQM Delay:
6164 17:16:45.434447 DQM0 = 102, DQM1 = 95
6165 17:16:45.437156 DQ Delay:
6166 17:16:45.440096 DQ0 =106, DQ1 =96, DQ2 =92, DQ3 =98
6167 17:16:45.443535 DQ4 =100, DQ5 =112, DQ6 =116, DQ7 =96
6168 17:16:45.446770 DQ8 =84, DQ9 =84, DQ10 =94, DQ11 =84
6169 17:16:45.450232 DQ12 =104, DQ13 =104, DQ14 =102, DQ15 =104
6170 17:16:45.450676
6171 17:16:45.451027
6172 17:16:45.456661 [DQSOSCAuto] RK1, (LSB)MR18= 0x5ff, (MSB)MR19= 0x504, tDQSOscB0 = 422 ps tDQSOscB1 = 420 ps
6173 17:16:45.460460 CH1 RK1: MR19=504, MR18=5FF
6174 17:16:45.466774 CH1_RK1: MR19=0x504, MR18=0x5FF, DQSOSC=420, MR23=63, INC=61, DEC=40
6175 17:16:45.469641 [RxdqsGatingPostProcess] freq 933
6176 17:16:45.476597 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6177 17:16:45.477077 best DQS0 dly(2T, 0.5T) = (0, 10)
6178 17:16:45.479543
6179 17:16:45.480006 best DQS1 dly(2T, 0.5T) = (0, 10)
6180 17:16:45.483100 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6181 17:16:45.486627 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6182 17:16:45.489605 best DQS0 dly(2T, 0.5T) = (0, 10)
6183 17:16:45.492833 best DQS1 dly(2T, 0.5T) = (0, 10)
6184 17:16:45.496452 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6185 17:16:45.499557 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6186 17:16:45.503010 Pre-setting of DQS Precalculation
6187 17:16:45.509598 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6188 17:16:45.515829 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6189 17:16:45.522323 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6190 17:16:45.522410
6191 17:16:45.522479
6192 17:16:45.526388 [Calibration Summary] 1866 Mbps
6193 17:16:45.526849 CH 0, Rank 0
6194 17:16:45.529391 SW Impedance : PASS
6195 17:16:45.532867 DUTY Scan : NO K
6196 17:16:45.533308 ZQ Calibration : PASS
6197 17:16:45.536187 Jitter Meter : NO K
6198 17:16:45.539540 CBT Training : PASS
6199 17:16:45.539983 Write leveling : PASS
6200 17:16:45.542808 RX DQS gating : PASS
6201 17:16:45.543248 RX DQ/DQS(RDDQC) : PASS
6202 17:16:45.545773 TX DQ/DQS : PASS
6203 17:16:45.549380 RX DATLAT : PASS
6204 17:16:45.549826 RX DQ/DQS(Engine): PASS
6205 17:16:45.552479 TX OE : NO K
6206 17:16:45.552926 All Pass.
6207 17:16:45.553276
6208 17:16:45.555871 CH 0, Rank 1
6209 17:16:45.556312 SW Impedance : PASS
6210 17:16:45.558964 DUTY Scan : NO K
6211 17:16:45.562743 ZQ Calibration : PASS
6212 17:16:45.563185 Jitter Meter : NO K
6213 17:16:45.565532 CBT Training : PASS
6214 17:16:45.568961 Write leveling : PASS
6215 17:16:45.569436 RX DQS gating : PASS
6216 17:16:45.572500 RX DQ/DQS(RDDQC) : PASS
6217 17:16:45.575992 TX DQ/DQS : PASS
6218 17:16:45.576411 RX DATLAT : PASS
6219 17:16:45.578616 RX DQ/DQS(Engine): PASS
6220 17:16:45.582442 TX OE : NO K
6221 17:16:45.582528 All Pass.
6222 17:16:45.582596
6223 17:16:45.582660 CH 1, Rank 0
6224 17:16:45.585283 SW Impedance : PASS
6225 17:16:45.588792 DUTY Scan : NO K
6226 17:16:45.588878 ZQ Calibration : PASS
6227 17:16:45.591889 Jitter Meter : NO K
6228 17:16:45.595519 CBT Training : PASS
6229 17:16:45.595626 Write leveling : PASS
6230 17:16:45.598597 RX DQS gating : PASS
6231 17:16:45.601624 RX DQ/DQS(RDDQC) : PASS
6232 17:16:45.601729 TX DQ/DQS : PASS
6233 17:16:45.605212 RX DATLAT : PASS
6234 17:16:45.608149 RX DQ/DQS(Engine): PASS
6235 17:16:45.608268 TX OE : NO K
6236 17:16:45.608359 All Pass.
6237 17:16:45.611455
6238 17:16:45.611581
6239 17:16:45.611679 CH 1, Rank 1
6240 17:16:45.614877 SW Impedance : PASS
6241 17:16:45.615002 DUTY Scan : NO K
6242 17:16:45.618268 ZQ Calibration : PASS
6243 17:16:45.621755 Jitter Meter : NO K
6244 17:16:45.621910 CBT Training : PASS
6245 17:16:45.624772 Write leveling : PASS
6246 17:16:45.627986 RX DQS gating : PASS
6247 17:16:45.628164 RX DQ/DQS(RDDQC) : PASS
6248 17:16:45.631599 TX DQ/DQS : PASS
6249 17:16:45.631807 RX DATLAT : PASS
6250 17:16:45.634549 RX DQ/DQS(Engine): PASS
6251 17:16:45.638049 TX OE : NO K
6252 17:16:45.638298 All Pass.
6253 17:16:45.638492
6254 17:16:45.641010 DramC Write-DBI off
6255 17:16:45.644968 PER_BANK_REFRESH: Hybrid Mode
6256 17:16:45.645303 TX_TRACKING: ON
6257 17:16:45.654611 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6258 17:16:45.657935 [FAST_K] Save calibration result to emmc
6259 17:16:45.661735 dramc_set_vcore_voltage set vcore to 650000
6260 17:16:45.664639 Read voltage for 400, 6
6261 17:16:45.665073 Vio18 = 0
6262 17:16:45.665455 Vcore = 650000
6263 17:16:45.668153 Vdram = 0
6264 17:16:45.668604 Vddq = 0
6265 17:16:45.668950 Vmddr = 0
6266 17:16:45.674676 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6267 17:16:45.677624 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6268 17:16:45.681149 MEM_TYPE=3, freq_sel=20
6269 17:16:45.684516 sv_algorithm_assistance_LP4_800
6270 17:16:45.688001 ============ PULL DRAM RESETB DOWN ============
6271 17:16:45.691065 ========== PULL DRAM RESETB DOWN end =========
6272 17:16:45.697813 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6273 17:16:45.701101 ===================================
6274 17:16:45.701565 LPDDR4 DRAM CONFIGURATION
6275 17:16:45.704236 ===================================
6276 17:16:45.708126 EX_ROW_EN[0] = 0x0
6277 17:16:45.711440 EX_ROW_EN[1] = 0x0
6278 17:16:45.712011 LP4Y_EN = 0x0
6279 17:16:45.714271 WORK_FSP = 0x0
6280 17:16:45.714708 WL = 0x2
6281 17:16:45.717996 RL = 0x2
6282 17:16:45.718541 BL = 0x2
6283 17:16:45.721234 RPST = 0x0
6284 17:16:45.721714 RD_PRE = 0x0
6285 17:16:45.724254 WR_PRE = 0x1
6286 17:16:45.724692 WR_PST = 0x0
6287 17:16:45.728012 DBI_WR = 0x0
6288 17:16:45.728571 DBI_RD = 0x0
6289 17:16:45.731366 OTF = 0x1
6290 17:16:45.734241 ===================================
6291 17:16:45.737795 ===================================
6292 17:16:45.738247 ANA top config
6293 17:16:45.740654 ===================================
6294 17:16:45.744272 DLL_ASYNC_EN = 0
6295 17:16:45.747204 ALL_SLAVE_EN = 1
6296 17:16:45.750558 NEW_RANK_MODE = 1
6297 17:16:45.751000 DLL_IDLE_MODE = 1
6298 17:16:45.754248 LP45_APHY_COMB_EN = 1
6299 17:16:45.757593 TX_ODT_DIS = 1
6300 17:16:45.761109 NEW_8X_MODE = 1
6301 17:16:45.764237 ===================================
6302 17:16:45.767052 ===================================
6303 17:16:45.770504 data_rate = 800
6304 17:16:45.770943 CKR = 1
6305 17:16:45.773526 DQ_P2S_RATIO = 4
6306 17:16:45.777379 ===================================
6307 17:16:45.780681 CA_P2S_RATIO = 4
6308 17:16:45.783606 DQ_CA_OPEN = 0
6309 17:16:45.786801 DQ_SEMI_OPEN = 1
6310 17:16:45.790073 CA_SEMI_OPEN = 1
6311 17:16:45.790553 CA_FULL_RATE = 0
6312 17:16:45.793289 DQ_CKDIV4_EN = 0
6313 17:16:45.796884 CA_CKDIV4_EN = 1
6314 17:16:45.800266 CA_PREDIV_EN = 0
6315 17:16:45.804083 PH8_DLY = 0
6316 17:16:45.807013 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6317 17:16:45.807553 DQ_AAMCK_DIV = 0
6318 17:16:45.809981 CA_AAMCK_DIV = 0
6319 17:16:45.813623 CA_ADMCK_DIV = 4
6320 17:16:45.816613 DQ_TRACK_CA_EN = 0
6321 17:16:45.820253 CA_PICK = 800
6322 17:16:45.823820 CA_MCKIO = 400
6323 17:16:45.826543 MCKIO_SEMI = 400
6324 17:16:45.827064 PLL_FREQ = 3016
6325 17:16:45.829996
6326 17:16:45.830442 DQ_UI_PI_RATIO = 32
6327 17:16:45.833123 CA_UI_PI_RATIO = 32
6328 17:16:45.836513 ===================================
6329 17:16:45.840174 ===================================
6330 17:16:45.843379 memory_type:LPDDR4
6331 17:16:45.846790 GP_NUM : 10
6332 17:16:45.847241 SRAM_EN : 1
6333 17:16:45.850136 MD32_EN : 0
6334 17:16:45.853683 ===================================
6335 17:16:45.854228 [ANA_INIT] >>>>>>>>>>>>>>
6336 17:16:45.856462 <<<<<< [CONFIGURE PHASE]: ANA_TX
6337 17:16:45.859688 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6338 17:16:45.863220 ===================================
6339 17:16:45.866292 data_rate = 800,PCW = 0X7400
6340 17:16:45.870045 ===================================
6341 17:16:45.873076 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6342 17:16:45.879520 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6343 17:16:45.889967 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6344 17:16:45.896155 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6345 17:16:45.899965 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6346 17:16:45.903008 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6347 17:16:45.903557 [ANA_INIT] flow start
6348 17:16:45.906361 [ANA_INIT] PLL >>>>>>>>
6349 17:16:45.909378 [ANA_INIT] PLL <<<<<<<<
6350 17:16:45.913412 [ANA_INIT] MIDPI >>>>>>>>
6351 17:16:45.913951 [ANA_INIT] MIDPI <<<<<<<<
6352 17:16:45.916120 [ANA_INIT] DLL >>>>>>>>
6353 17:16:45.916552 [ANA_INIT] flow end
6354 17:16:45.919680
6355 17:16:45.922612 ============ LP4 DIFF to SE enter ============
6356 17:16:45.926184 ============ LP4 DIFF to SE exit ============
6357 17:16:45.929279 [ANA_INIT] <<<<<<<<<<<<<
6358 17:16:45.932450 [Flow] Enable top DCM control >>>>>
6359 17:16:45.936330 [Flow] Enable top DCM control <<<<<
6360 17:16:45.939198 Enable DLL master slave shuffle
6361 17:16:45.942575 ==============================================================
6362 17:16:45.945917 Gating Mode config
6363 17:16:45.949551 ==============================================================
6364 17:16:45.952581 Config description:
6365 17:16:45.962272 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6366 17:16:45.968753 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6367 17:16:45.972459 SELPH_MODE 0: By rank 1: By Phase
6368 17:16:45.979042 ==============================================================
6369 17:16:45.981927 GAT_TRACK_EN = 0
6370 17:16:45.985647 RX_GATING_MODE = 2
6371 17:16:45.988788 RX_GATING_TRACK_MODE = 2
6372 17:16:45.992165 SELPH_MODE = 1
6373 17:16:45.995302 PICG_EARLY_EN = 1
6374 17:16:45.998932 VALID_LAT_VALUE = 1
6375 17:16:46.001909 ==============================================================
6376 17:16:46.005831 Enter into Gating configuration >>>>
6377 17:16:46.009206 Exit from Gating configuration <<<<
6378 17:16:46.012137 Enter into DVFS_PRE_config >>>>>
6379 17:16:46.022220 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6380 17:16:46.025291
6381 17:16:46.025851 Exit from DVFS_PRE_config <<<<<
6382 17:16:46.029192 Enter into PICG configuration >>>>
6383 17:16:46.032128 Exit from PICG configuration <<<<
6384 17:16:46.035206 [RX_INPUT] configuration >>>>>
6385 17:16:46.038929 [RX_INPUT] configuration <<<<<
6386 17:16:46.045436 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6387 17:16:46.048309 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6388 17:16:46.055005 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6389 17:16:46.061499 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6390 17:16:46.068263 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6391 17:16:46.074482 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6392 17:16:46.078175 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6393 17:16:46.081551 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6394 17:16:46.084516 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6395 17:16:46.091363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6396 17:16:46.094702 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6397 17:16:46.097594 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6398 17:16:46.101270 ===================================
6399 17:16:46.104448 LPDDR4 DRAM CONFIGURATION
6400 17:16:46.108162 ===================================
6401 17:16:46.110855 EX_ROW_EN[0] = 0x0
6402 17:16:46.111289 EX_ROW_EN[1] = 0x0
6403 17:16:46.114808 LP4Y_EN = 0x0
6404 17:16:46.115364 WORK_FSP = 0x0
6405 17:16:46.117731 WL = 0x2
6406 17:16:46.118164 RL = 0x2
6407 17:16:46.121091 BL = 0x2
6408 17:16:46.121582 RPST = 0x0
6409 17:16:46.124244 RD_PRE = 0x0
6410 17:16:46.124675 WR_PRE = 0x1
6411 17:16:46.127364 WR_PST = 0x0
6412 17:16:46.127794 DBI_WR = 0x0
6413 17:16:46.130810 DBI_RD = 0x0
6414 17:16:46.131242 OTF = 0x1
6415 17:16:46.134166 ===================================
6416 17:16:46.140599 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6417 17:16:46.143913 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6418 17:16:46.147585 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6419 17:16:46.151107 ===================================
6420 17:16:46.154041 LPDDR4 DRAM CONFIGURATION
6421 17:16:46.157737 ===================================
6422 17:16:46.160581 EX_ROW_EN[0] = 0x10
6423 17:16:46.161109 EX_ROW_EN[1] = 0x0
6424 17:16:46.163911 LP4Y_EN = 0x0
6425 17:16:46.164442 WORK_FSP = 0x0
6426 17:16:46.167144 WL = 0x2
6427 17:16:46.167579 RL = 0x2
6428 17:16:46.170567 BL = 0x2
6429 17:16:46.171007 RPST = 0x0
6430 17:16:46.173418 RD_PRE = 0x0
6431 17:16:46.173849 WR_PRE = 0x1
6432 17:16:46.177086 WR_PST = 0x0
6433 17:16:46.177571 DBI_WR = 0x0
6434 17:16:46.179971 DBI_RD = 0x0
6435 17:16:46.180402 OTF = 0x1
6436 17:16:46.183577 ===================================
6437 17:16:46.189861 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6438 17:16:46.195266 nWR fixed to 30
6439 17:16:46.198274 [ModeRegInit_LP4] CH0 RK0
6440 17:16:46.198706 [ModeRegInit_LP4] CH0 RK1
6441 17:16:46.201634 [ModeRegInit_LP4] CH1 RK0
6442 17:16:46.205406 [ModeRegInit_LP4] CH1 RK1
6443 17:16:46.205839 match AC timing 19
6444 17:16:46.211409 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6445 17:16:46.215168 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6446 17:16:46.218145 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6447 17:16:46.224826 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6448 17:16:46.228281 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6449 17:16:46.228718 ==
6450 17:16:46.231338 Dram Type= 6, Freq= 0, CH_0, rank 0
6451 17:16:46.234982 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6452 17:16:46.235421 ==
6453 17:16:46.241487 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6454 17:16:46.248267 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6455 17:16:46.251773 [CA 0] Center 36 (8~64) winsize 57
6456 17:16:46.254370 [CA 1] Center 36 (8~64) winsize 57
6457 17:16:46.257601 [CA 2] Center 36 (8~64) winsize 57
6458 17:16:46.260811 [CA 3] Center 36 (8~64) winsize 57
6459 17:16:46.260894 [CA 4] Center 36 (8~64) winsize 57
6460 17:16:46.264403 [CA 5] Center 36 (8~64) winsize 57
6461 17:16:46.264493
6462 17:16:46.270813 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6463 17:16:46.270909
6464 17:16:46.274046 [CATrainingPosCal] consider 1 rank data
6465 17:16:46.277593 u2DelayCellTimex100 = 270/100 ps
6466 17:16:46.281079 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6467 17:16:46.284261 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6468 17:16:46.287556 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6469 17:16:46.291336 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6470 17:16:46.294458 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6471 17:16:46.297708 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6472 17:16:46.297865
6473 17:16:46.301248 CA PerBit enable=1, Macro0, CA PI delay=36
6474 17:16:46.301447
6475 17:16:46.304737 [CBTSetCACLKResult] CA Dly = 36
6476 17:16:46.307662 CS Dly: 1 (0~32)
6477 17:16:46.307955 ==
6478 17:16:46.311098 Dram Type= 6, Freq= 0, CH_0, rank 1
6479 17:16:46.314144 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6480 17:16:46.314442 ==
6481 17:16:46.321196 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6482 17:16:46.324233 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6483 17:16:46.327727
6484 17:16:46.328159 [CA 0] Center 36 (8~64) winsize 57
6485 17:16:46.330930 [CA 1] Center 36 (8~64) winsize 57
6486 17:16:46.334129 [CA 2] Center 36 (8~64) winsize 57
6487 17:16:46.337660 [CA 3] Center 36 (8~64) winsize 57
6488 17:16:46.341198 [CA 4] Center 36 (8~64) winsize 57
6489 17:16:46.344121 [CA 5] Center 36 (8~64) winsize 57
6490 17:16:46.344563
6491 17:16:46.347555 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6492 17:16:46.347987
6493 17:16:46.350921 [CATrainingPosCal] consider 2 rank data
6494 17:16:46.354095 u2DelayCellTimex100 = 270/100 ps
6495 17:16:46.357260 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6496 17:16:46.364021 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6497 17:16:46.367039 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6498 17:16:46.370800 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6499 17:16:46.373597 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6500 17:16:46.377121 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6501 17:16:46.377586
6502 17:16:46.380086 CA PerBit enable=1, Macro0, CA PI delay=36
6503 17:16:46.380565
6504 17:16:46.383416 [CBTSetCACLKResult] CA Dly = 36
6505 17:16:46.386734 CS Dly: 1 (0~32)
6506 17:16:46.387168
6507 17:16:46.390233 ----->DramcWriteLeveling(PI) begin...
6508 17:16:46.390669 ==
6509 17:16:46.393781 Dram Type= 6, Freq= 0, CH_0, rank 0
6510 17:16:46.396939 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6511 17:16:46.397411 ==
6512 17:16:46.400124 Write leveling (Byte 0): 40 => 8
6513 17:16:46.403258 Write leveling (Byte 1): 32 => 0
6514 17:16:46.406870 DramcWriteLeveling(PI) end<-----
6515 17:16:46.407402
6516 17:16:46.407748 ==
6517 17:16:46.410113 Dram Type= 6, Freq= 0, CH_0, rank 0
6518 17:16:46.413192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6519 17:16:46.413661 ==
6520 17:16:46.416793 [Gating] SW mode calibration
6521 17:16:46.423367 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6522 17:16:46.429815 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6523 17:16:46.433299 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6524 17:16:46.436522 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6525 17:16:46.442808 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6526 17:16:46.446045 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6527 17:16:46.449315 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6528 17:16:46.455998 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6529 17:16:46.459388 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6530 17:16:46.462789 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6531 17:16:46.469296 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6532 17:16:46.472571 Total UI for P1: 0, mck2ui 16
6533 17:16:46.476114 best dqsien dly found for B0: ( 0, 14, 24)
6534 17:16:46.478936 Total UI for P1: 0, mck2ui 16
6535 17:16:46.482461 best dqsien dly found for B1: ( 0, 14, 24)
6536 17:16:46.485438 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6537 17:16:46.489034 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6538 17:16:46.489511
6539 17:16:46.492406 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6540 17:16:46.495450 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6541 17:16:46.498907 [Gating] SW calibration Done
6542 17:16:46.499341 ==
6543 17:16:46.501822 Dram Type= 6, Freq= 0, CH_0, rank 0
6544 17:16:46.505612 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6545 17:16:46.506048 ==
6546 17:16:46.508539 RX Vref Scan: 0
6547 17:16:46.508971
6548 17:16:46.512230 RX Vref 0 -> 0, step: 1
6549 17:16:46.512689
6550 17:16:46.513033 RX Delay -410 -> 252, step: 16
6551 17:16:46.515683
6552 17:16:46.518824 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6553 17:16:46.521946 iDelay=230, Bit 1, Center -27 (-266 ~ 213) 480
6554 17:16:46.525703 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6555 17:16:46.531665 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6556 17:16:46.534952 iDelay=230, Bit 4, Center -27 (-282 ~ 229) 512
6557 17:16:46.538238 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6558 17:16:46.541578 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6559 17:16:46.548312 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6560 17:16:46.551394 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
6561 17:16:46.554852 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6562 17:16:46.557902 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6563 17:16:46.564478 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6564 17:16:46.568156 iDelay=230, Bit 12, Center -43 (-298 ~ 213) 512
6565 17:16:46.571034 iDelay=230, Bit 13, Center -43 (-298 ~ 213) 512
6566 17:16:46.577725 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6567 17:16:46.581090 iDelay=230, Bit 15, Center -43 (-298 ~ 213) 512
6568 17:16:46.581616 ==
6569 17:16:46.584202 Dram Type= 6, Freq= 0, CH_0, rank 0
6570 17:16:46.587538 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6571 17:16:46.587978 ==
6572 17:16:46.591153 DQS Delay:
6573 17:16:46.591582 DQS0 = 43, DQS1 = 59
6574 17:16:46.591919 DQM Delay:
6575 17:16:46.594149 DQM0 = 12, DQM1 = 13
6576 17:16:46.594581 DQ Delay:
6577 17:16:46.597531 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6578 17:16:46.601016 DQ4 =16, DQ5 =0, DQ6 =24, DQ7 =16
6579 17:16:46.604131 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =16
6580 17:16:46.607502 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =16
6581 17:16:46.607936
6582 17:16:46.608279
6583 17:16:46.608595 ==
6584 17:16:46.610889 Dram Type= 6, Freq= 0, CH_0, rank 0
6585 17:16:46.614635 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6586 17:16:46.617707 ==
6587 17:16:46.618150
6588 17:16:46.618492
6589 17:16:46.618810 TX Vref Scan disable
6590 17:16:46.620622 == TX Byte 0 ==
6591 17:16:46.624184 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6592 17:16:46.627690 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6593 17:16:46.630992 == TX Byte 1 ==
6594 17:16:46.633956 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6595 17:16:46.637220 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6596 17:16:46.637709 ==
6597 17:16:46.640806 Dram Type= 6, Freq= 0, CH_0, rank 0
6598 17:16:46.647329 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6599 17:16:46.647764 ==
6600 17:16:46.648105
6601 17:16:46.648422
6602 17:16:46.648726 TX Vref Scan disable
6603 17:16:46.650522 == TX Byte 0 ==
6604 17:16:46.653946 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6605 17:16:46.657558 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6606 17:16:46.660440 == TX Byte 1 ==
6607 17:16:46.664044 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6608 17:16:46.667219 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6609 17:16:46.670536
6610 17:16:46.671089
6611 17:16:46.671439 [DATLAT]
6612 17:16:46.671759 Freq=400, CH0 RK0
6613 17:16:46.672069
6614 17:16:46.673484 DATLAT Default: 0xf
6615 17:16:46.673917 0, 0xFFFF, sum = 0
6616 17:16:46.676922 1, 0xFFFF, sum = 0
6617 17:16:46.677402 2, 0xFFFF, sum = 0
6618 17:16:46.680057 3, 0xFFFF, sum = 0
6619 17:16:46.683603 4, 0xFFFF, sum = 0
6620 17:16:46.684043 5, 0xFFFF, sum = 0
6621 17:16:46.687107 6, 0xFFFF, sum = 0
6622 17:16:46.687547 7, 0xFFFF, sum = 0
6623 17:16:46.689997 8, 0xFFFF, sum = 0
6624 17:16:46.690435 9, 0xFFFF, sum = 0
6625 17:16:46.693552 10, 0xFFFF, sum = 0
6626 17:16:46.693992 11, 0xFFFF, sum = 0
6627 17:16:46.696690 12, 0xFFFF, sum = 0
6628 17:16:46.697153 13, 0x0, sum = 1
6629 17:16:46.700046 14, 0x0, sum = 2
6630 17:16:46.700486 15, 0x0, sum = 3
6631 17:16:46.703531 16, 0x0, sum = 4
6632 17:16:46.703974 best_step = 14
6633 17:16:46.704314
6634 17:16:46.704633 ==
6635 17:16:46.706552 Dram Type= 6, Freq= 0, CH_0, rank 0
6636 17:16:46.710043 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6637 17:16:46.713134 ==
6638 17:16:46.713643 RX Vref Scan: 1
6639 17:16:46.713990
6640 17:16:46.716700 RX Vref 0 -> 0, step: 1
6641 17:16:46.717134
6642 17:16:46.719735 RX Delay -359 -> 252, step: 8
6643 17:16:46.720165
6644 17:16:46.723280 Set Vref, RX VrefLevel [Byte0]: 57
6645 17:16:46.726458 [Byte1]: 47
6646 17:16:46.726890
6647 17:16:46.729608 Final RX Vref Byte 0 = 57 to rank0
6648 17:16:46.733529 Final RX Vref Byte 1 = 47 to rank0
6649 17:16:46.736533 Final RX Vref Byte 0 = 57 to rank1
6650 17:16:46.739907 Final RX Vref Byte 1 = 47 to rank1==
6651 17:16:46.743284 Dram Type= 6, Freq= 0, CH_0, rank 0
6652 17:16:46.746295 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6653 17:16:46.746743 ==
6654 17:16:46.749420 DQS Delay:
6655 17:16:46.749861 DQS0 = 48, DQS1 = 60
6656 17:16:46.753064 DQM Delay:
6657 17:16:46.753643 DQM0 = 11, DQM1 = 12
6658 17:16:46.756631 DQ Delay:
6659 17:16:46.757163 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =8
6660 17:16:46.759601 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6661 17:16:46.762977 DQ8 =4, DQ9 =0, DQ10 =12, DQ11 =4
6662 17:16:46.766208 DQ12 =16, DQ13 =16, DQ14 =24, DQ15 =20
6663 17:16:46.766753
6664 17:16:46.767106
6665 17:16:46.776229 [DQSOSCAuto] RK0, (LSB)MR18= 0xbd80, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 386 ps
6666 17:16:46.779411 CH0 RK0: MR19=C0C, MR18=BD80
6667 17:16:46.785957 CH0_RK0: MR19=0xC0C, MR18=0xBD80, DQSOSC=386, MR23=63, INC=396, DEC=264
6668 17:16:46.786413 ==
6669 17:16:46.789426 Dram Type= 6, Freq= 0, CH_0, rank 1
6670 17:16:46.793032 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6671 17:16:46.793639 ==
6672 17:16:46.796124 [Gating] SW mode calibration
6673 17:16:46.802961 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6674 17:16:46.806078 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6675 17:16:46.812885 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6676 17:16:46.815894 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6677 17:16:46.819086 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6678 17:16:46.825816 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6679 17:16:46.829434 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6680 17:16:46.832327 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6681 17:16:46.839018 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6682 17:16:46.842031 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6683 17:16:46.845710 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6684 17:16:46.849405 Total UI for P1: 0, mck2ui 16
6685 17:16:46.852262 best dqsien dly found for B0: ( 0, 14, 24)
6686 17:16:46.855105 Total UI for P1: 0, mck2ui 16
6687 17:16:46.858688 best dqsien dly found for B1: ( 0, 14, 24)
6688 17:16:46.862219 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6689 17:16:46.868852 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6690 17:16:46.869441
6691 17:16:46.872067 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6692 17:16:46.875621 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6693 17:16:46.878692 [Gating] SW calibration Done
6694 17:16:46.879151 ==
6695 17:16:46.881676 Dram Type= 6, Freq= 0, CH_0, rank 1
6696 17:16:46.885265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6697 17:16:46.885754 ==
6698 17:16:46.888118 RX Vref Scan: 0
6699 17:16:46.888560
6700 17:16:46.888907 RX Vref 0 -> 0, step: 1
6701 17:16:46.889231
6702 17:16:46.891550 RX Delay -410 -> 252, step: 16
6703 17:16:46.895243 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6704 17:16:46.901614 iDelay=230, Bit 1, Center -27 (-282 ~ 229) 512
6705 17:16:46.905240 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6706 17:16:46.907902 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6707 17:16:46.911631 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6708 17:16:46.918108 iDelay=230, Bit 5, Center -43 (-298 ~ 213) 512
6709 17:16:46.921633 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6710 17:16:46.924695 iDelay=230, Bit 7, Center -27 (-282 ~ 229) 512
6711 17:16:46.928207 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6712 17:16:46.934787 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6713 17:16:46.937940 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6714 17:16:46.941670 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6715 17:16:46.948514 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6716 17:16:46.951078 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6717 17:16:46.954672 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6718 17:16:46.957694 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6719 17:16:46.958139 ==
6720 17:16:46.961460 Dram Type= 6, Freq= 0, CH_0, rank 1
6721 17:16:46.968132 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6722 17:16:46.968694 ==
6723 17:16:46.969066 DQS Delay:
6724 17:16:46.971412 DQS0 = 43, DQS1 = 59
6725 17:16:46.971873 DQM Delay:
6726 17:16:46.974447 DQM0 = 10, DQM1 = 16
6727 17:16:46.974955 DQ Delay:
6728 17:16:46.977530 DQ0 =8, DQ1 =16, DQ2 =8, DQ3 =8
6729 17:16:46.981053 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6730 17:16:46.984533 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6731 17:16:46.987622 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6732 17:16:46.988069
6733 17:16:46.988510
6734 17:16:46.988927 ==
6735 17:16:46.990691 Dram Type= 6, Freq= 0, CH_0, rank 1
6736 17:16:46.994559 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6737 17:16:46.995105 ==
6738 17:16:46.995559
6739 17:16:46.995980
6740 17:16:46.997517 TX Vref Scan disable
6741 17:16:46.997963 == TX Byte 0 ==
6742 17:16:47.003889 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6743 17:16:47.007381 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6744 17:16:47.007830 == TX Byte 1 ==
6745 17:16:47.014051 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6746 17:16:47.017652 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6747 17:16:47.018274 ==
6748 17:16:47.020992 Dram Type= 6, Freq= 0, CH_0, rank 1
6749 17:16:47.024117 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6750 17:16:47.024665 ==
6751 17:16:47.025116
6752 17:16:47.025573
6753 17:16:47.027699 TX Vref Scan disable
6754 17:16:47.028248 == TX Byte 0 ==
6755 17:16:47.033934 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
6756 17:16:47.037060 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
6757 17:16:47.037651 == TX Byte 1 ==
6758 17:16:47.043715 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
6759 17:16:47.046856 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
6760 17:16:47.047299
6761 17:16:47.047645 [DATLAT]
6762 17:16:47.050423 Freq=400, CH0 RK1
6763 17:16:47.050864
6764 17:16:47.051213 DATLAT Default: 0xe
6765 17:16:47.053934 0, 0xFFFF, sum = 0
6766 17:16:47.054383 1, 0xFFFF, sum = 0
6767 17:16:47.056828 2, 0xFFFF, sum = 0
6768 17:16:47.057269 3, 0xFFFF, sum = 0
6769 17:16:47.060448 4, 0xFFFF, sum = 0
6770 17:16:47.060889 5, 0xFFFF, sum = 0
6771 17:16:47.063573 6, 0xFFFF, sum = 0
6772 17:16:47.064015 7, 0xFFFF, sum = 0
6773 17:16:47.066640 8, 0xFFFF, sum = 0
6774 17:16:47.067094 9, 0xFFFF, sum = 0
6775 17:16:47.070485
6776 17:16:47.071035 10, 0xFFFF, sum = 0
6777 17:16:47.073221 11, 0xFFFF, sum = 0
6778 17:16:47.073714 12, 0xFFFF, sum = 0
6779 17:16:47.077106 13, 0x0, sum = 1
6780 17:16:47.077704 14, 0x0, sum = 2
6781 17:16:47.079740 15, 0x0, sum = 3
6782 17:16:47.080185 16, 0x0, sum = 4
6783 17:16:47.080535 best_step = 14
6784 17:16:47.080855
6785 17:16:47.083139
6786 17:16:47.083629 ==
6787 17:16:47.086288 Dram Type= 6, Freq= 0, CH_0, rank 1
6788 17:16:47.089809 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6789 17:16:47.090247 ==
6790 17:16:47.090592 RX Vref Scan: 0
6791 17:16:47.090916
6792 17:16:47.093013 RX Vref 0 -> 0, step: 1
6793 17:16:47.093475
6794 17:16:47.096637 RX Delay -359 -> 252, step: 8
6795 17:16:47.103281 iDelay=217, Bit 0, Center -40 (-279 ~ 200) 480
6796 17:16:47.107060 iDelay=217, Bit 1, Center -36 (-279 ~ 208) 488
6797 17:16:47.110664 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6798 17:16:47.113967 iDelay=217, Bit 3, Center -36 (-279 ~ 208) 488
6799 17:16:47.116728
6800 17:16:47.120381 iDelay=217, Bit 4, Center -36 (-279 ~ 208) 488
6801 17:16:47.123690 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6802 17:16:47.126621 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
6803 17:16:47.130203 iDelay=217, Bit 7, Center -28 (-271 ~ 216) 488
6804 17:16:47.133475
6805 17:16:47.136983 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6806 17:16:47.140448 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6807 17:16:47.143357 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6808 17:16:47.150105 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6809 17:16:47.153551 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6810 17:16:47.156578 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6811 17:16:47.159674 iDelay=217, Bit 14, Center -32 (-271 ~ 208) 480
6812 17:16:47.166494 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6813 17:16:47.167045 ==
6814 17:16:47.169710 Dram Type= 6, Freq= 0, CH_0, rank 1
6815 17:16:47.172962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6816 17:16:47.173547 ==
6817 17:16:47.173905 DQS Delay:
6818 17:16:47.176622 DQS0 = 44, DQS1 = 60
6819 17:16:47.177199 DQM Delay:
6820 17:16:47.179803 DQM0 = 8, DQM1 = 16
6821 17:16:47.180242 DQ Delay:
6822 17:16:47.182569 DQ0 =4, DQ1 =8, DQ2 =4, DQ3 =8
6823 17:16:47.186047 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6824 17:16:47.189570 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6825 17:16:47.192653 DQ12 =24, DQ13 =24, DQ14 =28, DQ15 =24
6826 17:16:47.193091
6827 17:16:47.193474
6828 17:16:47.199115 [DQSOSCAuto] RK1, (LSB)MR18= 0xb13b, (MSB)MR19= 0xc0c, tDQSOscB0 = 402 ps tDQSOscB1 = 387 ps
6829 17:16:47.202637 CH0 RK1: MR19=C0C, MR18=B13B
6830 17:16:47.208956 CH0_RK1: MR19=0xC0C, MR18=0xB13B, DQSOSC=387, MR23=63, INC=394, DEC=262
6831 17:16:47.212559 [RxdqsGatingPostProcess] freq 400
6832 17:16:47.218877 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6833 17:16:47.222178 best DQS0 dly(2T, 0.5T) = (0, 10)
6834 17:16:47.225433 best DQS1 dly(2T, 0.5T) = (0, 10)
6835 17:16:47.228637 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6836 17:16:47.232199 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6837 17:16:47.232757 best DQS0 dly(2T, 0.5T) = (0, 10)
6838 17:16:47.235356 best DQS1 dly(2T, 0.5T) = (0, 10)
6839 17:16:47.238864 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6840 17:16:47.241994 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6841 17:16:47.245232 Pre-setting of DQS Precalculation
6842 17:16:47.252278 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6843 17:16:47.252720 ==
6844 17:16:47.255432 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 17:16:47.258660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 17:16:47.259104 ==
6847 17:16:47.265304 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6848 17:16:47.272187 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=33, u1VrefScanEnd=33
6849 17:16:47.275400 [CA 0] Center 36 (8~64) winsize 57
6850 17:16:47.275952 [CA 1] Center 36 (8~64) winsize 57
6851 17:16:47.278525 [CA 2] Center 36 (8~64) winsize 57
6852 17:16:47.282135 [CA 3] Center 36 (8~64) winsize 57
6853 17:16:47.284939 [CA 4] Center 36 (8~64) winsize 57
6854 17:16:47.288177 [CA 5] Center 36 (8~64) winsize 57
6855 17:16:47.288638
6856 17:16:47.291584 [CmdBusTrainingLP45] Vref(ca) range 1: 33
6857 17:16:47.292023
6858 17:16:47.298697 [CATrainingPosCal] consider 1 rank data
6859 17:16:47.299245 u2DelayCellTimex100 = 270/100 ps
6860 17:16:47.301627 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6861 17:16:47.305720
6862 17:16:47.308184 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6863 17:16:47.312076 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6864 17:16:47.314697 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6865 17:16:47.318166 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6866 17:16:47.321141 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6867 17:16:47.321614
6868 17:16:47.324524 CA PerBit enable=1, Macro0, CA PI delay=36
6869 17:16:47.324963
6870 17:16:47.328232 [CBTSetCACLKResult] CA Dly = 36
6871 17:16:47.331158 CS Dly: 1 (0~32)
6872 17:16:47.331593 ==
6873 17:16:47.334645 Dram Type= 6, Freq= 0, CH_1, rank 1
6874 17:16:47.337859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6875 17:16:47.338300 ==
6876 17:16:47.344645 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6877 17:16:47.347634 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6878 17:16:47.351298 [CA 0] Center 36 (8~64) winsize 57
6879 17:16:47.354307 [CA 1] Center 36 (8~64) winsize 57
6880 17:16:47.358228 [CA 2] Center 36 (8~64) winsize 57
6881 17:16:47.361028 [CA 3] Center 36 (8~64) winsize 57
6882 17:16:47.364266 [CA 4] Center 36 (8~64) winsize 57
6883 17:16:47.367793 [CA 5] Center 36 (8~64) winsize 57
6884 17:16:47.368368
6885 17:16:47.370953 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6886 17:16:47.371397
6887 17:16:47.374117 [CATrainingPosCal] consider 2 rank data
6888 17:16:47.377545 u2DelayCellTimex100 = 270/100 ps
6889 17:16:47.380519 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6890 17:16:47.383882 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6891 17:16:47.390526 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6892 17:16:47.394211 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6893 17:16:47.397458 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6894 17:16:47.400563 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6895 17:16:47.401006
6896 17:16:47.404129 CA PerBit enable=1, Macro0, CA PI delay=36
6897 17:16:47.404568
6898 17:16:47.407295 [CBTSetCACLKResult] CA Dly = 36
6899 17:16:47.407856 CS Dly: 1 (0~32)
6900 17:16:47.408214
6901 17:16:47.410534 ----->DramcWriteLeveling(PI) begin...
6902 17:16:47.413754 ==
6903 17:16:47.417354 Dram Type= 6, Freq= 0, CH_1, rank 0
6904 17:16:47.420227 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6905 17:16:47.420682 ==
6906 17:16:47.423548 Write leveling (Byte 0): 40 => 8
6907 17:16:47.426797 Write leveling (Byte 1): 32 => 0
6908 17:16:47.430271 DramcWriteLeveling(PI) end<-----
6909 17:16:47.430716
6910 17:16:47.431108 ==
6911 17:16:47.433993 Dram Type= 6, Freq= 0, CH_1, rank 0
6912 17:16:47.436880 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6913 17:16:47.437475 ==
6914 17:16:47.440650 [Gating] SW mode calibration
6915 17:16:47.447354 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6916 17:16:47.453896 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6917 17:16:47.456995 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6918 17:16:47.460573 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6919 17:16:47.466654 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6920 17:16:47.470327 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6921 17:16:47.473307 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6922 17:16:47.479844 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6923 17:16:47.483348 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6924 17:16:47.486373 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6925 17:16:47.493454 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6926 17:16:47.493900 Total UI for P1: 0, mck2ui 16
6927 17:16:47.496809 best dqsien dly found for B0: ( 0, 14, 24)
6928 17:16:47.499597 Total UI for P1: 0, mck2ui 16
6929 17:16:47.503231 best dqsien dly found for B1: ( 0, 14, 24)
6930 17:16:47.509662 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6931 17:16:47.513136 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6932 17:16:47.513745
6933 17:16:47.516542 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6934 17:16:47.519573 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6935 17:16:47.522941 [Gating] SW calibration Done
6936 17:16:47.523402 ==
6937 17:16:47.525924 Dram Type= 6, Freq= 0, CH_1, rank 0
6938 17:16:47.529411 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6939 17:16:47.529852 ==
6940 17:16:47.532887 RX Vref Scan: 0
6941 17:16:47.533467
6942 17:16:47.533832 RX Vref 0 -> 0, step: 1
6943 17:16:47.534161
6944 17:16:47.536467 RX Delay -410 -> 252, step: 16
6945 17:16:47.542876 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6946 17:16:47.546321 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6947 17:16:47.549415 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6948 17:16:47.552770 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6949 17:16:47.559236 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6950 17:16:47.562191 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6951 17:16:47.565750 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6952 17:16:47.569075 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6953 17:16:47.575794 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6954 17:16:47.578927 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
6955 17:16:47.582002 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6956 17:16:47.585948 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6957 17:16:47.592134 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6958 17:16:47.595220 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6959 17:16:47.598519 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
6960 17:16:47.605079 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6961 17:16:47.605601 ==
6962 17:16:47.608368 Dram Type= 6, Freq= 0, CH_1, rank 0
6963 17:16:47.612045 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6964 17:16:47.612510 ==
6965 17:16:47.612862 DQS Delay:
6966 17:16:47.615034 DQS0 = 43, DQS1 = 51
6967 17:16:47.615487 DQM Delay:
6968 17:16:47.618466 DQM0 = 13, DQM1 = 14
6969 17:16:47.618924 DQ Delay:
6970 17:16:47.622023 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6971 17:16:47.624866 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6972 17:16:47.628300 DQ8 =0, DQ9 =8, DQ10 =8, DQ11 =0
6973 17:16:47.631654 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6974 17:16:47.632094
6975 17:16:47.632485
6976 17:16:47.632814 ==
6977 17:16:47.635172 Dram Type= 6, Freq= 0, CH_1, rank 0
6978 17:16:47.638268 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6979 17:16:47.638709 ==
6980 17:16:47.639055
6981 17:16:47.639375
6982 17:16:47.641570 TX Vref Scan disable
6983 17:16:47.642009 == TX Byte 0 ==
6984 17:16:47.648425 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6985 17:16:47.651726 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6986 17:16:47.652166 == TX Byte 1 ==
6987 17:16:47.658113 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
6988 17:16:47.661168 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
6989 17:16:47.661630 ==
6990 17:16:47.665017 Dram Type= 6, Freq= 0, CH_1, rank 0
6991 17:16:47.668056 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6992 17:16:47.668617 ==
6993 17:16:47.668971
6994 17:16:47.669299
6995 17:16:47.671424 TX Vref Scan disable
6996 17:16:47.674606 == TX Byte 0 ==
6997 17:16:47.677892 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6998 17:16:47.681147 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6999 17:16:47.685146 == TX Byte 1 ==
7000 17:16:47.687927 Update DQ dly =572 (4 ,1, 28) DQ OEN =(3 ,2)
7001 17:16:47.691410 Update DQM dly =572 (4 ,1, 28) DQM OEN =(3 ,2)
7002 17:16:47.691850
7003 17:16:47.692237 [DATLAT]
7004 17:16:47.694309 Freq=400, CH1 RK0
7005 17:16:47.694778
7006 17:16:47.698228 DATLAT Default: 0xf
7007 17:16:47.698667 0, 0xFFFF, sum = 0
7008 17:16:47.701106 1, 0xFFFF, sum = 0
7009 17:16:47.701588 2, 0xFFFF, sum = 0
7010 17:16:47.704173 3, 0xFFFF, sum = 0
7011 17:16:47.704616 4, 0xFFFF, sum = 0
7012 17:16:47.707786 5, 0xFFFF, sum = 0
7013 17:16:47.708277 6, 0xFFFF, sum = 0
7014 17:16:47.710963 7, 0xFFFF, sum = 0
7015 17:16:47.711510 8, 0xFFFF, sum = 0
7016 17:16:47.714423 9, 0xFFFF, sum = 0
7017 17:16:47.714872 10, 0xFFFF, sum = 0
7018 17:16:47.717747 11, 0xFFFF, sum = 0
7019 17:16:47.718249 12, 0xFFFF, sum = 0
7020 17:16:47.720878 13, 0x0, sum = 1
7021 17:16:47.721352 14, 0x0, sum = 2
7022 17:16:47.724274 15, 0x0, sum = 3
7023 17:16:47.724832 16, 0x0, sum = 4
7024 17:16:47.727467 best_step = 14
7025 17:16:47.727905
7026 17:16:47.728253 ==
7027 17:16:47.731181 Dram Type= 6, Freq= 0, CH_1, rank 0
7028 17:16:47.734025 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7029 17:16:47.734485 ==
7030 17:16:47.737144 RX Vref Scan: 1
7031 17:16:47.737630
7032 17:16:47.738028 RX Vref 0 -> 0, step: 1
7033 17:16:47.738360
7034 17:16:47.740684 RX Delay -343 -> 252, step: 8
7035 17:16:47.741155
7036 17:16:47.743612 Set Vref, RX VrefLevel [Byte0]: 47
7037 17:16:47.747357 [Byte1]: 60
7038 17:16:47.751766
7039 17:16:47.752228 Final RX Vref Byte 0 = 47 to rank0
7040 17:16:47.755045 Final RX Vref Byte 1 = 60 to rank0
7041 17:16:47.758624 Final RX Vref Byte 0 = 47 to rank1
7042 17:16:47.761761 Final RX Vref Byte 1 = 60 to rank1==
7043 17:16:47.765135 Dram Type= 6, Freq= 0, CH_1, rank 0
7044 17:16:47.771850 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7045 17:16:47.772325 ==
7046 17:16:47.772682 DQS Delay:
7047 17:16:47.775416 DQS0 = 44, DQS1 = 56
7048 17:16:47.775853 DQM Delay:
7049 17:16:47.776198 DQM0 = 7, DQM1 = 12
7050 17:16:47.778408 DQ Delay:
7051 17:16:47.781432 DQ0 =12, DQ1 =4, DQ2 =0, DQ3 =4
7052 17:16:47.781873 DQ4 =4, DQ5 =16, DQ6 =16, DQ7 =4
7053 17:16:47.785256 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7054 17:16:47.788525 DQ12 =20, DQ13 =16, DQ14 =20, DQ15 =24
7055 17:16:47.788971
7056 17:16:47.789319
7057 17:16:47.791580
7058 17:16:47.798546 [DQSOSCAuto] RK0, (LSB)MR18= 0x9368, (MSB)MR19= 0xc0c, tDQSOscB0 = 396 ps tDQSOscB1 = 391 ps
7059 17:16:47.801613 CH1 RK0: MR19=C0C, MR18=9368
7060 17:16:47.808641 CH1_RK0: MR19=0xC0C, MR18=0x9368, DQSOSC=391, MR23=63, INC=386, DEC=257
7061 17:16:47.809185 ==
7062 17:16:47.811815 Dram Type= 6, Freq= 0, CH_1, rank 1
7063 17:16:47.814883 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7064 17:16:47.815430 ==
7065 17:16:47.818327 [Gating] SW mode calibration
7066 17:16:47.824657 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
7067 17:16:47.831353 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
7068 17:16:47.834980 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7069 17:16:47.837995 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7070 17:16:47.844627 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7071 17:16:47.848002 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7072 17:16:47.850964 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7073 17:16:47.857736 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7074 17:16:47.861271 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7075 17:16:47.864239 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7076 17:16:47.868142 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7077 17:16:47.871214
7078 17:16:47.871677 Total UI for P1: 0, mck2ui 16
7079 17:16:47.874497 best dqsien dly found for B0: ( 0, 14, 24)
7080 17:16:47.877482 Total UI for P1: 0, mck2ui 16
7081 17:16:47.881038 best dqsien dly found for B1: ( 0, 14, 24)
7082 17:16:47.887359 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
7083 17:16:47.890576 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
7084 17:16:47.891016
7085 17:16:47.894151 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
7086 17:16:47.897209 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
7087 17:16:47.900557 [Gating] SW calibration Done
7088 17:16:47.901092 ==
7089 17:16:47.903744 Dram Type= 6, Freq= 0, CH_1, rank 1
7090 17:16:47.907128 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7091 17:16:47.907568 ==
7092 17:16:47.910893 RX Vref Scan: 0
7093 17:16:47.911331
7094 17:16:47.911676 RX Vref 0 -> 0, step: 1
7095 17:16:47.911995
7096 17:16:47.913858 RX Delay -410 -> 252, step: 16
7097 17:16:47.920659 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
7098 17:16:47.923575 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
7099 17:16:47.926950 iDelay=230, Bit 2, Center -51 (-298 ~ 197) 496
7100 17:16:47.930525 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
7101 17:16:47.937260 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
7102 17:16:47.940323 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
7103 17:16:47.943564 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
7104 17:16:47.946801 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
7105 17:16:47.953550 iDelay=230, Bit 8, Center -59 (-314 ~ 197) 512
7106 17:16:47.956739 iDelay=230, Bit 9, Center -43 (-298 ~ 213) 512
7107 17:16:47.960343 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
7108 17:16:47.963556 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
7109 17:16:47.969970 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
7110 17:16:47.973453 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
7111 17:16:47.976435 iDelay=230, Bit 14, Center -27 (-282 ~ 229) 512
7112 17:16:47.983499 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
7113 17:16:47.984076 ==
7114 17:16:47.986132 Dram Type= 6, Freq= 0, CH_1, rank 1
7115 17:16:47.989791 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7116 17:16:47.990242 ==
7117 17:16:47.990671 DQS Delay:
7118 17:16:47.992890 DQS0 = 51, DQS1 = 59
7119 17:16:47.993349 DQM Delay:
7120 17:16:47.996384 DQM0 = 19, DQM1 = 22
7121 17:16:47.996822 DQ Delay:
7122 17:16:47.999441 DQ0 =24, DQ1 =16, DQ2 =0, DQ3 =16
7123 17:16:48.002865 DQ4 =16, DQ5 =32, DQ6 =32, DQ7 =16
7124 17:16:48.006058 DQ8 =0, DQ9 =16, DQ10 =16, DQ11 =16
7125 17:16:48.009919 DQ12 =32, DQ13 =32, DQ14 =32, DQ15 =32
7126 17:16:48.010462
7127 17:16:48.010837
7128 17:16:48.011170 ==
7129 17:16:48.012699 Dram Type= 6, Freq= 0, CH_1, rank 1
7130 17:16:48.016065 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7131 17:16:48.016503 ==
7132 17:16:48.016847
7133 17:16:48.019234
7134 17:16:48.019715 TX Vref Scan disable
7135 17:16:48.022683 == TX Byte 0 ==
7136 17:16:48.026193 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
7137 17:16:48.029151 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
7138 17:16:48.032809 == TX Byte 1 ==
7139 17:16:48.035836 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7140 17:16:48.039235 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7141 17:16:48.039669 ==
7142 17:16:48.042715 Dram Type= 6, Freq= 0, CH_1, rank 1
7143 17:16:48.045775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7144 17:16:48.048918 ==
7145 17:16:48.049380
7146 17:16:48.049747
7147 17:16:48.050071 TX Vref Scan disable
7148 17:16:48.052525 == TX Byte 0 ==
7149 17:16:48.056060 Update DQ dly =585 (4 ,2, 9) DQ OEN =(3 ,3)
7150 17:16:48.059106 Update DQM dly =585 (4 ,2, 9) DQM OEN =(3 ,3)
7151 17:16:48.062499 == TX Byte 1 ==
7152 17:16:48.065765 Update DQ dly =581 (4 ,2, 5) DQ OEN =(3 ,3)
7153 17:16:48.068921 Update DQM dly =581 (4 ,2, 5) DQM OEN =(3 ,3)
7154 17:16:48.069509
7155 17:16:48.069868 [DATLAT]
7156 17:16:48.072515
7157 17:16:48.072948 Freq=400, CH1 RK1
7158 17:16:48.073294
7159 17:16:48.075522 DATLAT Default: 0xe
7160 17:16:48.075956 0, 0xFFFF, sum = 0
7161 17:16:48.078894 1, 0xFFFF, sum = 0
7162 17:16:48.079351 2, 0xFFFF, sum = 0
7163 17:16:48.082663 3, 0xFFFF, sum = 0
7164 17:16:48.083104 4, 0xFFFF, sum = 0
7165 17:16:48.085629 5, 0xFFFF, sum = 0
7166 17:16:48.086069 6, 0xFFFF, sum = 0
7167 17:16:48.089002 7, 0xFFFF, sum = 0
7168 17:16:48.089507 8, 0xFFFF, sum = 0
7169 17:16:48.092425 9, 0xFFFF, sum = 0
7170 17:16:48.092866 10, 0xFFFF, sum = 0
7171 17:16:48.095615 11, 0xFFFF, sum = 0
7172 17:16:48.096055 12, 0xFFFF, sum = 0
7173 17:16:48.098665 13, 0x0, sum = 1
7174 17:16:48.099104 14, 0x0, sum = 2
7175 17:16:48.101950 15, 0x0, sum = 3
7176 17:16:48.102350 16, 0x0, sum = 4
7177 17:16:48.105306 best_step = 14
7178 17:16:48.105734
7179 17:16:48.106067 ==
7180 17:16:48.108440 Dram Type= 6, Freq= 0, CH_1, rank 1
7181 17:16:48.111926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7182 17:16:48.112448 ==
7183 17:16:48.114980 RX Vref Scan: 0
7184 17:16:48.115439
7185 17:16:48.115782 RX Vref 0 -> 0, step: 1
7186 17:16:48.116103
7187 17:16:48.118462 RX Delay -359 -> 252, step: 8
7188 17:16:48.126567 iDelay=225, Bit 0, Center -32 (-271 ~ 208) 480
7189 17:16:48.129962 iDelay=225, Bit 1, Center -40 (-279 ~ 200) 480
7190 17:16:48.133592 iDelay=225, Bit 2, Center -48 (-287 ~ 192) 480
7191 17:16:48.137003 iDelay=225, Bit 3, Center -40 (-279 ~ 200) 480
7192 17:16:48.142939 iDelay=225, Bit 4, Center -36 (-279 ~ 208) 488
7193 17:16:48.146490 iDelay=225, Bit 5, Center -24 (-263 ~ 216) 480
7194 17:16:48.150047 iDelay=225, Bit 6, Center -24 (-271 ~ 224) 496
7195 17:16:48.153138 iDelay=225, Bit 7, Center -40 (-287 ~ 208) 496
7196 17:16:48.156103
7197 17:16:48.159525 iDelay=225, Bit 8, Center -56 (-303 ~ 192) 496
7198 17:16:48.163069 iDelay=225, Bit 9, Center -56 (-303 ~ 192) 496
7199 17:16:48.166228 iDelay=225, Bit 10, Center -44 (-295 ~ 208) 504
7200 17:16:48.172781 iDelay=225, Bit 11, Center -52 (-303 ~ 200) 504
7201 17:16:48.176443 iDelay=225, Bit 12, Center -36 (-287 ~ 216) 504
7202 17:16:48.179737 iDelay=225, Bit 13, Center -36 (-287 ~ 216) 504
7203 17:16:48.182686 iDelay=225, Bit 14, Center -36 (-287 ~ 216) 504
7204 17:16:48.189214 iDelay=225, Bit 15, Center -36 (-287 ~ 216) 504
7205 17:16:48.189737 ==
7206 17:16:48.192570 Dram Type= 6, Freq= 0, CH_1, rank 1
7207 17:16:48.196165 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7208 17:16:48.196603 ==
7209 17:16:48.196944 DQS Delay:
7210 17:16:48.199390 DQS0 = 48, DQS1 = 56
7211 17:16:48.199936 DQM Delay:
7212 17:16:48.202508 DQM0 = 12, DQM1 = 12
7213 17:16:48.202938 DQ Delay:
7214 17:16:48.205975 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7215 17:16:48.209593 DQ4 =12, DQ5 =24, DQ6 =24, DQ7 =8
7216 17:16:48.212739 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
7217 17:16:48.216250 DQ12 =20, DQ13 =20, DQ14 =20, DQ15 =20
7218 17:16:48.216697
7219 17:16:48.217040
7220 17:16:48.222434 [DQSOSCAuto] RK1, (LSB)MR18= 0x6452, (MSB)MR19= 0xc0c, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
7221 17:16:48.226027 CH1 RK1: MR19=C0C, MR18=6452
7222 17:16:48.232392 CH1_RK1: MR19=0xC0C, MR18=0x6452, DQSOSC=397, MR23=63, INC=374, DEC=249
7223 17:16:48.235990 [RxdqsGatingPostProcess] freq 400
7224 17:16:48.242242 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7225 17:16:48.245954 best DQS0 dly(2T, 0.5T) = (0, 10)
7226 17:16:48.249027 best DQS1 dly(2T, 0.5T) = (0, 10)
7227 17:16:48.252403 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7228 17:16:48.255564 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7229 17:16:48.256000 best DQS0 dly(2T, 0.5T) = (0, 10)
7230 17:16:48.258700 best DQS1 dly(2T, 0.5T) = (0, 10)
7231 17:16:48.262420 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7232 17:16:48.265592 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7233 17:16:48.268827 Pre-setting of DQS Precalculation
7234 17:16:48.275411 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7235 17:16:48.282509 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7236 17:16:48.288704 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7237 17:16:48.289348
7238 17:16:48.289718
7239 17:16:48.292207 [Calibration Summary] 800 Mbps
7240 17:16:48.292675 CH 0, Rank 0
7241 17:16:48.295178 SW Impedance : PASS
7242 17:16:48.299057 DUTY Scan : NO K
7243 17:16:48.299620 ZQ Calibration : PASS
7244 17:16:48.301800 Jitter Meter : NO K
7245 17:16:48.304960 CBT Training : PASS
7246 17:16:48.305464 Write leveling : PASS
7247 17:16:48.308842 RX DQS gating : PASS
7248 17:16:48.312361 RX DQ/DQS(RDDQC) : PASS
7249 17:16:48.312917 TX DQ/DQS : PASS
7250 17:16:48.315064 RX DATLAT : PASS
7251 17:16:48.318493 RX DQ/DQS(Engine): PASS
7252 17:16:48.318941 TX OE : NO K
7253 17:16:48.321595 All Pass.
7254 17:16:48.322041
7255 17:16:48.322487 CH 0, Rank 1
7256 17:16:48.325177 SW Impedance : PASS
7257 17:16:48.325781 DUTY Scan : NO K
7258 17:16:48.328365 ZQ Calibration : PASS
7259 17:16:48.331663 Jitter Meter : NO K
7260 17:16:48.332114 CBT Training : PASS
7261 17:16:48.335036 Write leveling : NO K
7262 17:16:48.337889 RX DQS gating : PASS
7263 17:16:48.338339 RX DQ/DQS(RDDQC) : PASS
7264 17:16:48.341300 TX DQ/DQS : PASS
7265 17:16:48.341789 RX DATLAT : PASS
7266 17:16:48.345500
7267 17:16:48.346053 RX DQ/DQS(Engine): PASS
7268 17:16:48.347806 TX OE : NO K
7269 17:16:48.348257 All Pass.
7270 17:16:48.348738
7271 17:16:48.349165 CH 1, Rank 0
7272 17:16:48.351805
7273 17:16:48.352252 SW Impedance : PASS
7274 17:16:48.354683 DUTY Scan : NO K
7275 17:16:48.355150 ZQ Calibration : PASS
7276 17:16:48.358339 Jitter Meter : NO K
7277 17:16:48.361183 CBT Training : PASS
7278 17:16:48.361674 Write leveling : PASS
7279 17:16:48.364389 RX DQS gating : PASS
7280 17:16:48.368225 RX DQ/DQS(RDDQC) : PASS
7281 17:16:48.368672 TX DQ/DQS : PASS
7282 17:16:48.371136 RX DATLAT : PASS
7283 17:16:48.374664 RX DQ/DQS(Engine): PASS
7284 17:16:48.375140 TX OE : NO K
7285 17:16:48.378173 All Pass.
7286 17:16:48.378643
7287 17:16:48.379090 CH 1, Rank 1
7288 17:16:48.381164 SW Impedance : PASS
7289 17:16:48.381665 DUTY Scan : NO K
7290 17:16:48.384584 ZQ Calibration : PASS
7291 17:16:48.387744 Jitter Meter : NO K
7292 17:16:48.388192 CBT Training : PASS
7293 17:16:48.391140 Write leveling : NO K
7294 17:16:48.394676 RX DQS gating : PASS
7295 17:16:48.395125 RX DQ/DQS(RDDQC) : PASS
7296 17:16:48.397467 TX DQ/DQS : PASS
7297 17:16:48.401178 RX DATLAT : PASS
7298 17:16:48.401665 RX DQ/DQS(Engine): PASS
7299 17:16:48.404292 TX OE : NO K
7300 17:16:48.404742 All Pass.
7301 17:16:48.405221
7302 17:16:48.407534 DramC Write-DBI off
7303 17:16:48.410958 PER_BANK_REFRESH: Hybrid Mode
7304 17:16:48.411423 TX_TRACKING: ON
7305 17:16:48.421000 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7306 17:16:48.424029 [FAST_K] Save calibration result to emmc
7307 17:16:48.427469 dramc_set_vcore_voltage set vcore to 725000
7308 17:16:48.430620 Read voltage for 1600, 0
7309 17:16:48.431069 Vio18 = 0
7310 17:16:48.431529 Vcore = 725000
7311 17:16:48.434205 Vdram = 0
7312 17:16:48.434680 Vddq = 0
7313 17:16:48.435145 Vmddr = 0
7314 17:16:48.440669 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7315 17:16:48.444074 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7316 17:16:48.447473 MEM_TYPE=3, freq_sel=13
7317 17:16:48.450882 sv_algorithm_assistance_LP4_3733
7318 17:16:48.454141 ============ PULL DRAM RESETB DOWN ============
7319 17:16:48.457135 ========== PULL DRAM RESETB DOWN end =========
7320 17:16:48.463811 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7321 17:16:48.467418 ===================================
7322 17:16:48.467859 LPDDR4 DRAM CONFIGURATION
7323 17:16:48.470464 ===================================
7324 17:16:48.473927 EX_ROW_EN[0] = 0x0
7325 17:16:48.477064 EX_ROW_EN[1] = 0x0
7326 17:16:48.477530 LP4Y_EN = 0x0
7327 17:16:48.480364 WORK_FSP = 0x1
7328 17:16:48.480853 WL = 0x5
7329 17:16:48.483799 RL = 0x5
7330 17:16:48.484233 BL = 0x2
7331 17:16:48.487112 RPST = 0x0
7332 17:16:48.487659 RD_PRE = 0x0
7333 17:16:48.490283 WR_PRE = 0x1
7334 17:16:48.490740 WR_PST = 0x1
7335 17:16:48.493569 DBI_WR = 0x0
7336 17:16:48.494000 DBI_RD = 0x0
7337 17:16:48.497090 OTF = 0x1
7338 17:16:48.500794 ===================================
7339 17:16:48.503640 ===================================
7340 17:16:48.504075 ANA top config
7341 17:16:48.506710 ===================================
7342 17:16:48.510160 DLL_ASYNC_EN = 0
7343 17:16:48.513442 ALL_SLAVE_EN = 0
7344 17:16:48.516909 NEW_RANK_MODE = 1
7345 17:16:48.517374 DLL_IDLE_MODE = 1
7346 17:16:48.520025 LP45_APHY_COMB_EN = 1
7347 17:16:48.523808 TX_ODT_DIS = 0
7348 17:16:48.526691 NEW_8X_MODE = 1
7349 17:16:48.529925 ===================================
7350 17:16:48.533382 ===================================
7351 17:16:48.536603 data_rate = 3200
7352 17:16:48.537029 CKR = 1
7353 17:16:48.540092 DQ_P2S_RATIO = 8
7354 17:16:48.543543 ===================================
7355 17:16:48.546358 CA_P2S_RATIO = 8
7356 17:16:48.549722 DQ_CA_OPEN = 0
7357 17:16:48.553239 DQ_SEMI_OPEN = 0
7358 17:16:48.556791 CA_SEMI_OPEN = 0
7359 17:16:48.557316 CA_FULL_RATE = 0
7360 17:16:48.560032 DQ_CKDIV4_EN = 0
7361 17:16:48.563369 CA_CKDIV4_EN = 0
7362 17:16:48.566782 CA_PREDIV_EN = 0
7363 17:16:48.569561 PH8_DLY = 12
7364 17:16:48.573357 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7365 17:16:48.573788 DQ_AAMCK_DIV = 4
7366 17:16:48.576213 CA_AAMCK_DIV = 4
7367 17:16:48.580148 CA_ADMCK_DIV = 4
7368 17:16:48.583019 DQ_TRACK_CA_EN = 0
7369 17:16:48.586731 CA_PICK = 1600
7370 17:16:48.589728 CA_MCKIO = 1600
7371 17:16:48.593191 MCKIO_SEMI = 0
7372 17:16:48.593671 PLL_FREQ = 3068
7373 17:16:48.596517 DQ_UI_PI_RATIO = 32
7374 17:16:48.599514 CA_UI_PI_RATIO = 0
7375 17:16:48.602739 ===================================
7376 17:16:48.605972 ===================================
7377 17:16:48.609454 memory_type:LPDDR4
7378 17:16:48.612822 GP_NUM : 10
7379 17:16:48.613385 SRAM_EN : 1
7380 17:16:48.616174 MD32_EN : 0
7381 17:16:48.619747 ===================================
7382 17:16:48.620292 [ANA_INIT] >>>>>>>>>>>>>>
7383 17:16:48.622622 <<<<<< [CONFIGURE PHASE]: ANA_TX
7384 17:16:48.626326 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7385 17:16:48.629586 ===================================
7386 17:16:48.632581 data_rate = 3200,PCW = 0X7600
7387 17:16:48.636478 ===================================
7388 17:16:48.639149 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7389 17:16:48.646195 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7390 17:16:48.652532 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7391 17:16:48.656025 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7392 17:16:48.659289 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7393 17:16:48.662331 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7394 17:16:48.666060 [ANA_INIT] flow start
7395 17:16:48.666587 [ANA_INIT] PLL >>>>>>>>
7396 17:16:48.668771 [ANA_INIT] PLL <<<<<<<<
7397 17:16:48.672862 [ANA_INIT] MIDPI >>>>>>>>
7398 17:16:48.673439 [ANA_INIT] MIDPI <<<<<<<<
7399 17:16:48.675457 [ANA_INIT] DLL >>>>>>>>
7400 17:16:48.679236 [ANA_INIT] DLL <<<<<<<<
7401 17:16:48.679765 [ANA_INIT] flow end
7402 17:16:48.685707 ============ LP4 DIFF to SE enter ============
7403 17:16:48.688869 ============ LP4 DIFF to SE exit ============
7404 17:16:48.692066 [ANA_INIT] <<<<<<<<<<<<<
7405 17:16:48.695138 [Flow] Enable top DCM control >>>>>
7406 17:16:48.698482 [Flow] Enable top DCM control <<<<<
7407 17:16:48.702154 Enable DLL master slave shuffle
7408 17:16:48.705015 ==============================================================
7409 17:16:48.708461 Gating Mode config
7410 17:16:48.711577 ==============================================================
7411 17:16:48.715047 Config description:
7412 17:16:48.725290 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7413 17:16:48.731560 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7414 17:16:48.734787 SELPH_MODE 0: By rank 1: By Phase
7415 17:16:48.741269 ==============================================================
7416 17:16:48.744900 GAT_TRACK_EN = 1
7417 17:16:48.748014 RX_GATING_MODE = 2
7418 17:16:48.751466 RX_GATING_TRACK_MODE = 2
7419 17:16:48.754456 SELPH_MODE = 1
7420 17:16:48.757932 PICG_EARLY_EN = 1
7421 17:16:48.761429 VALID_LAT_VALUE = 1
7422 17:16:48.764654 ==============================================================
7423 17:16:48.767830 Enter into Gating configuration >>>>
7424 17:16:48.771538 Exit from Gating configuration <<<<
7425 17:16:48.774562 Enter into DVFS_PRE_config >>>>>
7426 17:16:48.787837 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7427 17:16:48.788269 Exit from DVFS_PRE_config <<<<<
7428 17:16:48.790906 Enter into PICG configuration >>>>
7429 17:16:48.794381 Exit from PICG configuration <<<<
7430 17:16:48.797675 [RX_INPUT] configuration >>>>>
7431 17:16:48.800708 [RX_INPUT] configuration <<<<<
7432 17:16:48.807260 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7433 17:16:48.811070 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7434 17:16:48.817750 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7435 17:16:48.824601 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7436 17:16:48.831077 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7437 17:16:48.837379 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7438 17:16:48.840522 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7439 17:16:48.844156 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7440 17:16:48.847103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7441 17:16:48.854269 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7442 17:16:48.857182 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7443 17:16:48.860858 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7444 17:16:48.863958 ===================================
7445 17:16:48.867149 LPDDR4 DRAM CONFIGURATION
7446 17:16:48.870909 ===================================
7447 17:16:48.873642 EX_ROW_EN[0] = 0x0
7448 17:16:48.874065 EX_ROW_EN[1] = 0x0
7449 17:16:48.877251 LP4Y_EN = 0x0
7450 17:16:48.877861 WORK_FSP = 0x1
7451 17:16:48.880656 WL = 0x5
7452 17:16:48.881228 RL = 0x5
7453 17:16:48.884195 BL = 0x2
7454 17:16:48.884730 RPST = 0x0
7455 17:16:48.886947 RD_PRE = 0x0
7456 17:16:48.887372 WR_PRE = 0x1
7457 17:16:48.890126 WR_PST = 0x1
7458 17:16:48.890571 DBI_WR = 0x0
7459 17:16:48.893650 DBI_RD = 0x0
7460 17:16:48.894078 OTF = 0x1
7461 17:16:48.896829 ===================================
7462 17:16:48.903609 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7463 17:16:48.906632 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7464 17:16:48.910059 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7465 17:16:48.913668 ===================================
7466 17:16:48.917033 LPDDR4 DRAM CONFIGURATION
7467 17:16:48.920069 ===================================
7468 17:16:48.920505 EX_ROW_EN[0] = 0x10
7469 17:16:48.923263
7470 17:16:48.923748 EX_ROW_EN[1] = 0x0
7471 17:16:48.927033 LP4Y_EN = 0x0
7472 17:16:48.927529 WORK_FSP = 0x1
7473 17:16:48.930175 WL = 0x5
7474 17:16:48.930760 RL = 0x5
7475 17:16:48.933212 BL = 0x2
7476 17:16:48.933716 RPST = 0x0
7477 17:16:48.936468 RD_PRE = 0x0
7478 17:16:48.936895 WR_PRE = 0x1
7479 17:16:48.939800 WR_PST = 0x1
7480 17:16:48.940226 DBI_WR = 0x0
7481 17:16:48.943116 DBI_RD = 0x0
7482 17:16:48.943541 OTF = 0x1
7483 17:16:48.946696 ===================================
7484 17:16:48.952971 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7485 17:16:48.953526 ==
7486 17:16:48.956394 Dram Type= 6, Freq= 0, CH_0, rank 0
7487 17:16:48.962851 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7488 17:16:48.963304 ==
7489 17:16:48.963742 [Duty_Offset_Calibration]
7490 17:16:48.966326 B0:1 B1:-1 CA:0
7491 17:16:48.966773
7492 17:16:48.969587 [DutyScan_Calibration_Flow] k_type=0
7493 17:16:48.978822
7494 17:16:48.979268 ==CLK 0==
7495 17:16:48.982408 Final CLK duty delay cell = 0
7496 17:16:48.985426 [0] MAX Duty = 5125%(X100), DQS PI = 20
7497 17:16:48.989003 [0] MIN Duty = 4907%(X100), DQS PI = 8
7498 17:16:48.989479 [0] AVG Duty = 5016%(X100)
7499 17:16:48.991919
7500 17:16:48.992465 CH0 CLK Duty spec in!! Max-Min= 218%
7501 17:16:48.995550
7502 17:16:48.999095 [DutyScan_Calibration_Flow] ====Done====
7503 17:16:48.999532
7504 17:16:49.001999 [DutyScan_Calibration_Flow] k_type=1
7505 17:16:49.018366
7506 17:16:49.018797 ==DQS 0 ==
7507 17:16:49.021250 Final DQS duty delay cell = -4
7508 17:16:49.024650 [-4] MAX Duty = 5000%(X100), DQS PI = 18
7509 17:16:49.028270 [-4] MIN Duty = 4844%(X100), DQS PI = 58
7510 17:16:49.031437 [-4] AVG Duty = 4922%(X100)
7511 17:16:49.031874
7512 17:16:49.032216 ==DQS 1 ==
7513 17:16:49.034922 Final DQS duty delay cell = 0
7514 17:16:49.038098 [0] MAX Duty = 5156%(X100), DQS PI = 2
7515 17:16:49.041408 [0] MIN Duty = 5031%(X100), DQS PI = 20
7516 17:16:49.044352 [0] AVG Duty = 5093%(X100)
7517 17:16:49.044812
7518 17:16:49.048251 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7519 17:16:49.048780
7520 17:16:49.051211 CH0 DQS 1 Duty spec in!! Max-Min= 125%
7521 17:16:49.054396 [DutyScan_Calibration_Flow] ====Done====
7522 17:16:49.054832
7523 17:16:49.057847 [DutyScan_Calibration_Flow] k_type=3
7524 17:16:49.075543
7525 17:16:49.075978 ==DQM 0 ==
7526 17:16:49.079453 Final DQM duty delay cell = 0
7527 17:16:49.082295 [0] MAX Duty = 5124%(X100), DQS PI = 22
7528 17:16:49.085744 [0] MIN Duty = 4907%(X100), DQS PI = 10
7529 17:16:49.088684 [0] AVG Duty = 5015%(X100)
7530 17:16:49.089115
7531 17:16:49.089496 ==DQM 1 ==
7532 17:16:49.092316 Final DQM duty delay cell = 0
7533 17:16:49.095334 [0] MAX Duty = 5031%(X100), DQS PI = 10
7534 17:16:49.099155 [0] MIN Duty = 4813%(X100), DQS PI = 20
7535 17:16:49.102121 [0] AVG Duty = 4922%(X100)
7536 17:16:49.102651
7537 17:16:49.105773 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7538 17:16:49.106211
7539 17:16:49.108662 CH0 DQM 1 Duty spec in!! Max-Min= 218%
7540 17:16:49.112204 [DutyScan_Calibration_Flow] ====Done====
7541 17:16:49.112760
7542 17:16:49.115120 [DutyScan_Calibration_Flow] k_type=2
7543 17:16:49.132139
7544 17:16:49.132672 ==DQ 0 ==
7545 17:16:49.135676 Final DQ duty delay cell = -4
7546 17:16:49.138550 [-4] MAX Duty = 5031%(X100), DQS PI = 24
7547 17:16:49.141990 [-4] MIN Duty = 4876%(X100), DQS PI = 54
7548 17:16:49.145430 [-4] AVG Duty = 4953%(X100)
7549 17:16:49.145861
7550 17:16:49.146226 ==DQ 1 ==
7551 17:16:49.148690 Final DQ duty delay cell = 0
7552 17:16:49.151740 [0] MAX Duty = 5125%(X100), DQS PI = 4
7553 17:16:49.155204 [0] MIN Duty = 4969%(X100), DQS PI = 38
7554 17:16:49.158707 [0] AVG Duty = 5047%(X100)
7555 17:16:49.159138
7556 17:16:49.161633 CH0 DQ 0 Duty spec in!! Max-Min= 155%
7557 17:16:49.162079
7558 17:16:49.165261 CH0 DQ 1 Duty spec in!! Max-Min= 156%
7559 17:16:49.168110 [DutyScan_Calibration_Flow] ====Done====
7560 17:16:49.168542 ==
7561 17:16:49.171522 Dram Type= 6, Freq= 0, CH_1, rank 0
7562 17:16:49.174965 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7563 17:16:49.175406 ==
7564 17:16:49.178226 [Duty_Offset_Calibration]
7565 17:16:49.178695 B0:-1 B1:1 CA:2
7566 17:16:49.179044
7567 17:16:49.181580 [DutyScan_Calibration_Flow] k_type=0
7568 17:16:49.192947
7569 17:16:49.193678 ==CLK 0==
7570 17:16:49.195804 Final CLK duty delay cell = 0
7571 17:16:49.199644 [0] MAX Duty = 5187%(X100), DQS PI = 22
7572 17:16:49.202395 [0] MIN Duty = 4969%(X100), DQS PI = 0
7573 17:16:49.202866 [0] AVG Duty = 5078%(X100)
7574 17:16:49.205722
7575 17:16:49.206159 CH1 CLK Duty spec in!! Max-Min= 218%
7576 17:16:49.208979
7577 17:16:49.212354 [DutyScan_Calibration_Flow] ====Done====
7578 17:16:49.212823
7579 17:16:49.215607 [DutyScan_Calibration_Flow] k_type=1
7580 17:16:49.231843
7581 17:16:49.231928 ==DQS 0 ==
7582 17:16:49.235344 Final DQS duty delay cell = 0
7583 17:16:49.238507 [0] MAX Duty = 5125%(X100), DQS PI = 20
7584 17:16:49.241664 [0] MIN Duty = 4938%(X100), DQS PI = 8
7585 17:16:49.241761 [0] AVG Duty = 5031%(X100)
7586 17:16:49.245243
7587 17:16:49.245356
7588 17:16:49.245441 ==DQS 1 ==
7589 17:16:49.248266 Final DQS duty delay cell = 0
7590 17:16:49.251691 [0] MAX Duty = 5093%(X100), DQS PI = 12
7591 17:16:49.254982 [0] MIN Duty = 4969%(X100), DQS PI = 56
7592 17:16:49.258534 [0] AVG Duty = 5031%(X100)
7593 17:16:49.258662
7594 17:16:49.262011 CH1 DQS 0 Duty spec in!! Max-Min= 187%
7595 17:16:49.262154
7596 17:16:49.264950 CH1 DQS 1 Duty spec in!! Max-Min= 124%
7597 17:16:49.268596 [DutyScan_Calibration_Flow] ====Done====
7598 17:16:49.268756
7599 17:16:49.271507 [DutyScan_Calibration_Flow] k_type=3
7600 17:16:49.287791
7601 17:16:49.287877 ==DQM 0 ==
7602 17:16:49.291294 Final DQM duty delay cell = -4
7603 17:16:49.294750 [-4] MAX Duty = 5031%(X100), DQS PI = 18
7604 17:16:49.298018 [-4] MIN Duty = 4782%(X100), DQS PI = 8
7605 17:16:49.301117 [-4] AVG Duty = 4906%(X100)
7606 17:16:49.301229
7607 17:16:49.301336 ==DQM 1 ==
7608 17:16:49.304487 Final DQM duty delay cell = 0
7609 17:16:49.307548 [0] MAX Duty = 5156%(X100), DQS PI = 0
7610 17:16:49.310753 [0] MIN Duty = 4938%(X100), DQS PI = 34
7611 17:16:49.314153 [0] AVG Duty = 5047%(X100)
7612 17:16:49.314267
7613 17:16:49.317666 CH1 DQM 0 Duty spec in!! Max-Min= 249%
7614 17:16:49.317777
7615 17:16:49.320754 CH1 DQM 1 Duty spec in!! Max-Min= 218%
7616 17:16:49.324098 [DutyScan_Calibration_Flow] ====Done====
7617 17:16:49.324206
7618 17:16:49.327627 [DutyScan_Calibration_Flow] k_type=2
7619 17:16:49.345209
7620 17:16:49.345334 ==DQ 0 ==
7621 17:16:49.348235 Final DQ duty delay cell = 0
7622 17:16:49.351670 [0] MAX Duty = 5156%(X100), DQS PI = 30
7623 17:16:49.355176 [0] MIN Duty = 4938%(X100), DQS PI = 8
7624 17:16:49.355263 [0] AVG Duty = 5047%(X100)
7625 17:16:49.355330
7626 17:16:49.358108
7627 17:16:49.358203 ==DQ 1 ==
7628 17:16:49.361560 Final DQ duty delay cell = 0
7629 17:16:49.364641 [0] MAX Duty = 5156%(X100), DQS PI = 8
7630 17:16:49.368319 [0] MIN Duty = 4969%(X100), DQS PI = 56
7631 17:16:49.368424 [0] AVG Duty = 5062%(X100)
7632 17:16:49.368494
7633 17:16:49.371522 CH1 DQ 0 Duty spec in!! Max-Min= 218%
7634 17:16:49.375034
7635 17:16:49.375130
7636 17:16:49.378282 CH1 DQ 1 Duty spec in!! Max-Min= 187%
7637 17:16:49.381455 [DutyScan_Calibration_Flow] ====Done====
7638 17:16:49.384771 nWR fixed to 30
7639 17:16:49.384867 [ModeRegInit_LP4] CH0 RK0
7640 17:16:49.387795 [ModeRegInit_LP4] CH0 RK1
7641 17:16:49.391567 [ModeRegInit_LP4] CH1 RK0
7642 17:16:49.394479 [ModeRegInit_LP4] CH1 RK1
7643 17:16:49.394566 match AC timing 5
7644 17:16:49.398235 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7645 17:16:49.401590
7646 17:16:49.404961 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7647 17:16:49.408046 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7648 17:16:49.414530 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7649 17:16:49.417732 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7650 17:16:49.417868 [MiockJmeterHQA]
7651 17:16:49.417935
7652 17:16:49.421221 [DramcMiockJmeter] u1RxGatingPI = 0
7653 17:16:49.424517 0 : 4252, 4027
7654 17:16:49.424605 4 : 4252, 4027
7655 17:16:49.427684 8 : 4253, 4027
7656 17:16:49.427862 12 : 4252, 4027
7657 17:16:49.427949 16 : 4252, 4027
7658 17:16:49.431194 20 : 4252, 4027
7659 17:16:49.431351 24 : 4254, 4029
7660 17:16:49.434130 28 : 4363, 4137
7661 17:16:49.434277 32 : 4252, 4027
7662 17:16:49.437760 36 : 4252, 4027
7663 17:16:49.437870 40 : 4253, 4027
7664 17:16:49.440948 44 : 4254, 4029
7665 17:16:49.441140 48 : 4253, 4026
7666 17:16:49.441239 52 : 4363, 4138
7667 17:16:49.444446 56 : 4363, 4137
7668 17:16:49.444616 60 : 4252, 4027
7669 17:16:49.447420 64 : 4252, 4027
7670 17:16:49.447540 68 : 4252, 4027
7671 17:16:49.450765 72 : 4255, 4029
7672 17:16:49.450927 76 : 4254, 4029
7673 17:16:49.453866 80 : 4360, 4138
7674 17:16:49.454020 84 : 4250, 4027
7675 17:16:49.454125 88 : 4250, 4027
7676 17:16:49.457235 92 : 4250, 713
7677 17:16:49.457391 96 : 4361, 0
7678 17:16:49.460703 100 : 4250, 0
7679 17:16:49.460835 104 : 4250, 0
7680 17:16:49.460936 108 : 4250, 0
7681 17:16:49.464680 112 : 4252, 0
7682 17:16:49.464894 116 : 4360, 0
7683 17:16:49.467300 120 : 4361, 0
7684 17:16:49.467515 124 : 4363, 0
7685 17:16:49.467648 128 : 4250, 0
7686 17:16:49.470496 132 : 4360, 0
7687 17:16:49.470650 136 : 4361, 0
7688 17:16:49.473775 140 : 4250, 0
7689 17:16:49.473936 144 : 4250, 0
7690 17:16:49.474064 148 : 4250, 0
7691 17:16:49.477120 152 : 4252, 0
7692 17:16:49.477282 156 : 4250, 0
7693 17:16:49.480631 160 : 4250, 0
7694 17:16:49.480916 164 : 4253, 0
7695 17:16:49.481081 168 : 4360, 0
7696 17:16:49.483705 172 : 4361, 0
7697 17:16:49.483937 176 : 4363, 0
7698 17:16:49.484108 180 : 4361, 0
7699 17:16:49.487131
7700 17:16:49.487441 184 : 4250, 0
7701 17:16:49.487627 188 : 4250, 0
7702 17:16:49.490791 192 : 4250, 0
7703 17:16:49.491145 196 : 4250, 0
7704 17:16:49.491375 200 : 4250, 0
7705 17:16:49.493973 204 : 4252, 0
7706 17:16:49.494375 208 : 4250, 0
7707 17:16:49.497104 212 : 4250, 0
7708 17:16:49.497463 216 : 4253, 0
7709 17:16:49.497732 220 : 4250, 0
7710 17:16:49.500735 224 : 4361, 194
7711 17:16:49.501181 228 : 4250, 2944
7712 17:16:49.503695 232 : 4250, 4027
7713 17:16:49.504143 236 : 4250, 4026
7714 17:16:49.507452 240 : 4250, 4027
7715 17:16:49.507950 244 : 4360, 4138
7716 17:16:49.510536 248 : 4249, 4027
7717 17:16:49.510985 252 : 4361, 4137
7718 17:16:49.513474 256 : 4361, 4137
7719 17:16:49.513932 260 : 4250, 4027
7720 17:16:49.516973 264 : 4249, 4027
7721 17:16:49.517474 268 : 4363, 4140
7722 17:16:49.520264 272 : 4250, 4026
7723 17:16:49.520668 276 : 4250, 4027
7724 17:16:49.521116 280 : 4250, 4027
7725 17:16:49.523378 284 : 4249, 4027
7726 17:16:49.523831 288 : 4250, 4026
7727 17:16:49.526484 292 : 4250, 4027
7728 17:16:49.526931 296 : 4360, 4138
7729 17:16:49.530054 300 : 4250, 4027
7730 17:16:49.530568 304 : 4250, 4026
7731 17:16:49.533621 308 : 4361, 4137
7732 17:16:49.534072 312 : 4250, 4027
7733 17:16:49.536612 316 : 4250, 4027
7734 17:16:49.537080 320 : 4363, 4140
7735 17:16:49.539927 324 : 4250, 4026
7736 17:16:49.540454 328 : 4250, 4027
7737 17:16:49.543405 332 : 4249, 4027
7738 17:16:49.543898 336 : 4252, 3787
7739 17:16:49.546221 340 : 4250, 2094
7740 17:16:49.546678
7741 17:16:49.547146 MIOCK jitter meter ch=0
7742 17:16:49.547564
7743 17:16:49.549766 1T = (340-92) = 248 dly cells
7744 17:16:49.556192 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 262/100 ps
7745 17:16:49.556636 ==
7746 17:16:49.559836 Dram Type= 6, Freq= 0, CH_0, rank 0
7747 17:16:49.562950 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7748 17:16:49.563390 ==
7749 17:16:49.570094 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7750 17:16:49.573121 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7751 17:16:49.576016 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7752 17:16:49.582507 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7753 17:16:49.592508 [CA 0] Center 43 (12~74) winsize 63
7754 17:16:49.595882 [CA 1] Center 42 (12~73) winsize 62
7755 17:16:49.599023 [CA 2] Center 38 (9~68) winsize 60
7756 17:16:49.602098 [CA 3] Center 38 (8~68) winsize 61
7757 17:16:49.605411 [CA 4] Center 36 (7~66) winsize 60
7758 17:16:49.609350 [CA 5] Center 35 (6~65) winsize 60
7759 17:16:49.609846
7760 17:16:49.612525 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7761 17:16:49.613011
7762 17:16:49.615817 [CATrainingPosCal] consider 1 rank data
7763 17:16:49.619301 u2DelayCellTimex100 = 262/100 ps
7764 17:16:49.622129 CA0 delay=43 (12~74),Diff = 8 PI (29 cell)
7765 17:16:49.628826 CA1 delay=42 (12~73),Diff = 7 PI (26 cell)
7766 17:16:49.632352 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7767 17:16:49.635755 CA3 delay=38 (8~68),Diff = 3 PI (11 cell)
7768 17:16:49.638933 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7769 17:16:49.641939 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7770 17:16:49.642379
7771 17:16:49.645350 CA PerBit enable=1, Macro0, CA PI delay=35
7772 17:16:49.645817
7773 17:16:49.648545 [CBTSetCACLKResult] CA Dly = 35
7774 17:16:49.651867 CS Dly: 12 (0~43)
7775 17:16:49.655178 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7776 17:16:49.658762 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7777 17:16:49.659205 ==
7778 17:16:49.662069 Dram Type= 6, Freq= 0, CH_0, rank 1
7779 17:16:49.668478 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7780 17:16:49.668923 ==
7781 17:16:49.671932 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7782 17:16:49.678132 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7783 17:16:49.681846 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7784 17:16:49.688440 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7785 17:16:49.696068 [CA 0] Center 43 (13~74) winsize 62
7786 17:16:49.699093 [CA 1] Center 44 (14~74) winsize 61
7787 17:16:49.702476 [CA 2] Center 38 (9~68) winsize 60
7788 17:16:49.706037 [CA 3] Center 38 (9~68) winsize 60
7789 17:16:49.709194 [CA 4] Center 36 (7~66) winsize 60
7790 17:16:49.712612 [CA 5] Center 36 (6~66) winsize 61
7791 17:16:49.713186
7792 17:16:49.715983 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7793 17:16:49.716425
7794 17:16:49.719101 [CATrainingPosCal] consider 2 rank data
7795 17:16:49.722626 u2DelayCellTimex100 = 262/100 ps
7796 17:16:49.725743 CA0 delay=43 (13~74),Diff = 8 PI (29 cell)
7797 17:16:49.728986
7798 17:16:49.732476 CA1 delay=43 (14~73),Diff = 8 PI (29 cell)
7799 17:16:49.735766 CA2 delay=38 (9~68),Diff = 3 PI (11 cell)
7800 17:16:49.739385 CA3 delay=38 (9~68),Diff = 3 PI (11 cell)
7801 17:16:49.742568 CA4 delay=36 (7~66),Diff = 1 PI (3 cell)
7802 17:16:49.745740 CA5 delay=35 (6~65),Diff = 0 PI (0 cell)
7803 17:16:49.746293
7804 17:16:49.748913 CA PerBit enable=1, Macro0, CA PI delay=35
7805 17:16:49.749379
7806 17:16:49.752362 [CBTSetCACLKResult] CA Dly = 35
7807 17:16:49.755196 CS Dly: 12 (0~44)
7808 17:16:49.758964 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7809 17:16:49.762085 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7810 17:16:49.762531
7811 17:16:49.765514 ----->DramcWriteLeveling(PI) begin...
7812 17:16:49.765964 ==
7813 17:16:49.768546 Dram Type= 6, Freq= 0, CH_0, rank 0
7814 17:16:49.775000 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7815 17:16:49.775443 ==
7816 17:16:49.778540 Write leveling (Byte 0): 36 => 36
7817 17:16:49.782038 Write leveling (Byte 1): 25 => 25
7818 17:16:49.782480 DramcWriteLeveling(PI) end<-----
7819 17:16:49.784866
7820 17:16:49.785354 ==
7821 17:16:49.788690 Dram Type= 6, Freq= 0, CH_0, rank 0
7822 17:16:49.791887 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7823 17:16:49.792458 ==
7824 17:16:49.795082 [Gating] SW mode calibration
7825 17:16:49.801665 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7826 17:16:49.804854 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7827 17:16:49.808315
7828 17:16:49.811475 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7829 17:16:49.814509 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7830 17:16:49.818208 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7831 17:16:49.821460
7832 17:16:49.824406 1 4 12 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7833 17:16:49.827833 1 4 16 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7834 17:16:49.831375 1 4 20 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
7835 17:16:49.837880 1 4 24 | B1->B0 | 3232 3434 | 0 1 | (0 0) (1 1)
7836 17:16:49.841127 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7837 17:16:49.844433 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7838 17:16:49.851476 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7839 17:16:49.854129 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7840 17:16:49.857741 1 5 12 | B1->B0 | 3434 2c2c | 1 0 | (1 1) (0 1)
7841 17:16:49.860675
7842 17:16:49.864465 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7843 17:16:49.867881 1 5 20 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
7844 17:16:49.870875 1 5 24 | B1->B0 | 2929 2323 | 0 0 | (1 0) (0 0)
7845 17:16:49.877487 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7846 17:16:49.881052 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7847 17:16:49.884173 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7848 17:16:49.890530 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7849 17:16:49.893994 1 6 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
7850 17:16:49.897082 1 6 16 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
7851 17:16:49.903876 1 6 20 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
7852 17:16:49.907502 1 6 24 | B1->B0 | 4444 4646 | 0 0 | (0 0) (0 0)
7853 17:16:49.910597 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7854 17:16:49.917130 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7855 17:16:49.920832 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7856 17:16:49.923738 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7857 17:16:49.930532 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7858 17:16:49.934097 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7859 17:16:49.937436 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7860 17:16:49.943911 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7861 17:16:49.947013 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7862 17:16:49.950406 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7863 17:16:49.956810 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7864 17:16:49.960348 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7865 17:16:49.963679 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7866 17:16:49.970373 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7867 17:16:49.973505 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7868 17:16:49.976914 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7869 17:16:49.983329 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7870 17:16:49.986809 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7871 17:16:49.989756 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7872 17:16:49.996265 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7873 17:16:50.000037 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7874 17:16:50.003564 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7875 17:16:50.009663 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7876 17:16:50.010181 Total UI for P1: 0, mck2ui 16
7877 17:16:50.016246 best dqsien dly found for B0: ( 1, 9, 12)
7878 17:16:50.019630 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7879 17:16:50.023112 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7880 17:16:50.026151 Total UI for P1: 0, mck2ui 16
7881 17:16:50.029808 best dqsien dly found for B1: ( 1, 9, 22)
7882 17:16:50.032736 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
7883 17:16:50.036321 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
7884 17:16:50.036760
7885 17:16:50.042943 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
7886 17:16:50.046301 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
7887 17:16:50.046744 [Gating] SW calibration Done
7888 17:16:50.049577
7889 17:16:50.050162 ==
7890 17:16:50.053048 Dram Type= 6, Freq= 0, CH_0, rank 0
7891 17:16:50.056157 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7892 17:16:50.056663 ==
7893 17:16:50.057022 RX Vref Scan: 0
7894 17:16:50.057482
7895 17:16:50.059524 RX Vref 0 -> 0, step: 1
7896 17:16:50.060069
7897 17:16:50.062508 RX Delay 0 -> 252, step: 8
7898 17:16:50.065984 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
7899 17:16:50.069564 iDelay=200, Bit 1, Center 139 (88 ~ 191) 104
7900 17:16:50.072644 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
7901 17:16:50.076129
7902 17:16:50.079099 iDelay=200, Bit 3, Center 131 (80 ~ 183) 104
7903 17:16:50.082586 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
7904 17:16:50.085747 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
7905 17:16:50.089030 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
7906 17:16:50.092377 iDelay=200, Bit 7, Center 147 (96 ~ 199) 104
7907 17:16:50.099237 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
7908 17:16:50.102674 iDelay=200, Bit 9, Center 115 (64 ~ 167) 104
7909 17:16:50.105830 iDelay=200, Bit 10, Center 127 (72 ~ 183) 112
7910 17:16:50.108904 iDelay=200, Bit 11, Center 119 (64 ~ 175) 112
7911 17:16:50.115539 iDelay=200, Bit 12, Center 131 (80 ~ 183) 104
7912 17:16:50.119007 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
7913 17:16:50.122209 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
7914 17:16:50.125799 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
7915 17:16:50.126240 ==
7916 17:16:50.128753 Dram Type= 6, Freq= 0, CH_0, rank 0
7917 17:16:50.135512 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7918 17:16:50.135600 ==
7919 17:16:50.135668 DQS Delay:
7920 17:16:50.135730 DQS0 = 0, DQS1 = 0
7921 17:16:50.138305 DQM Delay:
7922 17:16:50.138395 DQM0 = 134, DQM1 = 127
7923 17:16:50.141751 DQ Delay:
7924 17:16:50.144848 DQ0 =131, DQ1 =139, DQ2 =131, DQ3 =131
7925 17:16:50.148291 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =147
7926 17:16:50.151549 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =119
7927 17:16:50.155046 DQ12 =131, DQ13 =135, DQ14 =139, DQ15 =131
7928 17:16:50.155132
7929 17:16:50.155200
7930 17:16:50.155269 ==
7931 17:16:50.157971 Dram Type= 6, Freq= 0, CH_0, rank 0
7932 17:16:50.161407 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7933 17:16:50.165031 ==
7934 17:16:50.165110
7935 17:16:50.165185
7936 17:16:50.165248 TX Vref Scan disable
7937 17:16:50.167951 == TX Byte 0 ==
7938 17:16:50.171681 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
7939 17:16:50.174688 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7940 17:16:50.177833 == TX Byte 1 ==
7941 17:16:50.181130 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
7942 17:16:50.184714 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7943 17:16:50.188227 ==
7944 17:16:50.191325 Dram Type= 6, Freq= 0, CH_0, rank 0
7945 17:16:50.194422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7946 17:16:50.194503 ==
7947 17:16:50.207644
7948 17:16:50.211027 TX Vref early break, caculate TX vref
7949 17:16:50.214727 TX Vref=16, minBit 3, minWin=22, winSum=366
7950 17:16:50.217684 TX Vref=18, minBit 4, minWin=22, winSum=375
7951 17:16:50.220799 TX Vref=20, minBit 0, minWin=23, winSum=388
7952 17:16:50.224505 TX Vref=22, minBit 0, minWin=24, winSum=400
7953 17:16:50.227616 TX Vref=24, minBit 0, minWin=25, winSum=409
7954 17:16:50.234130 TX Vref=26, minBit 1, minWin=25, winSum=416
7955 17:16:50.237660 TX Vref=28, minBit 0, minWin=25, winSum=419
7956 17:16:50.241139 TX Vref=30, minBit 4, minWin=24, winSum=408
7957 17:16:50.244116 TX Vref=32, minBit 7, minWin=23, winSum=400
7958 17:16:50.247745 TX Vref=34, minBit 0, minWin=23, winSum=387
7959 17:16:50.254042 [TxChooseVref] Worse bit 0, Min win 25, Win sum 419, Final Vref 28
7960 17:16:50.254129
7961 17:16:50.257513 Final TX Range 0 Vref 28
7962 17:16:50.257599
7963 17:16:50.257665 ==
7964 17:16:50.260521 Dram Type= 6, Freq= 0, CH_0, rank 0
7965 17:16:50.264023 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7966 17:16:50.264108 ==
7967 17:16:50.264175
7968 17:16:50.264236
7969 17:16:50.267463 TX Vref Scan disable
7970 17:16:50.274083 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
7971 17:16:50.274168 == TX Byte 0 ==
7972 17:16:50.277030 u2DelayCellOfst[0]=18 cells (5 PI)
7973 17:16:50.280514 u2DelayCellOfst[1]=22 cells (6 PI)
7974 17:16:50.283864 u2DelayCellOfst[2]=14 cells (4 PI)
7975 17:16:50.286990 u2DelayCellOfst[3]=14 cells (4 PI)
7976 17:16:50.290686 u2DelayCellOfst[4]=11 cells (3 PI)
7977 17:16:50.293702 u2DelayCellOfst[5]=0 cells (0 PI)
7978 17:16:50.297192 u2DelayCellOfst[6]=22 cells (6 PI)
7979 17:16:50.300357 u2DelayCellOfst[7]=22 cells (6 PI)
7980 17:16:50.303922 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
7981 17:16:50.307180 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
7982 17:16:50.310161 == TX Byte 1 ==
7983 17:16:50.313787 u2DelayCellOfst[8]=0 cells (0 PI)
7984 17:16:50.316848 u2DelayCellOfst[9]=3 cells (1 PI)
7985 17:16:50.316927 u2DelayCellOfst[10]=7 cells (2 PI)
7986 17:16:50.320273 u2DelayCellOfst[11]=0 cells (0 PI)
7987 17:16:50.323322 u2DelayCellOfst[12]=14 cells (4 PI)
7988 17:16:50.327052 u2DelayCellOfst[13]=14 cells (4 PI)
7989 17:16:50.330158 u2DelayCellOfst[14]=14 cells (4 PI)
7990 17:16:50.333205 u2DelayCellOfst[15]=14 cells (4 PI)
7991 17:16:50.339920 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
7992 17:16:50.343120 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
7993 17:16:50.343205 DramC Write-DBI on
7994 17:16:50.343271 ==
7995 17:16:50.346442 Dram Type= 6, Freq= 0, CH_0, rank 0
7996 17:16:50.353363 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7997 17:16:50.353449 ==
7998 17:16:50.353516
7999 17:16:50.353577
8000 17:16:50.353637 TX Vref Scan disable
8001 17:16:50.357495 == TX Byte 0 ==
8002 17:16:50.360906 Update DQM dly =736 (2 ,6, 32) DQM OEN =(3 ,3)
8003 17:16:50.364966 == TX Byte 1 ==
8004 17:16:50.367581 Update DQM dly =721 (2 ,6, 17) DQM OEN =(3 ,3)
8005 17:16:50.367741 DramC Write-DBI off
8006 17:16:50.371262
8007 17:16:50.371430
8008 17:16:50.371526 [DATLAT]
8009 17:16:50.371605 Freq=1600, CH0 RK0
8010 17:16:50.371685
8011 17:16:50.374567 DATLAT Default: 0xf
8012 17:16:50.374696 0, 0xFFFF, sum = 0
8013 17:16:50.377502 1, 0xFFFF, sum = 0
8014 17:16:50.377588 2, 0xFFFF, sum = 0
8015 17:16:50.380886
8016 17:16:50.381374 3, 0xFFFF, sum = 0
8017 17:16:50.384234 4, 0xFFFF, sum = 0
8018 17:16:50.384678 5, 0xFFFF, sum = 0
8019 17:16:50.387645 6, 0xFFFF, sum = 0
8020 17:16:50.388163 7, 0xFFFF, sum = 0
8021 17:16:50.391086 8, 0xFFFF, sum = 0
8022 17:16:50.391563 9, 0xFFFF, sum = 0
8023 17:16:50.394509 10, 0xFFFF, sum = 0
8024 17:16:50.394950 11, 0xFFFF, sum = 0
8025 17:16:50.397612 12, 0xFFFF, sum = 0
8026 17:16:50.398127 13, 0xFFFF, sum = 0
8027 17:16:50.400944 14, 0x0, sum = 1
8028 17:16:50.401454 15, 0x0, sum = 2
8029 17:16:50.404374 16, 0x0, sum = 3
8030 17:16:50.404904 17, 0x0, sum = 4
8031 17:16:50.407463 best_step = 15
8032 17:16:50.407905
8033 17:16:50.408272 ==
8034 17:16:50.410566 Dram Type= 6, Freq= 0, CH_0, rank 0
8035 17:16:50.414175 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8036 17:16:50.414632 ==
8037 17:16:50.417518 RX Vref Scan: 1
8038 17:16:50.417988
8039 17:16:50.418371 Set Vref Range= 24 -> 127
8040 17:16:50.418722
8041 17:16:50.420640 RX Vref 24 -> 127, step: 1
8042 17:16:50.421081
8043 17:16:50.423888 RX Delay 19 -> 252, step: 4
8044 17:16:50.424345
8045 17:16:50.427355 Set Vref, RX VrefLevel [Byte0]: 24
8046 17:16:50.430207 [Byte1]: 24
8047 17:16:50.430293
8048 17:16:50.433698 Set Vref, RX VrefLevel [Byte0]: 25
8049 17:16:50.436989 [Byte1]: 25
8050 17:16:50.440605
8051 17:16:50.440694 Set Vref, RX VrefLevel [Byte0]: 26
8052 17:16:50.443668 [Byte1]: 26
8053 17:16:50.448209
8054 17:16:50.448289 Set Vref, RX VrefLevel [Byte0]: 27
8055 17:16:50.451387 [Byte1]: 27
8056 17:16:50.455533
8057 17:16:50.455618 Set Vref, RX VrefLevel [Byte0]: 28
8058 17:16:50.458870 [Byte1]: 28
8059 17:16:50.462798
8060 17:16:50.462897 Set Vref, RX VrefLevel [Byte0]: 29
8061 17:16:50.466359 [Byte1]: 29
8062 17:16:50.470872
8063 17:16:50.470989 Set Vref, RX VrefLevel [Byte0]: 30
8064 17:16:50.474151 [Byte1]: 30
8065 17:16:50.478133
8066 17:16:50.478261 Set Vref, RX VrefLevel [Byte0]: 31
8067 17:16:50.481283 [Byte1]: 31
8068 17:16:50.485703
8069 17:16:50.485863 Set Vref, RX VrefLevel [Byte0]: 32
8070 17:16:50.489273 [Byte1]: 32
8071 17:16:50.493117
8072 17:16:50.493198 Set Vref, RX VrefLevel [Byte0]: 33
8073 17:16:50.496233 [Byte1]: 33
8074 17:16:50.500591
8075 17:16:50.503739 Set Vref, RX VrefLevel [Byte0]: 34
8076 17:16:50.507383 [Byte1]: 34
8077 17:16:50.507473
8078 17:16:50.510539 Set Vref, RX VrefLevel [Byte0]: 35
8079 17:16:50.513601 [Byte1]: 35
8080 17:16:50.513686
8081 17:16:50.517073 Set Vref, RX VrefLevel [Byte0]: 36
8082 17:16:50.520179 [Byte1]: 36
8083 17:16:50.520271
8084 17:16:50.524131 Set Vref, RX VrefLevel [Byte0]: 37
8085 17:16:50.527201 [Byte1]: 37
8086 17:16:50.531482
8087 17:16:50.531654 Set Vref, RX VrefLevel [Byte0]: 38
8088 17:16:50.534840 [Byte1]: 38
8089 17:16:50.538683
8090 17:16:50.538854 Set Vref, RX VrefLevel [Byte0]: 39
8091 17:16:50.542307 [Byte1]: 39
8092 17:16:50.546207
8093 17:16:50.546349 Set Vref, RX VrefLevel [Byte0]: 40
8094 17:16:50.549885 [Byte1]: 40
8095 17:16:50.553882
8096 17:16:50.554069 Set Vref, RX VrefLevel [Byte0]: 41
8097 17:16:50.557348 [Byte1]: 41
8098 17:16:50.561527
8099 17:16:50.561741 Set Vref, RX VrefLevel [Byte0]: 42
8100 17:16:50.565036 [Byte1]: 42
8101 17:16:50.569104
8102 17:16:50.569449 Set Vref, RX VrefLevel [Byte0]: 43
8103 17:16:50.572334 [Byte1]: 43
8104 17:16:50.576834
8105 17:16:50.577257 Set Vref, RX VrefLevel [Byte0]: 44
8106 17:16:50.580447 [Byte1]: 44
8107 17:16:50.584541
8108 17:16:50.584989 Set Vref, RX VrefLevel [Byte0]: 45
8109 17:16:50.587598 [Byte1]: 45
8110 17:16:50.592104
8111 17:16:50.592553 Set Vref, RX VrefLevel [Byte0]: 46
8112 17:16:50.595330 [Byte1]: 46
8113 17:16:50.599466
8114 17:16:50.599915 Set Vref, RX VrefLevel [Byte0]: 47
8115 17:16:50.603020 [Byte1]: 47
8116 17:16:50.607367
8117 17:16:50.607816 Set Vref, RX VrefLevel [Byte0]: 48
8118 17:16:50.610772 [Byte1]: 48
8119 17:16:50.614587
8120 17:16:50.615030 Set Vref, RX VrefLevel [Byte0]: 49
8121 17:16:50.618367 [Byte1]: 49
8122 17:16:50.622784
8123 17:16:50.623329 Set Vref, RX VrefLevel [Byte0]: 50
8124 17:16:50.625414 [Byte1]: 50
8125 17:16:50.629969
8126 17:16:50.630416 Set Vref, RX VrefLevel [Byte0]: 51
8127 17:16:50.636345 [Byte1]: 51
8128 17:16:50.636812
8129 17:16:50.640050 Set Vref, RX VrefLevel [Byte0]: 52
8130 17:16:50.643134 [Byte1]: 52
8131 17:16:50.643576
8132 17:16:50.646014 Set Vref, RX VrefLevel [Byte0]: 53
8133 17:16:50.649377 [Byte1]: 53
8134 17:16:50.649822
8135 17:16:50.653005 Set Vref, RX VrefLevel [Byte0]: 54
8136 17:16:50.655894 [Byte1]: 54
8137 17:16:50.660231
8138 17:16:50.660694 Set Vref, RX VrefLevel [Byte0]: 55
8139 17:16:50.663471 [Byte1]: 55
8140 17:16:50.667988
8141 17:16:50.668400 Set Vref, RX VrefLevel [Byte0]: 56
8142 17:16:50.671145 [Byte1]: 56
8143 17:16:50.675613
8144 17:16:50.676059 Set Vref, RX VrefLevel [Byte0]: 57
8145 17:16:50.678680 [Byte1]: 57
8146 17:16:50.683296
8147 17:16:50.683842 Set Vref, RX VrefLevel [Byte0]: 58
8148 17:16:50.686167 [Byte1]: 58
8149 17:16:50.690634
8150 17:16:50.691081 Set Vref, RX VrefLevel [Byte0]: 59
8151 17:16:50.693478 [Byte1]: 59
8152 17:16:50.697849
8153 17:16:50.698355 Set Vref, RX VrefLevel [Byte0]: 60
8154 17:16:50.701076 [Byte1]: 60
8155 17:16:50.705397
8156 17:16:50.705885 Set Vref, RX VrefLevel [Byte0]: 61
8157 17:16:50.708928 [Byte1]: 61
8158 17:16:50.713171
8159 17:16:50.713650 Set Vref, RX VrefLevel [Byte0]: 62
8160 17:16:50.716827 [Byte1]: 62
8161 17:16:50.720839
8162 17:16:50.721295 Set Vref, RX VrefLevel [Byte0]: 63
8163 17:16:50.723987 [Byte1]: 63
8164 17:16:50.728185
8165 17:16:50.728635 Set Vref, RX VrefLevel [Byte0]: 64
8166 17:16:50.731536 [Byte1]: 64
8167 17:16:50.735861
8168 17:16:50.736322 Set Vref, RX VrefLevel [Byte0]: 65
8169 17:16:50.739693 [Byte1]: 65
8170 17:16:50.743620
8171 17:16:50.744069 Set Vref, RX VrefLevel [Byte0]: 66
8172 17:16:50.746918 [Byte1]: 66
8173 17:16:50.750982
8174 17:16:50.751429 Set Vref, RX VrefLevel [Byte0]: 67
8175 17:16:50.754116 [Byte1]: 67
8176 17:16:50.758523
8177 17:16:50.758981 Set Vref, RX VrefLevel [Byte0]: 68
8178 17:16:50.762240 [Byte1]: 68
8179 17:16:50.766448
8180 17:16:50.766934 Set Vref, RX VrefLevel [Byte0]: 69
8181 17:16:50.769367 [Byte1]: 69
8182 17:16:50.773508
8183 17:16:50.773950 Set Vref, RX VrefLevel [Byte0]: 70
8184 17:16:50.777032 [Byte1]: 70
8185 17:16:50.781143
8186 17:16:50.781639 Set Vref, RX VrefLevel [Byte0]: 71
8187 17:16:50.784944 [Byte1]: 71
8188 17:16:50.789281
8189 17:16:50.789869 Set Vref, RX VrefLevel [Byte0]: 72
8190 17:16:50.792530 [Byte1]: 72
8191 17:16:50.796254
8192 17:16:50.796702 Set Vref, RX VrefLevel [Byte0]: 73
8193 17:16:50.800018 [Byte1]: 73
8194 17:16:50.803939
8195 17:16:50.804382 Set Vref, RX VrefLevel [Byte0]: 74
8196 17:16:50.807218 [Byte1]: 74
8197 17:16:50.811767
8198 17:16:50.812221 Set Vref, RX VrefLevel [Byte0]: 75
8199 17:16:50.814990 [Byte1]: 75
8200 17:16:50.819147
8201 17:16:50.819591 Set Vref, RX VrefLevel [Byte0]: 76
8202 17:16:50.822780 [Byte1]: 76
8203 17:16:50.826808
8204 17:16:50.827255 Set Vref, RX VrefLevel [Byte0]: 77
8205 17:16:50.830019 [Byte1]: 77
8206 17:16:50.834425
8207 17:16:50.834868 Set Vref, RX VrefLevel [Byte0]: 78
8208 17:16:50.837509 [Byte1]: 78
8209 17:16:50.841653
8210 17:16:50.842126 Final RX Vref Byte 0 = 67 to rank0
8211 17:16:50.845180 Final RX Vref Byte 1 = 57 to rank0
8212 17:16:50.848625 Final RX Vref Byte 0 = 67 to rank1
8213 17:16:50.852017 Final RX Vref Byte 1 = 57 to rank1==
8214 17:16:50.854864 Dram Type= 6, Freq= 0, CH_0, rank 0
8215 17:16:50.862128 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8216 17:16:50.862613 ==
8217 17:16:50.862978 DQS Delay:
8218 17:16:50.863307 DQS0 = 0, DQS1 = 0
8219 17:16:50.865217 DQM Delay:
8220 17:16:50.865697 DQM0 = 133, DQM1 = 124
8221 17:16:50.868649 DQ Delay:
8222 17:16:50.871508 DQ0 =132, DQ1 =136, DQ2 =130, DQ3 =132
8223 17:16:50.875486 DQ4 =132, DQ5 =122, DQ6 =140, DQ7 =142
8224 17:16:50.878397 DQ8 =116, DQ9 =112, DQ10 =126, DQ11 =120
8225 17:16:50.881829 DQ12 =130, DQ13 =128, DQ14 =136, DQ15 =130
8226 17:16:50.882272
8227 17:16:50.882619
8228 17:16:50.882943
8229 17:16:50.885046 [DramC_TX_OE_Calibration] TA2
8230 17:16:50.888216 Original DQ_B0 (3 6) =30, OEN = 27
8231 17:16:50.891859 Original DQ_B1 (3 6) =30, OEN = 27
8232 17:16:50.894770 24, 0x0, End_B0=24 End_B1=24
8233 17:16:50.895219 25, 0x0, End_B0=25 End_B1=25
8234 17:16:50.898240 26, 0x0, End_B0=26 End_B1=26
8235 17:16:50.901292 27, 0x0, End_B0=27 End_B1=27
8236 17:16:50.905019 28, 0x0, End_B0=28 End_B1=28
8237 17:16:50.908297 29, 0x0, End_B0=29 End_B1=29
8238 17:16:50.908748 30, 0x0, End_B0=30 End_B1=30
8239 17:16:50.911466 31, 0x4141, End_B0=30 End_B1=30
8240 17:16:50.914901 Byte0 end_step=30 best_step=27
8241 17:16:50.917991 Byte1 end_step=30 best_step=27
8242 17:16:50.921206 Byte0 TX OE(2T, 0.5T) = (3, 3)
8243 17:16:50.924746 Byte1 TX OE(2T, 0.5T) = (3, 3)
8244 17:16:50.925316
8245 17:16:50.925719
8246 17:16:50.931188 [DQSOSCAuto] RK0, (LSB)MR18= 0x2011, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 393 ps
8247 17:16:50.934412 CH0 RK0: MR19=303, MR18=2011
8248 17:16:50.940932 CH0_RK0: MR19=0x303, MR18=0x2011, DQSOSC=393, MR23=63, INC=23, DEC=15
8249 17:16:50.941429
8250 17:16:50.944146 ----->DramcWriteLeveling(PI) begin...
8251 17:16:50.944593 ==
8252 17:16:50.947678 Dram Type= 6, Freq= 0, CH_0, rank 1
8253 17:16:50.950969 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8254 17:16:50.951425 ==
8255 17:16:50.954034 Write leveling (Byte 0): 32 => 32
8256 17:16:50.957855 Write leveling (Byte 1): 28 => 28
8257 17:16:50.960875 DramcWriteLeveling(PI) end<-----
8258 17:16:50.961315
8259 17:16:50.961711 ==
8260 17:16:50.964469 Dram Type= 6, Freq= 0, CH_0, rank 1
8261 17:16:50.967435 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8262 17:16:50.971275 ==
8263 17:16:50.971852 [Gating] SW mode calibration
8264 17:16:50.977741 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8265 17:16:50.984233 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8266 17:16:50.987011 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8267 17:16:50.993981 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8268 17:16:50.997073 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8269 17:16:51.000100 1 4 12 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8270 17:16:51.007121 1 4 16 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8271 17:16:51.010698 1 4 20 | B1->B0 | 2b2b 3434 | 0 1 | (0 0) (1 1)
8272 17:16:51.013755 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8273 17:16:51.020364 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8274 17:16:51.023182 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8275 17:16:51.026390 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8276 17:16:51.032981 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8277 17:16:51.036433 1 5 12 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
8278 17:16:51.039766 1 5 16 | B1->B0 | 3434 2a2a | 1 0 | (1 1) (1 0)
8279 17:16:51.046438 1 5 20 | B1->B0 | 3232 2323 | 1 0 | (1 0) (0 0)
8280 17:16:51.049293 1 5 24 | B1->B0 | 2626 2323 | 0 0 | (0 0) (0 0)
8281 17:16:51.052969 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8282 17:16:51.059772 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8283 17:16:51.062839 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8284 17:16:51.066270 1 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8285 17:16:51.072978 1 6 12 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (1 1)
8286 17:16:51.076307 1 6 16 | B1->B0 | 2525 4343 | 0 0 | (0 0) (0 0)
8287 17:16:51.079455 1 6 20 | B1->B0 | 3838 4646 | 0 0 | (0 0) (0 0)
8288 17:16:51.086088 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8289 17:16:51.089374 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8290 17:16:51.092687 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8291 17:16:51.099134 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8292 17:16:51.102308 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8293 17:16:51.105890 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8294 17:16:51.112297 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8295 17:16:51.115676 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8296 17:16:51.118849 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8297 17:16:51.125668 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8298 17:16:51.128756 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8299 17:16:51.132210 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8300 17:16:51.138897 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8301 17:16:51.141912 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8302 17:16:51.145567 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8303 17:16:51.152177 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8304 17:16:51.155119 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8305 17:16:51.158621 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8306 17:16:51.165060 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8307 17:16:51.168070 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8308 17:16:51.171564 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8309 17:16:51.178020 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8310 17:16:51.181661 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8311 17:16:51.184616 Total UI for P1: 0, mck2ui 16
8312 17:16:51.187994 best dqsien dly found for B0: ( 1, 9, 12)
8313 17:16:51.191078 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8314 17:16:51.194504 Total UI for P1: 0, mck2ui 16
8315 17:16:51.197598 best dqsien dly found for B1: ( 1, 9, 18)
8316 17:16:51.201072 best DQS0 dly(MCK, UI, PI) = (1, 9, 12)
8317 17:16:51.204415 best DQS1 dly(MCK, UI, PI) = (1, 9, 18)
8318 17:16:51.204501
8319 17:16:51.211252 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 12)
8320 17:16:51.214533 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 18)
8321 17:16:51.217675 [Gating] SW calibration Done
8322 17:16:51.217759 ==
8323 17:16:51.221244 Dram Type= 6, Freq= 0, CH_0, rank 1
8324 17:16:51.224199 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8325 17:16:51.224284 ==
8326 17:16:51.224351 RX Vref Scan: 0
8327 17:16:51.224413
8328 17:16:51.227238 RX Vref 0 -> 0, step: 1
8329 17:16:51.227322
8330 17:16:51.230899 RX Delay 0 -> 252, step: 8
8331 17:16:51.234073 iDelay=200, Bit 0, Center 135 (80 ~ 191) 112
8332 17:16:51.237163 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8333 17:16:51.243784 iDelay=200, Bit 2, Center 127 (72 ~ 183) 112
8334 17:16:51.247304 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8335 17:16:51.250489 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8336 17:16:51.254126 iDelay=200, Bit 5, Center 123 (64 ~ 183) 120
8337 17:16:51.257482 iDelay=200, Bit 6, Center 139 (80 ~ 199) 120
8338 17:16:51.264171 iDelay=200, Bit 7, Center 143 (88 ~ 199) 112
8339 17:16:51.267049 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8340 17:16:51.270799 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8341 17:16:51.273591 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8342 17:16:51.277115 iDelay=200, Bit 11, Center 123 (64 ~ 183) 120
8343 17:16:51.283678 iDelay=200, Bit 12, Center 135 (80 ~ 191) 112
8344 17:16:51.287255 iDelay=200, Bit 13, Center 135 (80 ~ 191) 112
8345 17:16:51.290245 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8346 17:16:51.293702 iDelay=200, Bit 15, Center 135 (80 ~ 191) 112
8347 17:16:51.293787 ==
8348 17:16:51.296667 Dram Type= 6, Freq= 0, CH_0, rank 1
8349 17:16:51.303328 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8350 17:16:51.303417 ==
8351 17:16:51.303484 DQS Delay:
8352 17:16:51.306802 DQS0 = 0, DQS1 = 0
8353 17:16:51.306889 DQM Delay:
8354 17:16:51.309800 DQM0 = 133, DQM1 = 128
8355 17:16:51.309885 DQ Delay:
8356 17:16:51.313124 DQ0 =135, DQ1 =135, DQ2 =127, DQ3 =127
8357 17:16:51.316532 DQ4 =135, DQ5 =123, DQ6 =139, DQ7 =143
8358 17:16:51.320096 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =123
8359 17:16:51.323778 DQ12 =135, DQ13 =135, DQ14 =135, DQ15 =135
8360 17:16:51.323862
8361 17:16:51.323927
8362 17:16:51.323987 ==
8363 17:16:51.326736 Dram Type= 6, Freq= 0, CH_0, rank 1
8364 17:16:51.333122 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8365 17:16:51.333207 ==
8366 17:16:51.333273
8367 17:16:51.333377
8368 17:16:51.333438 TX Vref Scan disable
8369 17:16:51.336397 == TX Byte 0 ==
8370 17:16:51.339928 Update DQ dly =988 (3 ,6, 28) DQ OEN =(3 ,3)
8371 17:16:51.343028 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8372 17:16:51.346675
8373 17:16:51.346758 == TX Byte 1 ==
8374 17:16:51.349770 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8375 17:16:51.356289 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8376 17:16:51.356373 ==
8377 17:16:51.359421 Dram Type= 6, Freq= 0, CH_0, rank 1
8378 17:16:51.362973 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8379 17:16:51.363056 ==
8380 17:16:51.374800
8381 17:16:51.377757 TX Vref early break, caculate TX vref
8382 17:16:51.381205 TX Vref=16, minBit 1, minWin=22, winSum=378
8383 17:16:51.384749 TX Vref=18, minBit 1, minWin=23, winSum=385
8384 17:16:51.387872 TX Vref=20, minBit 1, minWin=23, winSum=394
8385 17:16:51.391395 TX Vref=22, minBit 4, minWin=24, winSum=407
8386 17:16:51.394620 TX Vref=24, minBit 1, minWin=24, winSum=411
8387 17:16:51.401242 TX Vref=26, minBit 4, minWin=24, winSum=417
8388 17:16:51.404661 TX Vref=28, minBit 4, minWin=24, winSum=415
8389 17:16:51.407742 TX Vref=30, minBit 4, minWin=24, winSum=404
8390 17:16:51.411163 TX Vref=32, minBit 1, minWin=23, winSum=395
8391 17:16:51.418245 [TxChooseVref] Worse bit 4, Min win 24, Win sum 417, Final Vref 26
8392 17:16:51.418331
8393 17:16:51.421256 Final TX Range 0 Vref 26
8394 17:16:51.421373
8395 17:16:51.421457 ==
8396 17:16:51.424754 Dram Type= 6, Freq= 0, CH_0, rank 1
8397 17:16:51.427713 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8398 17:16:51.427797 ==
8399 17:16:51.427862
8400 17:16:51.427924
8401 17:16:51.430984 TX Vref Scan disable
8402 17:16:51.434560 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8403 17:16:51.437728 == TX Byte 0 ==
8404 17:16:51.440829 u2DelayCellOfst[0]=11 cells (3 PI)
8405 17:16:51.444305 u2DelayCellOfst[1]=18 cells (5 PI)
8406 17:16:51.447616 u2DelayCellOfst[2]=11 cells (3 PI)
8407 17:16:51.451119 u2DelayCellOfst[3]=14 cells (4 PI)
8408 17:16:51.454318 u2DelayCellOfst[4]=7 cells (2 PI)
8409 17:16:51.454401 u2DelayCellOfst[5]=0 cells (0 PI)
8410 17:16:51.457246
8411 17:16:51.457353 u2DelayCellOfst[6]=18 cells (5 PI)
8412 17:16:51.460809 u2DelayCellOfst[7]=18 cells (5 PI)
8413 17:16:51.467801 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
8414 17:16:51.470800 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
8415 17:16:51.470884 == TX Byte 1 ==
8416 17:16:51.473935 u2DelayCellOfst[8]=0 cells (0 PI)
8417 17:16:51.477238 u2DelayCellOfst[9]=3 cells (1 PI)
8418 17:16:51.480314 u2DelayCellOfst[10]=7 cells (2 PI)
8419 17:16:51.484034 u2DelayCellOfst[11]=3 cells (1 PI)
8420 17:16:51.486949 u2DelayCellOfst[12]=11 cells (3 PI)
8421 17:16:51.490581 u2DelayCellOfst[13]=14 cells (4 PI)
8422 17:16:51.493554 u2DelayCellOfst[14]=18 cells (5 PI)
8423 17:16:51.497055 u2DelayCellOfst[15]=11 cells (3 PI)
8424 17:16:51.500594 Update DQ dly =981 (3 ,6, 21) DQ OEN =(3 ,3)
8425 17:16:51.507099 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
8426 17:16:51.507189 DramC Write-DBI on
8427 17:16:51.507255 ==
8428 17:16:51.510155 Dram Type= 6, Freq= 0, CH_0, rank 1
8429 17:16:51.513611 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8430 17:16:51.513695 ==
8431 17:16:51.516671
8432 17:16:51.516754
8433 17:16:51.516820 TX Vref Scan disable
8434 17:16:51.520219 == TX Byte 0 ==
8435 17:16:51.523916 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
8436 17:16:51.527047 == TX Byte 1 ==
8437 17:16:51.530089 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8438 17:16:51.530213 DramC Write-DBI off
8439 17:16:51.533638
8440 17:16:51.533721
8441 17:16:51.533786 [DATLAT]
8442 17:16:51.533846 Freq=1600, CH0 RK1
8443 17:16:51.533905
8444 17:16:51.536704 DATLAT Default: 0xf
8445 17:16:51.536787 0, 0xFFFF, sum = 0
8446 17:16:51.540158 1, 0xFFFF, sum = 0
8447 17:16:51.540244 2, 0xFFFF, sum = 0
8448 17:16:51.543230
8449 17:16:51.543313 3, 0xFFFF, sum = 0
8450 17:16:51.546828 4, 0xFFFF, sum = 0
8451 17:16:51.546912 5, 0xFFFF, sum = 0
8452 17:16:51.549975 6, 0xFFFF, sum = 0
8453 17:16:51.550089 7, 0xFFFF, sum = 0
8454 17:16:51.553288 8, 0xFFFF, sum = 0
8455 17:16:51.553395 9, 0xFFFF, sum = 0
8456 17:16:51.556836 10, 0xFFFF, sum = 0
8457 17:16:51.556919 11, 0xFFFF, sum = 0
8458 17:16:51.559732 12, 0xFFFF, sum = 0
8459 17:16:51.559834 13, 0xFFFF, sum = 0
8460 17:16:51.563261 14, 0x0, sum = 1
8461 17:16:51.563345 15, 0x0, sum = 2
8462 17:16:51.566368 16, 0x0, sum = 3
8463 17:16:51.566451 17, 0x0, sum = 4
8464 17:16:51.569753 best_step = 15
8465 17:16:51.569837
8466 17:16:51.569903 ==
8467 17:16:51.573065 Dram Type= 6, Freq= 0, CH_0, rank 1
8468 17:16:51.576598 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 17:16:51.576682 ==
8470 17:16:51.579802 RX Vref Scan: 0
8471 17:16:51.579881
8472 17:16:51.579946 RX Vref 0 -> 0, step: 1
8473 17:16:51.580006
8474 17:16:51.583066 RX Delay 11 -> 252, step: 4
8475 17:16:51.586150 iDelay=195, Bit 0, Center 128 (79 ~ 178) 100
8476 17:16:51.589652
8477 17:16:51.592718 iDelay=195, Bit 1, Center 134 (79 ~ 190) 112
8478 17:16:51.596058 iDelay=195, Bit 2, Center 124 (71 ~ 178) 108
8479 17:16:51.599471 iDelay=195, Bit 3, Center 128 (75 ~ 182) 108
8480 17:16:51.602720 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
8481 17:16:51.609176 iDelay=195, Bit 5, Center 120 (67 ~ 174) 108
8482 17:16:51.612695 iDelay=195, Bit 6, Center 138 (83 ~ 194) 112
8483 17:16:51.616073 iDelay=195, Bit 7, Center 140 (87 ~ 194) 108
8484 17:16:51.619304 iDelay=195, Bit 8, Center 114 (59 ~ 170) 112
8485 17:16:51.622832 iDelay=195, Bit 9, Center 112 (59 ~ 166) 108
8486 17:16:51.625988 iDelay=195, Bit 10, Center 126 (71 ~ 182) 112
8487 17:16:51.629341
8488 17:16:51.632502 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
8489 17:16:51.635880 iDelay=195, Bit 12, Center 132 (79 ~ 186) 108
8490 17:16:51.639271 iDelay=195, Bit 13, Center 132 (79 ~ 186) 108
8491 17:16:51.642484 iDelay=195, Bit 14, Center 136 (83 ~ 190) 108
8492 17:16:51.649174 iDelay=195, Bit 15, Center 132 (79 ~ 186) 108
8493 17:16:51.649252 ==
8494 17:16:51.652232 Dram Type= 6, Freq= 0, CH_0, rank 1
8495 17:16:51.655839 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8496 17:16:51.655922 ==
8497 17:16:51.655987 DQS Delay:
8498 17:16:51.659048 DQS0 = 0, DQS1 = 0
8499 17:16:51.659130 DQM Delay:
8500 17:16:51.662482 DQM0 = 130, DQM1 = 125
8501 17:16:51.662566 DQ Delay:
8502 17:16:51.665722 DQ0 =128, DQ1 =134, DQ2 =124, DQ3 =128
8503 17:16:51.668814 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =140
8504 17:16:51.672076 DQ8 =114, DQ9 =112, DQ10 =126, DQ11 =120
8505 17:16:51.675754 DQ12 =132, DQ13 =132, DQ14 =136, DQ15 =132
8506 17:16:51.675838
8507 17:16:51.678759
8508 17:16:51.678843
8509 17:16:51.678908
8510 17:16:51.678969 [DramC_TX_OE_Calibration] TA2
8511 17:16:51.682332 Original DQ_B0 (3 6) =30, OEN = 27
8512 17:16:51.685865 Original DQ_B1 (3 6) =30, OEN = 27
8513 17:16:51.688727 24, 0x0, End_B0=24 End_B1=24
8514 17:16:51.691945 25, 0x0, End_B0=25 End_B1=25
8515 17:16:51.695397 26, 0x0, End_B0=26 End_B1=26
8516 17:16:51.695481 27, 0x0, End_B0=27 End_B1=27
8517 17:16:51.698813 28, 0x0, End_B0=28 End_B1=28
8518 17:16:51.701744 29, 0x0, End_B0=29 End_B1=29
8519 17:16:51.705482 30, 0x0, End_B0=30 End_B1=30
8520 17:16:51.708616 31, 0x4545, End_B0=30 End_B1=30
8521 17:16:51.708701 Byte0 end_step=30 best_step=27
8522 17:16:51.711633
8523 17:16:51.711718 Byte1 end_step=30 best_step=27
8524 17:16:51.715096 Byte0 TX OE(2T, 0.5T) = (3, 3)
8525 17:16:51.718641 Byte1 TX OE(2T, 0.5T) = (3, 3)
8526 17:16:51.718725
8527 17:16:51.718793
8528 17:16:51.728562 [DQSOSCAuto] RK1, (LSB)MR18= 0x1d01, (MSB)MR19= 0x303, tDQSOscB0 = 409 ps tDQSOscB1 = 395 ps
8529 17:16:51.728664 CH0 RK1: MR19=303, MR18=1D01
8530 17:16:51.735514 CH0_RK1: MR19=0x303, MR18=0x1D01, DQSOSC=395, MR23=63, INC=23, DEC=15
8531 17:16:51.738451 [RxdqsGatingPostProcess] freq 1600
8532 17:16:51.745229 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8533 17:16:51.748517 best DQS0 dly(2T, 0.5T) = (1, 1)
8534 17:16:51.751530 best DQS1 dly(2T, 0.5T) = (1, 1)
8535 17:16:51.755196 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8536 17:16:51.758397 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8537 17:16:51.758541 best DQS0 dly(2T, 0.5T) = (1, 1)
8538 17:16:51.761377 best DQS1 dly(2T, 0.5T) = (1, 1)
8539 17:16:51.765151 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8540 17:16:51.768577 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8541 17:16:51.771496 Pre-setting of DQS Precalculation
8542 17:16:51.778201 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8543 17:16:51.778497 ==
8544 17:16:51.781221 Dram Type= 6, Freq= 0, CH_1, rank 0
8545 17:16:51.785046 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8546 17:16:51.785396 ==
8547 17:16:51.791490 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8548 17:16:51.795195 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8549 17:16:51.798351 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8550 17:16:51.804512 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8551 17:16:51.813935 [CA 0] Center 41 (12~71) winsize 60
8552 17:16:51.816865 [CA 1] Center 42 (12~72) winsize 61
8553 17:16:51.820466 [CA 2] Center 36 (7~66) winsize 60
8554 17:16:51.823813 [CA 3] Center 36 (7~65) winsize 59
8555 17:16:51.826805 [CA 4] Center 36 (7~66) winsize 60
8556 17:16:51.830362 [CA 5] Center 36 (7~66) winsize 60
8557 17:16:51.830797
8558 17:16:51.833855 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8559 17:16:51.834322
8560 17:16:51.836897 [CATrainingPosCal] consider 1 rank data
8561 17:16:51.840070 u2DelayCellTimex100 = 262/100 ps
8562 17:16:51.843594 CA0 delay=41 (12~71),Diff = 5 PI (18 cell)
8563 17:16:51.847392
8564 17:16:51.850568 CA1 delay=42 (12~72),Diff = 6 PI (22 cell)
8565 17:16:51.853351 CA2 delay=36 (7~66),Diff = 0 PI (0 cell)
8566 17:16:51.857033 CA3 delay=36 (7~65),Diff = 0 PI (0 cell)
8567 17:16:51.860363 CA4 delay=36 (7~66),Diff = 0 PI (0 cell)
8568 17:16:51.863599 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8569 17:16:51.864131
8570 17:16:51.866725 CA PerBit enable=1, Macro0, CA PI delay=36
8571 17:16:51.867160
8572 17:16:51.869961 [CBTSetCACLKResult] CA Dly = 36
8573 17:16:51.873583 CS Dly: 9 (0~40)
8574 17:16:51.877073 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8575 17:16:51.880121 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8576 17:16:51.880627 ==
8577 17:16:51.883021 Dram Type= 6, Freq= 0, CH_1, rank 1
8578 17:16:51.886460 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8579 17:16:51.890040 ==
8580 17:16:51.892993 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8581 17:16:51.896675 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8582 17:16:51.903005 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8583 17:16:51.909452 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8584 17:16:51.916780 [CA 0] Center 42 (13~71) winsize 59
8585 17:16:51.920188 [CA 1] Center 42 (13~72) winsize 60
8586 17:16:51.923325 [CA 2] Center 37 (8~67) winsize 60
8587 17:16:51.926774 [CA 3] Center 37 (8~66) winsize 59
8588 17:16:51.929856 [CA 4] Center 37 (8~67) winsize 60
8589 17:16:51.933446 [CA 5] Center 36 (7~66) winsize 60
8590 17:16:51.933900
8591 17:16:51.936445 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8592 17:16:51.936902
8593 17:16:51.943214 [CATrainingPosCal] consider 2 rank data
8594 17:16:51.943688 u2DelayCellTimex100 = 262/100 ps
8595 17:16:51.949570 CA0 delay=42 (13~71),Diff = 6 PI (22 cell)
8596 17:16:51.953228 CA1 delay=42 (13~72),Diff = 6 PI (22 cell)
8597 17:16:51.956191 CA2 delay=37 (8~66),Diff = 1 PI (3 cell)
8598 17:16:51.959584 CA3 delay=36 (8~65),Diff = 0 PI (0 cell)
8599 17:16:51.962759 CA4 delay=37 (8~66),Diff = 1 PI (3 cell)
8600 17:16:51.966260 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8601 17:16:51.966688
8602 17:16:51.969939 CA PerBit enable=1, Macro0, CA PI delay=36
8603 17:16:51.970373
8604 17:16:51.972800 [CBTSetCACLKResult] CA Dly = 36
8605 17:16:51.976163 CS Dly: 11 (0~44)
8606 17:16:51.979662 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8607 17:16:51.982846 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8608 17:16:51.983279
8609 17:16:51.986307 ----->DramcWriteLeveling(PI) begin...
8610 17:16:51.986744 ==
8611 17:16:51.989577 Dram Type= 6, Freq= 0, CH_1, rank 0
8612 17:16:51.996152 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8613 17:16:51.996586 ==
8614 17:16:51.999291 Write leveling (Byte 0): 23 => 23
8615 17:16:52.002748 Write leveling (Byte 1): 27 => 27
8616 17:16:52.003202 DramcWriteLeveling(PI) end<-----
8617 17:16:52.003542
8618 17:16:52.006407 ==
8619 17:16:52.009405 Dram Type= 6, Freq= 0, CH_1, rank 0
8620 17:16:52.012782 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8621 17:16:52.013217 ==
8622 17:16:52.016013 [Gating] SW mode calibration
8623 17:16:52.022259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8624 17:16:52.025521 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8625 17:16:52.032304 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8626 17:16:52.035933 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8627 17:16:52.038952 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8628 17:16:52.045820 1 4 12 | B1->B0 | 2d2c 3232 | 1 0 | (0 0) (0 0)
8629 17:16:52.048720 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8630 17:16:52.052153 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8631 17:16:52.058740 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8632 17:16:52.061835 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8633 17:16:52.065698 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8634 17:16:52.072018 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8635 17:16:52.075375 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 0)
8636 17:16:52.078357 1 5 12 | B1->B0 | 3131 2525 | 0 0 | (0 0) (1 0)
8637 17:16:52.085243 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8638 17:16:52.088730 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8639 17:16:52.091566 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8640 17:16:52.098240 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8641 17:16:52.101787 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8642 17:16:52.105186 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8643 17:16:52.111696 1 6 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
8644 17:16:52.115241 1 6 12 | B1->B0 | 3d3d 4646 | 0 0 | (0 0) (0 0)
8645 17:16:52.118364 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8646 17:16:52.124890 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8647 17:16:52.128436 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8648 17:16:52.131426 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8649 17:16:52.138185 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8650 17:16:52.141511 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8651 17:16:52.144717 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8652 17:16:52.151417 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
8653 17:16:52.154800 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8654 17:16:52.157974 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8655 17:16:52.164620 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8656 17:16:52.167429 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8657 17:16:52.171105 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8658 17:16:52.177279 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8659 17:16:52.181038 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8660 17:16:52.184389 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8661 17:16:52.190823 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8662 17:16:52.194262 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8663 17:16:52.197651 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8664 17:16:52.204205 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8665 17:16:52.207288 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8666 17:16:52.210557 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8667 17:16:52.217623 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8668 17:16:52.220632 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8669 17:16:52.224018 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8670 17:16:52.227471 Total UI for P1: 0, mck2ui 16
8671 17:16:52.230439 best dqsien dly found for B0: ( 1, 9, 10)
8672 17:16:52.234160 Total UI for P1: 0, mck2ui 16
8673 17:16:52.237040 best dqsien dly found for B1: ( 1, 9, 10)
8674 17:16:52.240289 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8675 17:16:52.243447 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
8676 17:16:52.243531
8677 17:16:52.250231 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8678 17:16:52.253305 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
8679 17:16:52.257025 [Gating] SW calibration Done
8680 17:16:52.257656 ==
8681 17:16:52.260170 Dram Type= 6, Freq= 0, CH_1, rank 0
8682 17:16:52.263817 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8683 17:16:52.264526 ==
8684 17:16:52.264999 RX Vref Scan: 0
8685 17:16:52.265385
8686 17:16:52.267206 RX Vref 0 -> 0, step: 1
8687 17:16:52.267819
8688 17:16:52.270196 RX Delay 0 -> 252, step: 8
8689 17:16:52.273776 iDelay=208, Bit 0, Center 143 (88 ~ 199) 112
8690 17:16:52.276633 iDelay=208, Bit 1, Center 131 (80 ~ 183) 104
8691 17:16:52.283466 iDelay=208, Bit 2, Center 127 (72 ~ 183) 112
8692 17:16:52.286611 iDelay=208, Bit 3, Center 139 (88 ~ 191) 104
8693 17:16:52.290026 iDelay=208, Bit 4, Center 135 (80 ~ 191) 112
8694 17:16:52.293094 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
8695 17:16:52.296545 iDelay=208, Bit 6, Center 147 (96 ~ 199) 104
8696 17:16:52.303610 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
8697 17:16:52.306623 iDelay=208, Bit 8, Center 119 (64 ~ 175) 112
8698 17:16:52.310151 iDelay=208, Bit 9, Center 119 (64 ~ 175) 112
8699 17:16:52.313172 iDelay=208, Bit 10, Center 135 (80 ~ 191) 112
8700 17:16:52.316322 iDelay=208, Bit 11, Center 123 (72 ~ 175) 104
8701 17:16:52.322959 iDelay=208, Bit 12, Center 135 (80 ~ 191) 112
8702 17:16:52.326579 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
8703 17:16:52.329985 iDelay=208, Bit 14, Center 139 (88 ~ 191) 104
8704 17:16:52.332997 iDelay=208, Bit 15, Center 139 (88 ~ 191) 104
8705 17:16:52.333465 ==
8706 17:16:52.336104 Dram Type= 6, Freq= 0, CH_1, rank 0
8707 17:16:52.343248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8708 17:16:52.343752 ==
8709 17:16:52.344093 DQS Delay:
8710 17:16:52.346127 DQS0 = 0, DQS1 = 0
8711 17:16:52.346559 DQM Delay:
8712 17:16:52.346896 DQM0 = 138, DQM1 = 131
8713 17:16:52.349765 DQ Delay:
8714 17:16:52.352847 DQ0 =143, DQ1 =131, DQ2 =127, DQ3 =139
8715 17:16:52.356445 DQ4 =135, DQ5 =151, DQ6 =147, DQ7 =135
8716 17:16:52.359494 DQ8 =119, DQ9 =119, DQ10 =135, DQ11 =123
8717 17:16:52.362781 DQ12 =135, DQ13 =139, DQ14 =139, DQ15 =139
8718 17:16:52.363315
8719 17:16:52.363666
8720 17:16:52.363985 ==
8721 17:16:52.366112 Dram Type= 6, Freq= 0, CH_1, rank 0
8722 17:16:52.369210 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8723 17:16:52.372354
8724 17:16:52.372788 ==
8725 17:16:52.373160
8726 17:16:52.373543
8727 17:16:52.373854 TX Vref Scan disable
8728 17:16:52.375841 == TX Byte 0 ==
8729 17:16:52.379421 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8730 17:16:52.382406 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8731 17:16:52.385924
8732 17:16:52.386419 == TX Byte 1 ==
8733 17:16:52.389388 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8734 17:16:52.392534 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8735 17:16:52.395724
8736 17:16:52.396259 ==
8737 17:16:52.398917 Dram Type= 6, Freq= 0, CH_1, rank 0
8738 17:16:52.402145 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8739 17:16:52.402640 ==
8740 17:16:52.414713
8741 17:16:52.418398 TX Vref early break, caculate TX vref
8742 17:16:52.421209 TX Vref=16, minBit 0, minWin=21, winSum=372
8743 17:16:52.424829 TX Vref=18, minBit 0, minWin=22, winSum=381
8744 17:16:52.427746 TX Vref=20, minBit 0, minWin=23, winSum=390
8745 17:16:52.431349 TX Vref=22, minBit 5, minWin=23, winSum=401
8746 17:16:52.434286 TX Vref=24, minBit 0, minWin=23, winSum=410
8747 17:16:52.440872 TX Vref=26, minBit 0, minWin=25, winSum=413
8748 17:16:52.444716 TX Vref=28, minBit 0, minWin=24, winSum=416
8749 17:16:52.448020 TX Vref=30, minBit 5, minWin=23, winSum=409
8750 17:16:52.450700 TX Vref=32, minBit 0, minWin=23, winSum=398
8751 17:16:52.454054 TX Vref=34, minBit 1, minWin=22, winSum=392
8752 17:16:52.460812 [TxChooseVref] Worse bit 0, Min win 25, Win sum 413, Final Vref 26
8753 17:16:52.461258
8754 17:16:52.463706 Final TX Range 0 Vref 26
8755 17:16:52.464148
8756 17:16:52.464494 ==
8757 17:16:52.467491 Dram Type= 6, Freq= 0, CH_1, rank 0
8758 17:16:52.470583 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8759 17:16:52.471031 ==
8760 17:16:52.471383
8761 17:16:52.471713
8762 17:16:52.473847
8763 17:16:52.474288 TX Vref Scan disable
8764 17:16:52.480326 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
8765 17:16:52.480778 == TX Byte 0 ==
8766 17:16:52.483458 u2DelayCellOfst[0]=14 cells (4 PI)
8767 17:16:52.486943 u2DelayCellOfst[1]=11 cells (3 PI)
8768 17:16:52.490040 u2DelayCellOfst[2]=0 cells (0 PI)
8769 17:16:52.493379 u2DelayCellOfst[3]=3 cells (1 PI)
8770 17:16:52.497147 u2DelayCellOfst[4]=7 cells (2 PI)
8771 17:16:52.500269 u2DelayCellOfst[5]=18 cells (5 PI)
8772 17:16:52.503568 u2DelayCellOfst[6]=18 cells (5 PI)
8773 17:16:52.506465 u2DelayCellOfst[7]=7 cells (2 PI)
8774 17:16:52.510069 Update DQ dly =977 (3 ,6, 17) DQ OEN =(3 ,3)
8775 17:16:52.513077 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8776 17:16:52.516502 == TX Byte 1 ==
8777 17:16:52.519881 u2DelayCellOfst[8]=0 cells (0 PI)
8778 17:16:52.522917 u2DelayCellOfst[9]=3 cells (1 PI)
8779 17:16:52.526625 u2DelayCellOfst[10]=11 cells (3 PI)
8780 17:16:52.529640 u2DelayCellOfst[11]=3 cells (1 PI)
8781 17:16:52.532865 u2DelayCellOfst[12]=14 cells (4 PI)
8782 17:16:52.533316 u2DelayCellOfst[13]=18 cells (5 PI)
8783 17:16:52.536370
8784 17:16:52.536828 u2DelayCellOfst[14]=18 cells (5 PI)
8785 17:16:52.539416 u2DelayCellOfst[15]=18 cells (5 PI)
8786 17:16:52.546249 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8787 17:16:52.549870 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
8788 17:16:52.550322 DramC Write-DBI on
8789 17:16:52.552894
8790 17:16:52.553357 ==
8791 17:16:52.556819 Dram Type= 6, Freq= 0, CH_1, rank 0
8792 17:16:52.559656 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8793 17:16:52.560103 ==
8794 17:16:52.560454
8795 17:16:52.560866
8796 17:16:52.562757 TX Vref Scan disable
8797 17:16:52.563278 == TX Byte 0 ==
8798 17:16:52.569438 Update DQM dly =720 (2 ,6, 16) DQM OEN =(3 ,3)
8799 17:16:52.569893 == TX Byte 1 ==
8800 17:16:52.572386 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8801 17:16:52.575715 DramC Write-DBI off
8802 17:16:52.576173
8803 17:16:52.576521 [DATLAT]
8804 17:16:52.579211 Freq=1600, CH1 RK0
8805 17:16:52.579669
8806 17:16:52.580022 DATLAT Default: 0xf
8807 17:16:52.582824 0, 0xFFFF, sum = 0
8808 17:16:52.583298 1, 0xFFFF, sum = 0
8809 17:16:52.585937 2, 0xFFFF, sum = 0
8810 17:16:52.586434 3, 0xFFFF, sum = 0
8811 17:16:52.589011 4, 0xFFFF, sum = 0
8812 17:16:52.589490 5, 0xFFFF, sum = 0
8813 17:16:52.592402
8814 17:16:52.592835 6, 0xFFFF, sum = 0
8815 17:16:52.595906 7, 0xFFFF, sum = 0
8816 17:16:52.596344 8, 0xFFFF, sum = 0
8817 17:16:52.599151 9, 0xFFFF, sum = 0
8818 17:16:52.599594 10, 0xFFFF, sum = 0
8819 17:16:52.602237 11, 0xFFFF, sum = 0
8820 17:16:52.602677 12, 0xFFFF, sum = 0
8821 17:16:52.605650 13, 0xFFFF, sum = 0
8822 17:16:52.606171 14, 0x0, sum = 1
8823 17:16:52.609051 15, 0x0, sum = 2
8824 17:16:52.609568 16, 0x0, sum = 3
8825 17:16:52.612046 17, 0x0, sum = 4
8826 17:16:52.612661 best_step = 15
8827 17:16:52.613112
8828 17:16:52.613486 ==
8829 17:16:52.615474 Dram Type= 6, Freq= 0, CH_1, rank 0
8830 17:16:52.618853 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8831 17:16:52.622433 ==
8832 17:16:52.622874 RX Vref Scan: 1
8833 17:16:52.623223
8834 17:16:52.625385 Set Vref Range= 24 -> 127
8835 17:16:52.625833
8836 17:16:52.628387 RX Vref 24 -> 127, step: 1
8837 17:16:52.628831
8838 17:16:52.629182 RX Delay 19 -> 252, step: 4
8839 17:16:52.629563
8840 17:16:52.631973 Set Vref, RX VrefLevel [Byte0]: 24
8841 17:16:52.635149 [Byte1]: 24
8842 17:16:52.639093
8843 17:16:52.639536 Set Vref, RX VrefLevel [Byte0]: 25
8844 17:16:52.642422 [Byte1]: 25
8845 17:16:52.647092
8846 17:16:52.647534 Set Vref, RX VrefLevel [Byte0]: 26
8847 17:16:52.650055 [Byte1]: 26
8848 17:16:52.654256
8849 17:16:52.654694 Set Vref, RX VrefLevel [Byte0]: 27
8850 17:16:52.657739 [Byte1]: 27
8851 17:16:52.661887
8852 17:16:52.662322 Set Vref, RX VrefLevel [Byte0]: 28
8853 17:16:52.665038 [Byte1]: 28
8854 17:16:52.669583
8855 17:16:52.670019 Set Vref, RX VrefLevel [Byte0]: 29
8856 17:16:52.672846 [Byte1]: 29
8857 17:16:52.677682
8858 17:16:52.678224 Set Vref, RX VrefLevel [Byte0]: 30
8859 17:16:52.680530 [Byte1]: 30
8860 17:16:52.684409
8861 17:16:52.684849 Set Vref, RX VrefLevel [Byte0]: 31
8862 17:16:52.688060 [Byte1]: 31
8863 17:16:52.692160
8864 17:16:52.692680 Set Vref, RX VrefLevel [Byte0]: 32
8865 17:16:52.695724 [Byte1]: 32
8866 17:16:52.699779
8867 17:16:52.700219 Set Vref, RX VrefLevel [Byte0]: 33
8868 17:16:52.703244 [Byte1]: 33
8869 17:16:52.707084
8870 17:16:52.707537 Set Vref, RX VrefLevel [Byte0]: 34
8871 17:16:52.710600 [Byte1]: 34
8872 17:16:52.714790
8873 17:16:52.718151 Set Vref, RX VrefLevel [Byte0]: 35
8874 17:16:52.721122 [Byte1]: 35
8875 17:16:52.721617
8876 17:16:52.724688 Set Vref, RX VrefLevel [Byte0]: 36
8877 17:16:52.727702 [Byte1]: 36
8878 17:16:52.728145
8879 17:16:52.731350 Set Vref, RX VrefLevel [Byte0]: 37
8880 17:16:52.734485 [Byte1]: 37
8881 17:16:52.734936
8882 17:16:52.737917
8883 17:16:52.738372 Set Vref, RX VrefLevel [Byte0]: 38
8884 17:16:52.741006 [Byte1]: 38
8885 17:16:52.745042
8886 17:16:52.745531 Set Vref, RX VrefLevel [Byte0]: 39
8887 17:16:52.748518 [Byte1]: 39
8888 17:16:52.751756
8889 17:16:52.752198
8890 17:16:52.754659 Set Vref, RX VrefLevel [Byte0]: 40
8891 17:16:52.758240 [Byte1]: 40
8892 17:16:52.758698
8893 17:16:52.761349 Set Vref, RX VrefLevel [Byte0]: 41
8894 17:16:52.765144 [Byte1]: 41
8895 17:16:52.765695
8896 17:16:52.768118 Set Vref, RX VrefLevel [Byte0]: 42
8897 17:16:52.771889 [Byte1]: 42
8898 17:16:52.775805
8899 17:16:52.776346 Set Vref, RX VrefLevel [Byte0]: 43
8900 17:16:52.778918 [Byte1]: 43
8901 17:16:52.783168
8902 17:16:52.783612 Set Vref, RX VrefLevel [Byte0]: 44
8903 17:16:52.786711 [Byte1]: 44
8904 17:16:52.790593
8905 17:16:52.791057 Set Vref, RX VrefLevel [Byte0]: 45
8906 17:16:52.793849 [Byte1]: 45
8907 17:16:52.798146
8908 17:16:52.798584 Set Vref, RX VrefLevel [Byte0]: 46
8909 17:16:52.801971 [Byte1]: 46
8910 17:16:52.805917
8911 17:16:52.806415 Set Vref, RX VrefLevel [Byte0]: 47
8912 17:16:52.808820 [Byte1]: 47
8913 17:16:52.813415
8914 17:16:52.813848 Set Vref, RX VrefLevel [Byte0]: 48
8915 17:16:52.816426 [Byte1]: 48
8916 17:16:52.821012
8917 17:16:52.821481 Set Vref, RX VrefLevel [Byte0]: 49
8918 17:16:52.824168 [Byte1]: 49
8919 17:16:52.828872
8920 17:16:52.829307 Set Vref, RX VrefLevel [Byte0]: 50
8921 17:16:52.831766 [Byte1]: 50
8922 17:16:52.836362
8923 17:16:52.836808 Set Vref, RX VrefLevel [Byte0]: 51
8924 17:16:52.839119 [Byte1]: 51
8925 17:16:52.843651
8926 17:16:52.844084 Set Vref, RX VrefLevel [Byte0]: 52
8927 17:16:52.846648 [Byte1]: 52
8928 17:16:52.851417
8929 17:16:52.851976 Set Vref, RX VrefLevel [Byte0]: 53
8930 17:16:52.854575 [Byte1]: 53
8931 17:16:52.858741
8932 17:16:52.859220 Set Vref, RX VrefLevel [Byte0]: 54
8933 17:16:52.862405 [Byte1]: 54
8934 17:16:52.866495
8935 17:16:52.867030 Set Vref, RX VrefLevel [Byte0]: 55
8936 17:16:52.869524 [Byte1]: 55
8937 17:16:52.873930
8938 17:16:52.874460 Set Vref, RX VrefLevel [Byte0]: 56
8939 17:16:52.877404 [Byte1]: 56
8940 17:16:52.881608
8941 17:16:52.882076 Set Vref, RX VrefLevel [Byte0]: 57
8942 17:16:52.884700 [Byte1]: 57
8943 17:16:52.889255
8944 17:16:52.889770 Set Vref, RX VrefLevel [Byte0]: 58
8945 17:16:52.892482 [Byte1]: 58
8946 17:16:52.897202
8947 17:16:52.897766 Set Vref, RX VrefLevel [Byte0]: 59
8948 17:16:52.899778 [Byte1]: 59
8949 17:16:52.904035
8950 17:16:52.904546 Set Vref, RX VrefLevel [Byte0]: 60
8951 17:16:52.907407 [Byte1]: 60
8952 17:16:52.912083
8953 17:16:52.912623 Set Vref, RX VrefLevel [Byte0]: 61
8954 17:16:52.914954 [Byte1]: 61
8955 17:16:52.919439
8956 17:16:52.919939 Set Vref, RX VrefLevel [Byte0]: 62
8957 17:16:52.922592 [Byte1]: 62
8958 17:16:52.927008
8959 17:16:52.927445 Set Vref, RX VrefLevel [Byte0]: 63
8960 17:16:52.930156 [Byte1]: 63
8961 17:16:52.934671
8962 17:16:52.935163 Set Vref, RX VrefLevel [Byte0]: 64
8963 17:16:52.937841 [Byte1]: 64
8964 17:16:52.941874
8965 17:16:52.942308 Set Vref, RX VrefLevel [Byte0]: 65
8966 17:16:52.945422 [Byte1]: 65
8967 17:16:52.949439
8968 17:16:52.949874 Set Vref, RX VrefLevel [Byte0]: 66
8969 17:16:52.953222 [Byte1]: 66
8970 17:16:52.957172
8971 17:16:52.957685 Set Vref, RX VrefLevel [Byte0]: 67
8972 17:16:52.960597 [Byte1]: 67
8973 17:16:52.964746
8974 17:16:52.965228 Set Vref, RX VrefLevel [Byte0]: 68
8975 17:16:52.968398 [Byte1]: 68
8976 17:16:52.972511
8977 17:16:52.972992 Set Vref, RX VrefLevel [Byte0]: 69
8978 17:16:52.975561 [Byte1]: 69
8979 17:16:52.980171
8980 17:16:52.980714 Set Vref, RX VrefLevel [Byte0]: 70
8981 17:16:52.983349 [Byte1]: 70
8982 17:16:52.987534
8983 17:16:52.988065 Set Vref, RX VrefLevel [Byte0]: 71
8984 17:16:52.990571 [Byte1]: 71
8985 17:16:52.995122
8986 17:16:52.995588 Set Vref, RX VrefLevel [Byte0]: 72
8987 17:16:52.998584 [Byte1]: 72
8988 17:16:53.002779
8989 17:16:53.003362 Set Vref, RX VrefLevel [Byte0]: 73
8990 17:16:53.005989 [Byte1]: 73
8991 17:16:53.010039
8992 17:16:53.010544 Final RX Vref Byte 0 = 52 to rank0
8993 17:16:53.013506 Final RX Vref Byte 1 = 58 to rank0
8994 17:16:53.016765 Final RX Vref Byte 0 = 52 to rank1
8995 17:16:53.019896 Final RX Vref Byte 1 = 58 to rank1==
8996 17:16:53.023203 Dram Type= 6, Freq= 0, CH_1, rank 0
8997 17:16:53.029931 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8998 17:16:53.030413 ==
8999 17:16:53.030765 DQS Delay:
9000 17:16:53.033230 DQS0 = 0, DQS1 = 0
9001 17:16:53.033738 DQM Delay:
9002 17:16:53.034094 DQM0 = 134, DQM1 = 129
9003 17:16:53.036480 DQ Delay:
9004 17:16:53.039525 DQ0 =142, DQ1 =128, DQ2 =124, DQ3 =132
9005 17:16:53.043419 DQ4 =132, DQ5 =148, DQ6 =144, DQ7 =128
9006 17:16:53.046191 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =118
9007 17:16:53.049513 DQ12 =136, DQ13 =138, DQ14 =138, DQ15 =138
9008 17:16:53.049961
9009 17:16:53.050360
9010 17:16:53.050748
9011 17:16:53.052881 [DramC_TX_OE_Calibration] TA2
9012 17:16:53.056822 Original DQ_B0 (3 6) =30, OEN = 27
9013 17:16:53.059736 Original DQ_B1 (3 6) =30, OEN = 27
9014 17:16:53.062568 24, 0x0, End_B0=24 End_B1=24
9015 17:16:53.065926 25, 0x0, End_B0=25 End_B1=25
9016 17:16:53.066375 26, 0x0, End_B0=26 End_B1=26
9017 17:16:53.069467 27, 0x0, End_B0=27 End_B1=27
9018 17:16:53.072549 28, 0x0, End_B0=28 End_B1=28
9019 17:16:53.075843 29, 0x0, End_B0=29 End_B1=29
9020 17:16:53.076293 30, 0x0, End_B0=30 End_B1=30
9021 17:16:53.079622 31, 0x4141, End_B0=30 End_B1=30
9022 17:16:53.082730 Byte0 end_step=30 best_step=27
9023 17:16:53.085990 Byte1 end_step=30 best_step=27
9024 17:16:53.089214 Byte0 TX OE(2T, 0.5T) = (3, 3)
9025 17:16:53.092450 Byte1 TX OE(2T, 0.5T) = (3, 3)
9026 17:16:53.092890
9027 17:16:53.093241
9028 17:16:53.099422 [DQSOSCAuto] RK0, (LSB)MR18= 0x190e, (MSB)MR19= 0x303, tDQSOscB0 = 402 ps tDQSOscB1 = 397 ps
9029 17:16:53.102531 CH1 RK0: MR19=303, MR18=190E
9030 17:16:53.108772 CH1_RK0: MR19=0x303, MR18=0x190E, DQSOSC=397, MR23=63, INC=23, DEC=15
9031 17:16:53.109229
9032 17:16:53.112149 ----->DramcWriteLeveling(PI) begin...
9033 17:16:53.112607 ==
9034 17:16:53.115441 Dram Type= 6, Freq= 0, CH_1, rank 1
9035 17:16:53.118757 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9036 17:16:53.119202 ==
9037 17:16:53.122302 Write leveling (Byte 0): 25 => 25
9038 17:16:53.125538 Write leveling (Byte 1): 27 => 27
9039 17:16:53.128821 DramcWriteLeveling(PI) end<-----
9040 17:16:53.129260
9041 17:16:53.129678 ==
9042 17:16:53.132452 Dram Type= 6, Freq= 0, CH_1, rank 1
9043 17:16:53.135467 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9044 17:16:53.138852
9045 17:16:53.139311 ==
9046 17:16:53.139760 [Gating] SW mode calibration
9047 17:16:53.148400 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
9048 17:16:53.152201 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
9049 17:16:53.155135 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9050 17:16:53.161819 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9051 17:16:53.165095 1 4 8 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
9052 17:16:53.168631 1 4 12 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
9053 17:16:53.175039 1 4 16 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
9054 17:16:53.178344 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
9055 17:16:53.181862 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
9056 17:16:53.188499 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
9057 17:16:53.191747 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
9058 17:16:53.194765 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
9059 17:16:53.201859 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 0) (1 1)
9060 17:16:53.204571 1 5 12 | B1->B0 | 2525 3333 | 0 1 | (1 0) (1 0)
9061 17:16:53.207890 1 5 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9062 17:16:53.214833 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9063 17:16:53.217798 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9064 17:16:53.221448 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9065 17:16:53.227999 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9066 17:16:53.231448 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
9067 17:16:53.234486 1 6 8 | B1->B0 | 2e2d 2323 | 1 0 | (0 0) (0 0)
9068 17:16:53.241143 1 6 12 | B1->B0 | 4646 2929 | 0 0 | (0 0) (0 0)
9069 17:16:53.244213 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9070 17:16:53.247611 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9071 17:16:53.254587 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9072 17:16:53.257654 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9073 17:16:53.260933 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9074 17:16:53.267717 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9075 17:16:53.270606 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 0)
9076 17:16:53.274189 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
9077 17:16:53.280677 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 1)
9078 17:16:53.283889 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9079 17:16:53.286910 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9080 17:16:53.293571 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9081 17:16:53.296696 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9082 17:16:53.300208 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9083 17:16:53.306648 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9084 17:16:53.309721 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9085 17:16:53.313126 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9086 17:16:53.316197
9087 17:16:53.320041 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9088 17:16:53.322939 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9089 17:16:53.326486 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9090 17:16:53.333437 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9091 17:16:53.336563 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
9092 17:16:53.339980 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
9093 17:16:53.346142 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
9094 17:16:53.349767 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
9095 17:16:53.352943 Total UI for P1: 0, mck2ui 16
9096 17:16:53.356127 best dqsien dly found for B0: ( 1, 9, 10)
9097 17:16:53.359321 Total UI for P1: 0, mck2ui 16
9098 17:16:53.362679 best dqsien dly found for B1: ( 1, 9, 10)
9099 17:16:53.366267 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
9100 17:16:53.369199 best DQS1 dly(MCK, UI, PI) = (1, 9, 10)
9101 17:16:53.369674
9102 17:16:53.372906 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
9103 17:16:53.379234 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 10)
9104 17:16:53.379793 [Gating] SW calibration Done
9105 17:16:53.382583 ==
9106 17:16:53.383029 Dram Type= 6, Freq= 0, CH_1, rank 1
9107 17:16:53.385666
9108 17:16:53.389502 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9109 17:16:53.390058 ==
9110 17:16:53.390414 RX Vref Scan: 0
9111 17:16:53.390738
9112 17:16:53.392298 RX Vref 0 -> 0, step: 1
9113 17:16:53.392738
9114 17:16:53.395486 RX Delay 0 -> 252, step: 8
9115 17:16:53.398916 iDelay=208, Bit 0, Center 139 (80 ~ 199) 120
9116 17:16:53.402339 iDelay=208, Bit 1, Center 131 (72 ~ 191) 120
9117 17:16:53.406011 iDelay=208, Bit 2, Center 123 (64 ~ 183) 120
9118 17:16:53.412416 iDelay=208, Bit 3, Center 135 (80 ~ 191) 112
9119 17:16:53.415372 iDelay=208, Bit 4, Center 131 (72 ~ 191) 120
9120 17:16:53.419260 iDelay=208, Bit 5, Center 151 (96 ~ 207) 112
9121 17:16:53.422073 iDelay=208, Bit 6, Center 147 (88 ~ 207) 120
9122 17:16:53.425012 iDelay=208, Bit 7, Center 135 (80 ~ 191) 112
9123 17:16:53.431903 iDelay=208, Bit 8, Center 115 (56 ~ 175) 120
9124 17:16:53.434925 iDelay=208, Bit 9, Center 115 (56 ~ 175) 120
9125 17:16:53.438606 iDelay=208, Bit 10, Center 131 (72 ~ 191) 120
9126 17:16:53.442130 iDelay=208, Bit 11, Center 119 (64 ~ 175) 112
9127 17:16:53.445142 iDelay=208, Bit 12, Center 139 (80 ~ 199) 120
9128 17:16:53.448714
9129 17:16:53.451684 iDelay=208, Bit 13, Center 139 (80 ~ 199) 120
9130 17:16:53.455013 iDelay=208, Bit 14, Center 135 (72 ~ 199) 128
9131 17:16:53.458499 iDelay=208, Bit 15, Center 139 (80 ~ 199) 120
9132 17:16:53.458965 ==
9133 17:16:53.461562 Dram Type= 6, Freq= 0, CH_1, rank 1
9134 17:16:53.465055 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9135 17:16:53.468183
9136 17:16:53.468624 ==
9137 17:16:53.468972 DQS Delay:
9138 17:16:53.469381 DQS0 = 0, DQS1 = 0
9139 17:16:53.471439 DQM Delay:
9140 17:16:53.471883 DQM0 = 136, DQM1 = 129
9141 17:16:53.474636 DQ Delay:
9142 17:16:53.477757 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
9143 17:16:53.481432 DQ4 =131, DQ5 =151, DQ6 =147, DQ7 =135
9144 17:16:53.484429 DQ8 =115, DQ9 =115, DQ10 =131, DQ11 =119
9145 17:16:53.488089 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
9146 17:16:53.488534
9147 17:16:53.488881
9148 17:16:53.489211 ==
9149 17:16:53.491097 Dram Type= 6, Freq= 0, CH_1, rank 1
9150 17:16:53.494827 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9151 17:16:53.497769 ==
9152 17:16:53.498305
9153 17:16:53.498662
9154 17:16:53.498988 TX Vref Scan disable
9155 17:16:53.501229 == TX Byte 0 ==
9156 17:16:53.504520 Update DQ dly =983 (3 ,6, 23) DQ OEN =(3 ,3)
9157 17:16:53.507941 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9158 17:16:53.510867 == TX Byte 1 ==
9159 17:16:53.514351 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
9160 17:16:53.517642 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9161 17:16:53.520760
9162 17:16:53.521201 ==
9163 17:16:53.524158 Dram Type= 6, Freq= 0, CH_1, rank 1
9164 17:16:53.527387 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9165 17:16:53.527829 ==
9166 17:16:53.540104
9167 17:16:53.543047 TX Vref early break, caculate TX vref
9168 17:16:53.546458 TX Vref=16, minBit 0, minWin=22, winSum=386
9169 17:16:53.549867 TX Vref=18, minBit 0, minWin=23, winSum=396
9170 17:16:53.552965 TX Vref=20, minBit 0, minWin=24, winSum=406
9171 17:16:53.556507 TX Vref=22, minBit 0, minWin=25, winSum=413
9172 17:16:53.559732 TX Vref=24, minBit 13, minWin=25, winSum=421
9173 17:16:53.566273 TX Vref=26, minBit 13, minWin=25, winSum=424
9174 17:16:53.569110 TX Vref=28, minBit 0, minWin=25, winSum=425
9175 17:16:53.572828 TX Vref=30, minBit 0, minWin=25, winSum=419
9176 17:16:53.576068 TX Vref=32, minBit 0, minWin=24, winSum=412
9177 17:16:53.579307 TX Vref=34, minBit 0, minWin=23, winSum=398
9178 17:16:53.585684 [TxChooseVref] Worse bit 0, Min win 25, Win sum 425, Final Vref 28
9179 17:16:53.585818
9180 17:16:53.589179 Final TX Range 0 Vref 28
9181 17:16:53.589303
9182 17:16:53.589401 ==
9183 17:16:53.592195 Dram Type= 6, Freq= 0, CH_1, rank 1
9184 17:16:53.596237 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9185 17:16:53.596441 ==
9186 17:16:53.596559
9187 17:16:53.596664
9188 17:16:53.598872 TX Vref Scan disable
9189 17:16:53.605938 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =262/100 ps
9190 17:16:53.606191 == TX Byte 0 ==
9191 17:16:53.608841 u2DelayCellOfst[0]=18 cells (5 PI)
9192 17:16:53.612250 u2DelayCellOfst[1]=14 cells (4 PI)
9193 17:16:53.615942 u2DelayCellOfst[2]=0 cells (0 PI)
9194 17:16:53.618920 u2DelayCellOfst[3]=7 cells (2 PI)
9195 17:16:53.622123 u2DelayCellOfst[4]=11 cells (3 PI)
9196 17:16:53.625649 u2DelayCellOfst[5]=22 cells (6 PI)
9197 17:16:53.628776 u2DelayCellOfst[6]=22 cells (6 PI)
9198 17:16:53.632205 u2DelayCellOfst[7]=7 cells (2 PI)
9199 17:16:53.635989 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9200 17:16:53.638762 Update DQM dly =983 (3 ,6, 23) DQM OEN =(3 ,3)
9201 17:16:53.642193 == TX Byte 1 ==
9202 17:16:53.645407 u2DelayCellOfst[8]=0 cells (0 PI)
9203 17:16:53.648594 u2DelayCellOfst[9]=3 cells (1 PI)
9204 17:16:53.652410 u2DelayCellOfst[10]=11 cells (3 PI)
9205 17:16:53.652854 u2DelayCellOfst[11]=7 cells (2 PI)
9206 17:16:53.655219 u2DelayCellOfst[12]=18 cells (5 PI)
9207 17:16:53.659077 u2DelayCellOfst[13]=18 cells (5 PI)
9208 17:16:53.661911 u2DelayCellOfst[14]=18 cells (5 PI)
9209 17:16:53.665458 u2DelayCellOfst[15]=18 cells (5 PI)
9210 17:16:53.672053 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
9211 17:16:53.674917 Update DQM dly =981 (3 ,6, 21) DQM OEN =(3 ,3)
9212 17:16:53.675362 DramC Write-DBI on
9213 17:16:53.678454 ==
9214 17:16:53.678967 Dram Type= 6, Freq= 0, CH_1, rank 1
9215 17:16:53.681441
9216 17:16:53.684805 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9217 17:16:53.685240 ==
9218 17:16:53.685638
9219 17:16:53.685979
9220 17:16:53.688149 TX Vref Scan disable
9221 17:16:53.688593 == TX Byte 0 ==
9222 17:16:53.694776 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
9223 17:16:53.695236 == TX Byte 1 ==
9224 17:16:53.697967 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9225 17:16:53.701109 DramC Write-DBI off
9226 17:16:53.701579
9227 17:16:53.701941 [DATLAT]
9228 17:16:53.704654 Freq=1600, CH1 RK1
9229 17:16:53.705088
9230 17:16:53.705465 DATLAT Default: 0xf
9231 17:16:53.707841 0, 0xFFFF, sum = 0
9232 17:16:53.708282 1, 0xFFFF, sum = 0
9233 17:16:53.711416 2, 0xFFFF, sum = 0
9234 17:16:53.711873 3, 0xFFFF, sum = 0
9235 17:16:53.714421 4, 0xFFFF, sum = 0
9236 17:16:53.714860 5, 0xFFFF, sum = 0
9237 17:16:53.717725
9238 17:16:53.718176 6, 0xFFFF, sum = 0
9239 17:16:53.721354 7, 0xFFFF, sum = 0
9240 17:16:53.721799 8, 0xFFFF, sum = 0
9241 17:16:53.724519 9, 0xFFFF, sum = 0
9242 17:16:53.724962 10, 0xFFFF, sum = 0
9243 17:16:53.727621 11, 0xFFFF, sum = 0
9244 17:16:53.728060 12, 0xFFFF, sum = 0
9245 17:16:53.730976 13, 0xFFFF, sum = 0
9246 17:16:53.731418 14, 0x0, sum = 1
9247 17:16:53.734384 15, 0x0, sum = 2
9248 17:16:53.734826 16, 0x0, sum = 3
9249 17:16:53.738149 17, 0x0, sum = 4
9250 17:16:53.738663 best_step = 15
9251 17:16:53.739009
9252 17:16:53.739347 ==
9253 17:16:53.741003 Dram Type= 6, Freq= 0, CH_1, rank 1
9254 17:16:53.744461 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9255 17:16:53.744945 ==
9256 17:16:53.747453
9257 17:16:53.747934 RX Vref Scan: 0
9258 17:16:53.748273
9259 17:16:53.750660 RX Vref 0 -> 0, step: 1
9260 17:16:53.751193
9261 17:16:53.751643 RX Delay 11 -> 252, step: 4
9262 17:16:53.758405 iDelay=203, Bit 0, Center 138 (87 ~ 190) 104
9263 17:16:53.761420 iDelay=203, Bit 1, Center 128 (75 ~ 182) 108
9264 17:16:53.764988 iDelay=203, Bit 2, Center 122 (67 ~ 178) 112
9265 17:16:53.768128 iDelay=203, Bit 3, Center 130 (79 ~ 182) 104
9266 17:16:53.771615 iDelay=203, Bit 4, Center 134 (79 ~ 190) 112
9267 17:16:53.774934
9268 17:16:53.778053 iDelay=203, Bit 5, Center 146 (95 ~ 198) 104
9269 17:16:53.781667 iDelay=203, Bit 6, Center 146 (91 ~ 202) 112
9270 17:16:53.784762 iDelay=203, Bit 7, Center 130 (79 ~ 182) 104
9271 17:16:53.788265 iDelay=203, Bit 8, Center 112 (55 ~ 170) 116
9272 17:16:53.791384 iDelay=203, Bit 9, Center 116 (63 ~ 170) 108
9273 17:16:53.794497
9274 17:16:53.798178 iDelay=203, Bit 10, Center 126 (71 ~ 182) 112
9275 17:16:53.801128 iDelay=203, Bit 11, Center 116 (63 ~ 170) 108
9276 17:16:53.804892 iDelay=203, Bit 12, Center 136 (79 ~ 194) 116
9277 17:16:53.807731 iDelay=203, Bit 13, Center 136 (83 ~ 190) 108
9278 17:16:53.814794 iDelay=203, Bit 14, Center 132 (75 ~ 190) 116
9279 17:16:53.817902 iDelay=203, Bit 15, Center 138 (83 ~ 194) 112
9280 17:16:53.818350 ==
9281 17:16:53.820973 Dram Type= 6, Freq= 0, CH_1, rank 1
9282 17:16:53.824274 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9283 17:16:53.824722 ==
9284 17:16:53.828167 DQS Delay:
9285 17:16:53.828609 DQS0 = 0, DQS1 = 0
9286 17:16:53.828955 DQM Delay:
9287 17:16:53.830764 DQM0 = 134, DQM1 = 126
9288 17:16:53.831207 DQ Delay:
9289 17:16:53.834379 DQ0 =138, DQ1 =128, DQ2 =122, DQ3 =130
9290 17:16:53.837419 DQ4 =134, DQ5 =146, DQ6 =146, DQ7 =130
9291 17:16:53.843980 DQ8 =112, DQ9 =116, DQ10 =126, DQ11 =116
9292 17:16:53.847217 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =138
9293 17:16:53.847742
9294 17:16:53.848131
9295 17:16:53.848465
9296 17:16:53.850537 [DramC_TX_OE_Calibration] TA2
9297 17:16:53.853936 Original DQ_B0 (3 6) =30, OEN = 27
9298 17:16:53.857519 Original DQ_B1 (3 6) =30, OEN = 27
9299 17:16:53.857959 24, 0x0, End_B0=24 End_B1=24
9300 17:16:53.860687 25, 0x0, End_B0=25 End_B1=25
9301 17:16:53.864195 26, 0x0, End_B0=26 End_B1=26
9302 17:16:53.867395 27, 0x0, End_B0=27 End_B1=27
9303 17:16:53.867892 28, 0x0, End_B0=28 End_B1=28
9304 17:16:53.870540 29, 0x0, End_B0=29 End_B1=29
9305 17:16:53.873992 30, 0x0, End_B0=30 End_B1=30
9306 17:16:53.877107 31, 0x4141, End_B0=30 End_B1=30
9307 17:16:53.880838 Byte0 end_step=30 best_step=27
9308 17:16:53.883536 Byte1 end_step=30 best_step=27
9309 17:16:53.884085 Byte0 TX OE(2T, 0.5T) = (3, 3)
9310 17:16:53.887106 Byte1 TX OE(2T, 0.5T) = (3, 3)
9311 17:16:53.887548
9312 17:16:53.887894
9313 17:16:53.896964 [DQSOSCAuto] RK1, (LSB)MR18= 0xe09, (MSB)MR19= 0x303, tDQSOscB0 = 405 ps tDQSOscB1 = 402 ps
9314 17:16:53.900119 CH1 RK1: MR19=303, MR18=E09
9315 17:16:53.903766 CH1_RK1: MR19=0x303, MR18=0xE09, DQSOSC=402, MR23=63, INC=22, DEC=15
9316 17:16:53.906629 [RxdqsGatingPostProcess] freq 1600
9317 17:16:53.913312 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9318 17:16:53.916762 best DQS0 dly(2T, 0.5T) = (1, 1)
9319 17:16:53.920226 best DQS1 dly(2T, 0.5T) = (1, 1)
9320 17:16:53.923404 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9321 17:16:53.926525 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9322 17:16:53.930196 best DQS0 dly(2T, 0.5T) = (1, 1)
9323 17:16:53.930641 best DQS1 dly(2T, 0.5T) = (1, 1)
9324 17:16:53.933125 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9325 17:16:53.936666 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9326 17:16:53.939911 Pre-setting of DQS Precalculation
9327 17:16:53.946534 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9328 17:16:53.953112 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9329 17:16:53.959505 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9330 17:16:53.959951
9331 17:16:53.960296
9332 17:16:53.962981 [Calibration Summary] 3200 Mbps
9333 17:16:53.966460 CH 0, Rank 0
9334 17:16:53.966903 SW Impedance : PASS
9335 17:16:53.969568 DUTY Scan : NO K
9336 17:16:53.973115 ZQ Calibration : PASS
9337 17:16:53.973604 Jitter Meter : NO K
9338 17:16:53.976773 CBT Training : PASS
9339 17:16:53.977354 Write leveling : PASS
9340 17:16:53.979499 RX DQS gating : PASS
9341 17:16:53.983034 RX DQ/DQS(RDDQC) : PASS
9342 17:16:53.983505 TX DQ/DQS : PASS
9343 17:16:53.986058 RX DATLAT : PASS
9344 17:16:53.989401 RX DQ/DQS(Engine): PASS
9345 17:16:53.989965 TX OE : PASS
9346 17:16:53.992771 All Pass.
9347 17:16:53.993206
9348 17:16:53.993598 CH 0, Rank 1
9349 17:16:53.995683 SW Impedance : PASS
9350 17:16:53.996212 DUTY Scan : NO K
9351 17:16:53.999453 ZQ Calibration : PASS
9352 17:16:54.002428 Jitter Meter : NO K
9353 17:16:54.002881 CBT Training : PASS
9354 17:16:54.005617 Write leveling : PASS
9355 17:16:54.009153 RX DQS gating : PASS
9356 17:16:54.009756 RX DQ/DQS(RDDQC) : PASS
9357 17:16:54.012308 TX DQ/DQS : PASS
9358 17:16:54.015718 RX DATLAT : PASS
9359 17:16:54.016222 RX DQ/DQS(Engine): PASS
9360 17:16:54.018846 TX OE : PASS
9361 17:16:54.019306 All Pass.
9362 17:16:54.019644
9363 17:16:54.022079 CH 1, Rank 0
9364 17:16:54.022507 SW Impedance : PASS
9365 17:16:54.025471 DUTY Scan : NO K
9366 17:16:54.028677 ZQ Calibration : PASS
9367 17:16:54.029150 Jitter Meter : NO K
9368 17:16:54.032282 CBT Training : PASS
9369 17:16:54.035637 Write leveling : PASS
9370 17:16:54.036181 RX DQS gating : PASS
9371 17:16:54.038790 RX DQ/DQS(RDDQC) : PASS
9372 17:16:54.042267 TX DQ/DQS : PASS
9373 17:16:54.042722 RX DATLAT : PASS
9374 17:16:54.045439 RX DQ/DQS(Engine): PASS
9375 17:16:54.048868 TX OE : PASS
9376 17:16:54.049431 All Pass.
9377 17:16:54.049823
9378 17:16:54.050147 CH 1, Rank 1
9379 17:16:54.051778 SW Impedance : PASS
9380 17:16:54.055129 DUTY Scan : NO K
9381 17:16:54.055556 ZQ Calibration : PASS
9382 17:16:54.058295 Jitter Meter : NO K
9383 17:16:54.058722 CBT Training : PASS
9384 17:16:54.061928 Write leveling : PASS
9385 17:16:54.065131 RX DQS gating : PASS
9386 17:16:54.065636 RX DQ/DQS(RDDQC) : PASS
9387 17:16:54.068721 TX DQ/DQS : PASS
9388 17:16:54.071634 RX DATLAT : PASS
9389 17:16:54.072062 RX DQ/DQS(Engine): PASS
9390 17:16:54.075242 TX OE : PASS
9391 17:16:54.075685 All Pass.
9392 17:16:54.076023
9393 17:16:54.078207 DramC Write-DBI on
9394 17:16:54.081623 PER_BANK_REFRESH: Hybrid Mode
9395 17:16:54.082062 TX_TRACKING: ON
9396 17:16:54.091675 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9397 17:16:54.097929 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9398 17:16:54.104680 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9399 17:16:54.107982
9400 17:16:54.110980 [FAST_K] Save calibration result to emmc
9401 17:16:54.111527 sync common calibartion params.
9402 17:16:54.114644 sync cbt_mode0:1, 1:1
9403 17:16:54.117839 dram_init: ddr_geometry: 2
9404 17:16:54.118577 dram_init: ddr_geometry: 2
9405 17:16:54.121379
9406 17:16:54.121809 dram_init: ddr_geometry: 2
9407 17:16:54.124367 0:dram_rank_size:100000000
9408 17:16:54.127719 1:dram_rank_size:100000000
9409 17:16:54.131030 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9410 17:16:54.134472 DFS_SHUFFLE_HW_MODE: ON
9411 17:16:54.137569 dramc_set_vcore_voltage set vcore to 725000
9412 17:16:54.140817 Read voltage for 1600, 0
9413 17:16:54.141249 Vio18 = 0
9414 17:16:54.144414 Vcore = 725000
9415 17:16:54.144858 Vdram = 0
9416 17:16:54.145228 Vddq = 0
9417 17:16:54.145652 Vmddr = 0
9418 17:16:54.147321 switch to 3200 Mbps bootup
9419 17:16:54.150876 [DramcRunTimeConfig]
9420 17:16:54.151323 PHYPLL
9421 17:16:54.154091 DPM_CONTROL_AFTERK: ON
9422 17:16:54.154544 PER_BANK_REFRESH: ON
9423 17:16:54.157535 REFRESH_OVERHEAD_REDUCTION: ON
9424 17:16:54.160947 CMD_PICG_NEW_MODE: OFF
9425 17:16:54.161485 XRTWTW_NEW_MODE: ON
9426 17:16:54.163736 XRTRTR_NEW_MODE: ON
9427 17:16:54.164167 TX_TRACKING: ON
9428 17:16:54.167412 RDSEL_TRACKING: OFF
9429 17:16:54.170204 DQS Precalculation for DVFS: ON
9430 17:16:54.170288 RX_TRACKING: OFF
9431 17:16:54.173561 HW_GATING DBG: ON
9432 17:16:54.173646 ZQCS_ENABLE_LP4: ON
9433 17:16:54.176592 RX_PICG_NEW_MODE: ON
9434 17:16:54.176676 TX_PICG_NEW_MODE: ON
9435 17:16:54.180261 ENABLE_RX_DCM_DPHY: ON
9436 17:16:54.183533 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9437 17:16:54.186602 DUMMY_READ_FOR_TRACKING: OFF
9438 17:16:54.186690 !!! SPM_CONTROL_AFTERK: OFF
9439 17:16:54.190055 !!! SPM could not control APHY
9440 17:16:54.193627 IMPEDANCE_TRACKING: ON
9441 17:16:54.193739 TEMP_SENSOR: ON
9442 17:16:54.196679 HW_SAVE_FOR_SR: OFF
9443 17:16:54.199900 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9444 17:16:54.203348 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9445 17:16:54.203464 Read ODT Tracking: ON
9446 17:16:54.206389 Refresh Rate DeBounce: ON
9447 17:16:54.210125 DFS_NO_QUEUE_FLUSH: ON
9448 17:16:54.213094 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9449 17:16:54.213179 ENABLE_DFS_RUNTIME_MRW: OFF
9450 17:16:54.216329 DDR_RESERVE_NEW_MODE: ON
9451 17:16:54.219719 MR_CBT_SWITCH_FREQ: ON
9452 17:16:54.219803 =========================
9453 17:16:54.223009
9454 17:16:54.240387 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9455 17:16:54.243281 dram_init: ddr_geometry: 2
9456 17:16:54.261911 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9457 17:16:54.265053 dram_init: dram init end (result: 0)
9458 17:16:54.271546 DRAM-K: Full calibration passed in 24627 msecs
9459 17:16:54.275182 MRC: failed to locate region type 0.
9460 17:16:54.275266 DRAM rank0 size:0x100000000,
9461 17:16:54.278304 DRAM rank1 size=0x100000000
9462 17:16:54.288094 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9463 17:16:54.294574 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9464 17:16:54.301308 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9465 17:16:54.308192 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9466 17:16:54.311502 DRAM rank0 size:0x100000000,
9467 17:16:54.314677 DRAM rank1 size=0x100000000
9468 17:16:54.314764 CBMEM:
9469 17:16:54.318125 IMD: root @ 0xfffff000 254 entries.
9470 17:16:54.321134 IMD: root @ 0xffffec00 62 entries.
9471 17:16:54.324910 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9472 17:16:54.331318 WARNING: RO_VPD is uninitialized or empty.
9473 17:16:54.334645 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9474 17:16:54.338045 WARNING: RW_VPD is uninitialized or empty.
9475 17:16:54.346054 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9476 17:16:54.358246 read SPI 0x42894 0xe01e: 6226 us, 9215 KB/s, 73.720 Mbps
9477 17:16:54.370341 BS: romstage times (exec / console): total (unknown) / 24127 ms
9478 17:16:54.370569
9479 17:16:54.370705
9480 17:16:54.379868 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9481 17:16:54.383527 ARM64: Exception handlers installed.
9482 17:16:54.386374 ARM64: Testing exception
9483 17:16:54.389901 ARM64: Done test exception
9484 17:16:54.390150 Enumerating buses...
9485 17:16:54.393245 Show all devs... Before device enumeration.
9486 17:16:54.395903 Root Device: enabled 1
9487 17:16:54.399596 CPU_CLUSTER: 0: enabled 1
9488 17:16:54.399680 CPU: 00: enabled 1
9489 17:16:54.402559 Compare with tree...
9490 17:16:54.402643 Root Device: enabled 1
9491 17:16:54.406372 CPU_CLUSTER: 0: enabled 1
9492 17:16:54.409163 CPU: 00: enabled 1
9493 17:16:54.409276 Root Device scanning...
9494 17:16:54.412450 scan_static_bus for Root Device
9495 17:16:54.415854 CPU_CLUSTER: 0 enabled
9496 17:16:54.419015 scan_static_bus for Root Device done
9497 17:16:54.422702 scan_bus: bus Root Device finished in 8 msecs
9498 17:16:54.422792 done
9499 17:16:54.429316 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9500 17:16:54.432356 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9501 17:16:54.439265 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9502 17:16:54.445308 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9503 17:16:54.445441 Allocating resources...
9504 17:16:54.449136 Reading resources...
9505 17:16:54.452209 Root Device read_resources bus 0 link: 0
9506 17:16:54.455337 DRAM rank0 size:0x100000000,
9507 17:16:54.455509 DRAM rank1 size=0x100000000
9508 17:16:54.461910 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9509 17:16:54.462146 CPU: 00 missing read_resources
9510 17:16:54.468647 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9511 17:16:54.472578 Root Device read_resources bus 0 link: 0 done
9512 17:16:54.475340 Done reading resources.
9513 17:16:54.478716 Show resources in subtree (Root Device)...After reading.
9514 17:16:54.482317 Root Device child on link 0 CPU_CLUSTER: 0
9515 17:16:54.485753 CPU_CLUSTER: 0 child on link 0 CPU: 00
9516 17:16:54.495597 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9517 17:16:54.496050 CPU: 00
9518 17:16:54.498635 Root Device assign_resources, bus 0 link: 0
9519 17:16:54.502314
9520 17:16:54.502872 CPU_CLUSTER: 0 missing set_resources
9521 17:16:54.508478 Root Device assign_resources, bus 0 link: 0 done
9522 17:16:54.508918 Done setting resources.
9523 17:16:54.515142 Show resources in subtree (Root Device)...After assigning values.
9524 17:16:54.518546 Root Device child on link 0 CPU_CLUSTER: 0
9525 17:16:54.521762 CPU_CLUSTER: 0 child on link 0 CPU: 00
9526 17:16:54.524903
9527 17:16:54.531799 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9528 17:16:54.532240 CPU: 00
9529 17:16:54.534768 Done allocating resources.
9530 17:16:54.541472 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9531 17:16:54.541878 Enabling resources...
9532 17:16:54.545038 done.
9533 17:16:54.548388 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9534 17:16:54.551559 Initializing devices...
9535 17:16:54.551995 Root Device init
9536 17:16:54.554885 init hardware done!
9537 17:16:54.555322 0x00000018: ctrlr->caps
9538 17:16:54.558324 52.000 MHz: ctrlr->f_max
9539 17:16:54.561399 0.400 MHz: ctrlr->f_min
9540 17:16:54.561846 0x40ff8080: ctrlr->voltages
9541 17:16:54.564564 sclk: 390625
9542 17:16:54.565053 Bus Width = 1
9543 17:16:54.567905 sclk: 390625
9544 17:16:54.568379 Bus Width = 1
9545 17:16:54.571063 Early init status = 3
9546 17:16:54.574624 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9547 17:16:54.577817 in-header: 03 fb 00 00 01 00 00 00
9548 17:16:54.581079 in-data: 01
9549 17:16:54.584571 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9550 17:16:54.588320 in-header: 03 fb 00 00 01 00 00 00
9551 17:16:54.591759 in-data: 01
9552 17:16:54.594858 [SSUSB] Setting up USB HOST controller...
9553 17:16:54.598243 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9554 17:16:54.601931 [SSUSB] phy power-on done.
9555 17:16:54.604787 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9556 17:16:54.611473 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9557 17:16:54.614639 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9558 17:16:54.621677 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9559 17:16:54.628261 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9560 17:16:54.634683 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9561 17:16:54.641560 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9562 17:16:54.648378 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9563 17:16:54.651393 SPM: binary array size = 0x9dc
9564 17:16:54.654592 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9565 17:16:54.661395 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9566 17:16:54.667654 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9567 17:16:54.674479 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9568 17:16:54.677510 configure_display: Starting display init
9569 17:16:54.711921 anx7625_power_on_init: Init interface.
9570 17:16:54.715392 anx7625_disable_pd_protocol: Disabled PD feature.
9571 17:16:54.718364 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9572 17:16:54.746480 anx7625_start_dp_work: Secure OCM version=00
9573 17:16:54.749480 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9574 17:16:54.767808 sp_tx_get_edid_block: EDID Block = 1
9575 17:16:54.866912 Extracted contents:
9576 17:16:54.870432 header: 00 ff ff ff ff ff ff 00
9577 17:16:54.873542 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9578 17:16:54.876836 version: 01 04
9579 17:16:54.880589 basic params: 95 1f 11 78 0a
9580 17:16:54.883654 chroma info: 76 90 94 55 54 90 27 21 50 54
9581 17:16:54.887059 established: 00 00 00
9582 17:16:54.893360 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9583 17:16:54.896520 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9584 17:16:54.903115 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9585 17:16:54.909694 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9586 17:16:54.916586 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9587 17:16:54.919654 extensions: 00
9588 17:16:54.920096 checksum: fb
9589 17:16:54.920443
9590 17:16:54.923227 Manufacturer: IVO Model 57d Serial Number 0
9591 17:16:54.926684 Made week 0 of 2020
9592 17:16:54.927127 EDID version: 1.4
9593 17:16:54.929828
9594 17:16:54.930271 Digital display
9595 17:16:54.932862 6 bits per primary color channel
9596 17:16:54.933312 DisplayPort interface
9597 17:16:54.936528 Maximum image size: 31 cm x 17 cm
9598 17:16:54.940027 Gamma: 220%
9599 17:16:54.940470 Check DPMS levels
9600 17:16:54.942739 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9601 17:16:54.949664 First detailed timing is preferred timing
9602 17:16:54.950132 Established timings supported:
9603 17:16:54.953102 Standard timings supported:
9604 17:16:54.956119 Detailed timings
9605 17:16:54.959719 Hex of detail: 383680a07038204018303c0035ae10000019
9606 17:16:54.966243 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9607 17:16:54.969381 0780 0798 07c8 0820 hborder 0
9608 17:16:54.972723 0438 043b 0447 0458 vborder 0
9609 17:16:54.976564 -hsync -vsync
9610 17:16:54.977010 Did detailed timing
9611 17:16:54.982520 Hex of detail: 000000000000000000000000000000000000
9612 17:16:54.986139 Manufacturer-specified data, tag 0
9613 17:16:54.989711 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9614 17:16:54.992690 ASCII string: InfoVision
9615 17:16:54.996411 Hex of detail: 000000fe00523134304e574635205248200a
9616 17:16:54.999627 ASCII string: R140NWF5 RH
9617 17:16:55.000187 Checksum
9618 17:16:55.003104 Checksum: 0xfb (valid)
9619 17:16:55.006585 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9620 17:16:55.009156 DSI data_rate: 832800000 bps
9621 17:16:55.015728 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9622 17:16:55.018795 anx7625_parse_edid: pixelclock(138800).
9623 17:16:55.022602 hactive(1920), hsync(48), hfp(24), hbp(88)
9624 17:16:55.025517 vactive(1080), vsync(12), vfp(3), vbp(17)
9625 17:16:55.028795 anx7625_dsi_config: config dsi.
9626 17:16:55.035375 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9627 17:16:55.049432 anx7625_dsi_config: success to config DSI
9628 17:16:55.052361 anx7625_dp_start: MIPI phy setup OK.
9629 17:16:55.056023 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9630 17:16:55.058957 mtk_ddp_mode_set invalid vrefresh 60
9631 17:16:55.062336 main_disp_path_setup
9632 17:16:55.062779 ovl_layer_smi_id_en
9633 17:16:55.065830 ovl_layer_smi_id_en
9634 17:16:55.066273 ccorr_config
9635 17:16:55.066620 aal_config
9636 17:16:55.068780 gamma_config
9637 17:16:55.069275 postmask_config
9638 17:16:55.072691 dither_config
9639 17:16:55.075510 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9640 17:16:55.081953 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9641 17:16:55.085369 Root Device init finished in 530 msecs
9642 17:16:55.088817 CPU_CLUSTER: 0 init
9643 17:16:55.095466 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9644 17:16:55.101887 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9645 17:16:55.102327 APU_MBOX 0x190000b0 = 0x10001
9646 17:16:55.105076 APU_MBOX 0x190001b0 = 0x10001
9647 17:16:55.108400 APU_MBOX 0x190005b0 = 0x10001
9648 17:16:55.111523 APU_MBOX 0x190006b0 = 0x10001
9649 17:16:55.118128 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9650 17:16:55.128247 read SPI 0x539f4 0xe237: 6247 us, 9270 KB/s, 74.160 Mbps
9651 17:16:55.140749 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9652 17:16:55.147317 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9653 17:16:55.158629 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9654 17:16:55.167769 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9655 17:16:55.171148 CPU_CLUSTER: 0 init finished in 81 msecs
9656 17:16:55.174463 Devices initialized
9657 17:16:55.177983 Show all devs... After init.
9658 17:16:55.178425 Root Device: enabled 1
9659 17:16:55.181046 CPU_CLUSTER: 0: enabled 1
9660 17:16:55.184448 CPU: 00: enabled 1
9661 17:16:55.187922 BS: BS_DEV_INIT run times (exec / console): 207 / 428 ms
9662 17:16:55.191165 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9663 17:16:55.193999 ELOG: NV offset 0x57f000 size 0x1000
9664 17:16:55.201523 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9665 17:16:55.207618 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9666 17:16:55.210895 ELOG: Event(17) added with size 13 at 2022-11-22 17:16:55 UTC
9667 17:16:55.214195 out: cmd=0x121: 03 db 21 01 00 00 00 00
9668 17:16:55.217563
9669 17:16:55.221151 in-header: 03 cf 00 00 2c 00 00 00
9670 17:16:55.230464 in-data: 90 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9671 17:16:55.237040 ELOG: Event(A1) added with size 10 at 2022-11-22 17:16:55 UTC
9672 17:16:55.243620 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9673 17:16:55.250445 ELOG: Event(A0) added with size 9 at 2022-11-22 17:16:55 UTC
9674 17:16:55.253629 elog_add_boot_reason: Logged dev mode boot
9675 17:16:55.260280 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9676 17:16:55.260722 Finalize devices...
9677 17:16:55.263584 Devices finalized
9678 17:16:55.266536 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9679 17:16:55.269910 Writing coreboot table at 0xffe64000
9680 17:16:55.273076 0. 000000000010a000-0000000000113fff: RAMSTAGE
9681 17:16:55.279799 1. 0000000040000000-00000000400fffff: RAM
9682 17:16:55.283283 2. 0000000040100000-000000004032afff: RAMSTAGE
9683 17:16:55.286670 3. 000000004032b000-00000000545fffff: RAM
9684 17:16:55.289670 4. 0000000054600000-000000005465ffff: BL31
9685 17:16:55.293248 5. 0000000054660000-00000000ffe63fff: RAM
9686 17:16:55.299584 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9687 17:16:55.302890 7. 0000000100000000-000000023fffffff: RAM
9688 17:16:55.306633 Passing 5 GPIOs to payload:
9689 17:16:55.309781 NAME | PORT | POLARITY | VALUE
9690 17:16:55.315999 EC in RW | 0x000000aa | low | undefined
9691 17:16:55.319732 EC interrupt | 0x00000005 | low | undefined
9692 17:16:55.326036 TPM interrupt | 0x000000ab | high | undefined
9693 17:16:55.329301 SD card detect | 0x00000011 | high | undefined
9694 17:16:55.332672 speaker enable | 0x00000093 | high | undefined
9695 17:16:55.336557 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9696 17:16:55.339876 in-header: 03 f9 00 00 02 00 00 00
9697 17:16:55.343433 in-data: 02 00
9698 17:16:55.346272 ADC[4]: Raw value=903031 ID=7
9699 17:16:55.346836 ADC[3]: Raw value=212912 ID=1
9700 17:16:55.349558
9701 17:16:55.349994 RAM Code: 0x71
9702 17:16:55.352860 ADC[6]: Raw value=75036 ID=0
9703 17:16:55.355841 ADC[5]: Raw value=212543 ID=1
9704 17:16:55.356280 SKU Code: 0x1
9705 17:16:55.362699 Wrote coreboot table at: 0xffe64000, 0x384 bytes, checksum 71af
9706 17:16:55.363227 coreboot table: 924 bytes.
9707 17:16:55.366063 IMD ROOT 0. 0xfffff000 0x00001000
9708 17:16:55.369414 IMD SMALL 1. 0xffffe000 0x00001000
9709 17:16:55.372883 RO MCACHE 2. 0xffffc000 0x00001104
9710 17:16:55.376504 CONSOLE 3. 0xfff7c000 0x00080000
9711 17:16:55.379061 FMAP 4. 0xfff7b000 0x00000452
9712 17:16:55.382595 TIME STAMP 5. 0xfff7a000 0x00000910
9713 17:16:55.385687 VBOOT WORK 6. 0xfff66000 0x00014000
9714 17:16:55.388696 RAMOOPS 7. 0xffe66000 0x00100000
9715 17:16:55.392268 COREBOOT 8. 0xffe64000 0x00002000
9716 17:16:55.395486 IMD small region:
9717 17:16:55.398951 IMD ROOT 0. 0xffffec00 0x00000400
9718 17:16:55.402428 MMC STATUS 1. 0xffffebe0 0x00000004
9719 17:16:55.405302 BS: BS_WRITE_TABLES run times (exec / console): 0 / 134 ms
9720 17:16:55.408907 Probing TPM: done!
9721 17:16:55.412591 Connected to device vid:did:rid of 1ae0:0028:00
9722 17:16:55.423223 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9723 17:16:55.426765 Initialized TPM device CR50 revision 0
9724 17:16:55.430373 Checking cr50 for pending updates
9725 17:16:55.434470 Reading cr50 TPM mode
9726 17:16:55.443115 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9727 17:16:55.449196 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9728 17:16:55.489603 read SPI 0x3990ec 0x4f1b0: 34847 us, 9298 KB/s, 74.384 Mbps
9729 17:16:55.493300 Checking segment from ROM address 0x40100000
9730 17:16:55.496048 Checking segment from ROM address 0x4010001c
9731 17:16:55.503007 Loading segment from ROM address 0x40100000
9732 17:16:55.503529 code (compression=0)
9733 17:16:55.513272 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9734 17:16:55.519020 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9735 17:16:55.519488 it's not compressed!
9736 17:16:55.525588 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9737 17:16:55.532491 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9738 17:16:55.551330 Loading segment from ROM address 0x4010001c
9739 17:16:55.551876 Entry Point 0x80000000
9740 17:16:55.554139 Loaded segments
9741 17:16:55.557513 BS: BS_PAYLOAD_LOAD run times (exec / console): 50 / 61 ms
9742 17:16:55.564319 Jumping to boot code at 0x80000000(0xffe64000)
9743 17:16:55.570891 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9744 17:16:55.577761 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9745 17:16:55.585257 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9746 17:16:55.588767 Checking segment from ROM address 0x40100000
9747 17:16:55.592268 Checking segment from ROM address 0x4010001c
9748 17:16:55.598816 Loading segment from ROM address 0x40100000
9749 17:16:55.599375 code (compression=1)
9750 17:16:55.605306 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9751 17:16:55.614998 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9752 17:16:55.615707 using LZMA
9753 17:16:55.623866 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9754 17:16:55.630603 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9755 17:16:55.633670 Loading segment from ROM address 0x4010001c
9756 17:16:55.634134 Entry Point 0x54601000
9757 17:16:55.637306 Loaded segments
9758 17:16:55.640446 NOTICE: MT8192 bl31_setup
9759 17:16:55.647612 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9760 17:16:55.650570 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9761 17:16:55.654322 WARNING: region 0:
9762 17:16:55.657778 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9763 17:16:55.658338 WARNING: region 1:
9764 17:16:55.663845 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9765 17:16:55.667859 WARNING: region 2:
9766 17:16:55.670859 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9767 17:16:55.674221 WARNING: region 3:
9768 17:16:55.677706 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9769 17:16:55.680565 WARNING: region 4:
9770 17:16:55.687149 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9771 17:16:55.687614 WARNING: region 5:
9772 17:16:55.690784 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9773 17:16:55.693857 WARNING: region 6:
9774 17:16:55.697202 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9775 17:16:55.700362 WARNING: region 7:
9776 17:16:55.703907 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9777 17:16:55.710580 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9778 17:16:55.714213 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9779 17:16:55.716889 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9780 17:16:55.724033 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9781 17:16:55.727106 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9782 17:16:55.730234 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9783 17:16:55.737184 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9784 17:16:55.740644 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9785 17:16:55.747434 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9786 17:16:55.750260 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9787 17:16:55.753731 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9788 17:16:55.760371 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9789 17:16:55.763286 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9790 17:16:55.767214 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9791 17:16:55.769909
9792 17:16:55.773753 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9793 17:16:55.776598 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9794 17:16:55.783531 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9795 17:16:55.786834 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9796 17:16:55.789814 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9797 17:16:55.796495 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9798 17:16:55.799977 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9799 17:16:55.806584 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9800 17:16:55.809990 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9801 17:16:55.813430 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9802 17:16:55.819790 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9803 17:16:55.823691 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9804 17:16:55.829975 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9805 17:16:55.833210 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9806 17:16:55.837061 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9807 17:16:55.843328 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9808 17:16:55.846488 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9809 17:16:55.853488 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9810 17:16:55.856679 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9811 17:16:55.860323 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9812 17:16:55.863162 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9813 17:16:55.866602 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9814 17:16:55.869996
9815 17:16:55.872972 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9816 17:16:55.876458 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9817 17:16:55.879964 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9818 17:16:55.883006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9819 17:16:55.886365
9820 17:16:55.889803 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9821 17:16:55.893390 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9822 17:16:55.896408 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9823 17:16:55.903245 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9824 17:16:55.906613 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9825 17:16:55.909611 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9826 17:16:55.913064 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9827 17:16:55.919448 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9828 17:16:55.922689 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9829 17:16:55.926112 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9830 17:16:55.932979 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9831 17:16:55.936064 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9832 17:16:55.942785 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9833 17:16:55.946585 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9834 17:16:55.953110 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9835 17:16:55.956189 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9836 17:16:55.959697 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9837 17:16:55.966220 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9838 17:16:55.969522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9839 17:16:55.976120 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9840 17:16:55.979835 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9841 17:16:55.985929 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9842 17:16:55.989615 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9843 17:16:55.996012 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9844 17:16:55.999554 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9845 17:16:56.002923 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9846 17:16:56.009794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9847 17:16:56.012640 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9848 17:16:56.019109 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9849 17:16:56.022593 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9850 17:16:56.029266 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9851 17:16:56.032629 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9852 17:16:56.035779 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9853 17:16:56.042715 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9854 17:16:56.045892 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9855 17:16:56.052794 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9856 17:16:56.056046 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9857 17:16:56.062855 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9858 17:16:56.065491 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9859 17:16:56.072616 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9860 17:16:56.076030 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9861 17:16:56.078823 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9862 17:16:56.085424 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9863 17:16:56.089056 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9864 17:16:56.095657 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9865 17:16:56.099472 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9866 17:16:56.105835 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9867 17:16:56.108900 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9868 17:16:56.112127 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9869 17:16:56.118582 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9870 17:16:56.121971 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9871 17:16:56.128906 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9872 17:16:56.132046 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9873 17:16:56.139468 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9874 17:16:56.142031 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9875 17:16:56.148784 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9876 17:16:56.151770 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9877 17:16:56.155333 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9878 17:16:56.158582 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9879 17:16:56.165470 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9880 17:16:56.168715 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9881 17:16:56.171739 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9882 17:16:56.178516 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9883 17:16:56.181957 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9884 17:16:56.188991 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9885 17:16:56.191861 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9886 17:16:56.194781 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9887 17:16:56.201821 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9888 17:16:56.205160 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9889 17:16:56.211476 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9890 17:16:56.215083 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9891 17:16:56.218055 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9892 17:16:56.224669 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9893 17:16:56.228438 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9894 17:16:56.234893 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9895 17:16:56.237915 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9896 17:16:56.241753 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9897 17:16:56.244626 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9898 17:16:56.248312
9899 17:16:56.251118 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9900 17:16:56.254770 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9901 17:16:56.257832 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9902 17:16:56.264424 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9903 17:16:56.268191 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9904 17:16:56.271380 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9905 17:16:56.274958 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9906 17:16:56.281228 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9907 17:16:56.284769 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9908 17:16:56.290987 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9909 17:16:56.294223 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9910 17:16:56.297950 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9911 17:16:56.301365
9912 17:16:56.304317 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9913 17:16:56.307921 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9914 17:16:56.314400 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9915 17:16:56.317960 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9916 17:16:56.320915 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9917 17:16:56.327884 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9918 17:16:56.330981 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9919 17:16:56.337914 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9920 17:16:56.340965 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9921 17:16:56.344511 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9922 17:16:56.350626 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9923 17:16:56.354273 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9924 17:16:56.361006 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9925 17:16:56.364111 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9926 17:16:56.367269 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9927 17:16:56.373934 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9928 17:16:56.377810 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9929 17:16:56.380719 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9930 17:16:56.387217 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9931 17:16:56.390932 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9932 17:16:56.397552 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9933 17:16:56.400616 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9934 17:16:56.404091 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9935 17:16:56.410650 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9936 17:16:56.414036 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9937 17:16:56.420253 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9938 17:16:56.423911 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9939 17:16:56.427201 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9940 17:16:56.433870 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9941 17:16:56.437253 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9942 17:16:56.443984 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9943 17:16:56.447151 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9944 17:16:56.450611 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9945 17:16:56.456636 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9946 17:16:56.460235 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9947 17:16:56.466857 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9948 17:16:56.469962 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9949 17:16:56.473125 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9950 17:16:56.480164 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9951 17:16:56.483114 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9952 17:16:56.490210 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9953 17:16:56.493074 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9954 17:16:56.496144 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9955 17:16:56.502819 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9956 17:16:56.506224 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9957 17:16:56.512719 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9958 17:16:56.516262 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9959 17:16:56.519462 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9960 17:16:56.525871 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9961 17:16:56.529255 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9962 17:16:56.535760 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9963 17:16:56.539565 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9964 17:16:56.542551 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9965 17:16:56.549068 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9966 17:16:56.552686 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9967 17:16:56.559083 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9968 17:16:56.562499 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9969 17:16:56.565648 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9970 17:16:56.572264 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9971 17:16:56.575694 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9972 17:16:56.582251 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9973 17:16:56.585702 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9974 17:16:56.592315 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9975 17:16:56.595062 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9976 17:16:56.598727 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9977 17:16:56.605486 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9978 17:16:56.608455 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9979 17:16:56.615005 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9980 17:16:56.618271 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9981 17:16:56.624821 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9982 17:16:56.628142 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9983 17:16:56.631281 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9984 17:16:56.638393 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9985 17:16:56.641457 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9986 17:16:56.648087 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9987 17:16:56.651473 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9988 17:16:56.657722 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9989 17:16:56.661337 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9990 17:16:56.664512 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9991 17:16:56.671304 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9992 17:16:56.674493 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9993 17:16:56.680999 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9994 17:16:56.684148 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9995 17:16:56.691156 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9996 17:16:56.694505 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9997 17:16:56.697657 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9998 17:16:56.704244 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9999 17:16:56.707429 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
10000 17:16:56.714596 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
10001 17:16:56.717477 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
10002 17:16:56.720821 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
10003 17:16:56.727471 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
10004 17:16:56.730434 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
10005 17:16:56.737264 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
10006 17:16:56.740676 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
10007 17:16:56.747450 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
10008 17:16:56.750707 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
10009 17:16:56.754250 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
10010 17:16:56.760689 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
10011 17:16:56.763839 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
10012 17:16:56.767346 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
10013 17:16:56.770738 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
10014 17:16:56.777243 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
10015 17:16:56.780338 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
10016 17:16:56.783660 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
10017 17:16:56.790210 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
10018 17:16:56.793771 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
10019 17:16:56.800317 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
10020 17:16:56.803807 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
10021 17:16:56.806666 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
10022 17:16:56.813681 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
10023 17:16:56.816462 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
10024 17:16:56.819699 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
10025 17:16:56.826447 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
10026 17:16:56.829684 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
10027 17:16:56.833154 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
10028 17:16:56.839650 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
10029 17:16:56.842832 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
10030 17:16:56.849394 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
10031 17:16:56.853014 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
10032 17:16:56.855992 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
10033 17:16:56.863056 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
10034 17:16:56.866060 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
10035 17:16:56.869436 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
10036 17:16:56.876028 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
10037 17:16:56.879185 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
10038 17:16:56.885655 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
10039 17:16:56.889130 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
10040 17:16:56.892709 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
10041 17:16:56.898872 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
10042 17:16:56.902000 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
10043 17:16:56.905462 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
10044 17:16:56.908982
10045 17:16:56.912002 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
10046 17:16:56.915843 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
10047 17:16:56.921940 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
10048 17:16:56.925362 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
10049 17:16:56.928785 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
10050 17:16:56.935217 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
10051 17:16:56.938844 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
10052 17:16:56.941739 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
10053 17:16:56.945258 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
10054 17:16:56.951853 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
10055 17:16:56.955010 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
10056 17:16:56.959053 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
10057 17:16:56.961808 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
10058 17:16:56.968512 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
10059 17:16:56.971699 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
10060 17:16:56.975074 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
10061 17:16:56.977912 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
10062 17:16:56.984703 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
10063 17:16:56.988122 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
10064 17:16:56.991447 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
10065 17:16:56.998031 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
10066 17:16:57.001957 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
10067 17:16:57.007809 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
10068 17:16:57.011322 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
10069 17:16:57.014581 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
10070 17:16:57.017463
10071 17:16:57.021008 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
10072 17:16:57.024525 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
10073 17:16:57.031273 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
10074 17:16:57.034589 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
10075 17:16:57.037727 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
10076 17:16:57.040937
10077 17:16:57.044386 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
10078 17:16:57.047499 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
10079 17:16:57.054219 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
10080 17:16:57.057732 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
10081 17:16:57.063876 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
10082 17:16:57.067573 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
10083 17:16:57.070938 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
10084 17:16:57.077436 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
10085 17:16:57.080887 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
10086 17:16:57.087672 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
10087 17:16:57.090562 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
10088 17:16:57.097409 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
10089 17:16:57.100358 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
10090 17:16:57.104039 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
10091 17:16:57.110826 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
10092 17:16:57.114024 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
10093 17:16:57.120712 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
10094 17:16:57.124012 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
10095 17:16:57.127115 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
10096 17:16:57.133444 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
10097 17:16:57.136883 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
10098 17:16:57.143518 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
10099 17:16:57.146798 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
10100 17:16:57.150535 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
10101 17:16:57.156558 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
10102 17:16:57.159844 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
10103 17:16:57.166638 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
10104 17:16:57.170407 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
10105 17:16:57.176932 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
10106 17:16:57.180186 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
10107 17:16:57.183054 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
10108 17:16:57.189813 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
10109 17:16:57.192918 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
10110 17:16:57.199670 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
10111 17:16:57.202593 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
10112 17:16:57.209615 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
10113 17:16:57.212795 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
10114 17:16:57.216527 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
10115 17:16:57.222787 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
10116 17:16:57.226283 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
10117 17:16:57.232595 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
10118 17:16:57.235828 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
10119 17:16:57.239035 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
10120 17:16:57.245707 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
10121 17:16:57.249106 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
10122 17:16:57.255598 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
10123 17:16:57.259088 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
10124 17:16:57.262039 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
10125 17:16:57.268669 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
10126 17:16:57.272161 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
10127 17:16:57.279025 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
10128 17:16:57.282024 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
10129 17:16:57.288768 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
10130 17:16:57.291867 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
10131 17:16:57.295552 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
10132 17:16:57.301758 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
10133 17:16:57.305205 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
10134 17:16:57.311780 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
10135 17:16:57.315410 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
10136 17:16:57.318552 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
10137 17:16:57.321801
10138 17:16:57.324844 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
10139 17:16:57.327979 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
10140 17:16:57.334774 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
10141 17:16:57.337996 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
10142 17:16:57.345085 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
10143 17:16:57.348025 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
10144 17:16:57.354417 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
10145 17:16:57.357971 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
10146 17:16:57.361381 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
10147 17:16:57.367791 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
10148 17:16:57.370894 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
10149 17:16:57.377387 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
10150 17:16:57.381262 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
10151 17:16:57.387371 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
10152 17:16:57.391088 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
10153 17:16:57.397470 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
10154 17:16:57.401078 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
10155 17:16:57.403741 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
10156 17:16:57.410568 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
10157 17:16:57.413467 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
10158 17:16:57.420038 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
10159 17:16:57.423673 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
10160 17:16:57.429849 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
10161 17:16:57.433753 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
10162 17:16:57.436678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
10163 17:16:57.440009
10164 17:16:57.443635 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
10165 17:16:57.446535 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
10166 17:16:57.453344 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
10167 17:16:57.456465 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
10168 17:16:57.463414 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
10169 17:16:57.466831 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
10170 17:16:57.472903 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
10171 17:16:57.476794 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
10172 17:16:57.479705 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
10173 17:16:57.486369 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
10174 17:16:57.489815 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
10175 17:16:57.496239 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
10176 17:16:57.499539 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
10177 17:16:57.506402 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
10178 17:16:57.509414 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
10179 17:16:57.516238 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
10180 17:16:57.519760 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
10181 17:16:57.522976 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
10182 17:16:57.529134 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
10183 17:16:57.532732 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
10184 17:16:57.539178 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
10185 17:16:57.542693 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
10186 17:16:57.549213 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
10187 17:16:57.552605 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10188 17:16:57.556087 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10189 17:16:57.562522 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10190 17:16:57.565542 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10191 17:16:57.572250 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10192 17:16:57.575949 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10193 17:16:57.582094 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10194 17:16:57.585668 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10195 17:16:57.592532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10196 17:16:57.595372 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10197 17:16:57.602168 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10198 17:16:57.605085 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10199 17:16:57.611872 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10200 17:16:57.615118 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10201 17:16:57.618525 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10202 17:16:57.622241
10203 17:16:57.625145 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10204 17:16:57.628545 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10205 17:16:57.635073 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10206 17:16:57.638602 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10207 17:16:57.645025 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10208 17:16:57.648640 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10209 17:16:57.654997 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10210 17:16:57.658559 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10211 17:16:57.665028 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10212 17:16:57.668099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10213 17:16:57.674708 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10214 17:16:57.677842 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10215 17:16:57.681350
10216 17:16:57.684598 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10217 17:16:57.691316 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10218 17:16:57.694241 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10219 17:16:57.701112 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10220 17:16:57.704252 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10221 17:16:57.711099 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10222 17:16:57.714196 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10223 17:16:57.717497 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10224 17:16:57.721191 INFO: [APUAPC] vio 0
10225 17:16:57.724148 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10226 17:16:57.727497
10227 17:16:57.730809 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10228 17:16:57.733931 INFO: [APUAPC] D0_APC_0: 0x400510
10229 17:16:57.737610 INFO: [APUAPC] D0_APC_1: 0x0
10230 17:16:57.740459 INFO: [APUAPC] D0_APC_2: 0x1540
10231 17:16:57.743991 INFO: [APUAPC] D0_APC_3: 0x0
10232 17:16:57.747397 INFO: [APUAPC] D1_APC_0: 0xffffffff
10233 17:16:57.750466 INFO: [APUAPC] D1_APC_1: 0xffffffff
10234 17:16:57.753674 INFO: [APUAPC] D1_APC_2: 0x3fffff
10235 17:16:57.753755 INFO: [APUAPC] D1_APC_3: 0x0
10236 17:16:57.757060
10237 17:16:57.760793 INFO: [APUAPC] D2_APC_0: 0xffffffff
10238 17:16:57.763838 INFO: [APUAPC] D2_APC_1: 0xffffffff
10239 17:16:57.766941 INFO: [APUAPC] D2_APC_2: 0x3fffff
10240 17:16:57.767021 INFO: [APUAPC] D2_APC_3: 0x0
10241 17:16:57.770425 INFO: [APUAPC] D3_APC_0: 0xffffffff
10242 17:16:57.773912 INFO: [APUAPC] D3_APC_1: 0xffffffff
10243 17:16:57.777172
10244 17:16:57.777252 INFO: [APUAPC] D3_APC_2: 0x3fffff
10245 17:16:57.780123
10246 17:16:57.780202 INFO: [APUAPC] D3_APC_3: 0x0
10247 17:16:57.783708 INFO: [APUAPC] D4_APC_0: 0xffffffff
10248 17:16:57.786609 INFO: [APUAPC] D4_APC_1: 0xffffffff
10249 17:16:57.790214 INFO: [APUAPC] D4_APC_2: 0x3fffff
10250 17:16:57.793649 INFO: [APUAPC] D4_APC_3: 0x0
10251 17:16:57.796836 INFO: [APUAPC] D5_APC_0: 0xffffffff
10252 17:16:57.799936 INFO: [APUAPC] D5_APC_1: 0xffffffff
10253 17:16:57.803416 INFO: [APUAPC] D5_APC_2: 0x3fffff
10254 17:16:57.806552 INFO: [APUAPC] D5_APC_3: 0x0
10255 17:16:57.809902 INFO: [APUAPC] D6_APC_0: 0xffffffff
10256 17:16:57.813292 INFO: [APUAPC] D6_APC_1: 0xffffffff
10257 17:16:57.816866 INFO: [APUAPC] D6_APC_2: 0x3fffff
10258 17:16:57.819963 INFO: [APUAPC] D6_APC_3: 0x0
10259 17:16:57.823033 INFO: [APUAPC] D7_APC_0: 0xffffffff
10260 17:16:57.826583 INFO: [APUAPC] D7_APC_1: 0xffffffff
10261 17:16:57.829828 INFO: [APUAPC] D7_APC_2: 0x3fffff
10262 17:16:57.833624 INFO: [APUAPC] D7_APC_3: 0x0
10263 17:16:57.836519 INFO: [APUAPC] D8_APC_0: 0xffffffff
10264 17:16:57.839917 INFO: [APUAPC] D8_APC_1: 0xffffffff
10265 17:16:57.843445 INFO: [APUAPC] D8_APC_2: 0x3fffff
10266 17:16:57.846817 INFO: [APUAPC] D8_APC_3: 0x0
10267 17:16:57.849941 INFO: [APUAPC] D9_APC_0: 0xffffffff
10268 17:16:57.853001 INFO: [APUAPC] D9_APC_1: 0xffffffff
10269 17:16:57.856403 INFO: [APUAPC] D9_APC_2: 0x3fffff
10270 17:16:57.859615 INFO: [APUAPC] D9_APC_3: 0x0
10271 17:16:57.863031 INFO: [APUAPC] D10_APC_0: 0xffffffff
10272 17:16:57.866149 INFO: [APUAPC] D10_APC_1: 0xffffffff
10273 17:16:57.869417 INFO: [APUAPC] D10_APC_2: 0x3fffff
10274 17:16:57.872803 INFO: [APUAPC] D10_APC_3: 0x0
10275 17:16:57.876516 INFO: [APUAPC] D11_APC_0: 0xffffffff
10276 17:16:57.879437 INFO: [APUAPC] D11_APC_1: 0xffffffff
10277 17:16:57.883027 INFO: [APUAPC] D11_APC_2: 0x3fffff
10278 17:16:57.886276 INFO: [APUAPC] D11_APC_3: 0x0
10279 17:16:57.889674 INFO: [APUAPC] D12_APC_0: 0xffffffff
10280 17:16:57.892647 INFO: [APUAPC] D12_APC_1: 0xffffffff
10281 17:16:57.895846 INFO: [APUAPC] D12_APC_2: 0x3fffff
10282 17:16:57.899259 INFO: [APUAPC] D12_APC_3: 0x0
10283 17:16:57.902500 INFO: [APUAPC] D13_APC_0: 0xffffffff
10284 17:16:57.905587 INFO: [APUAPC] D13_APC_1: 0xffffffff
10285 17:16:57.909130 INFO: [APUAPC] D13_APC_2: 0x3fffff
10286 17:16:57.912661 INFO: [APUAPC] D13_APC_3: 0x0
10287 17:16:57.915608 INFO: [APUAPC] D14_APC_0: 0xffffffff
10288 17:16:57.919077 INFO: [APUAPC] D14_APC_1: 0xffffffff
10289 17:16:57.922077 INFO: [APUAPC] D14_APC_2: 0x3fffff
10290 17:16:57.925689 INFO: [APUAPC] D14_APC_3: 0x0
10291 17:16:57.929027 INFO: [APUAPC] D15_APC_0: 0xffffffff
10292 17:16:57.932301 INFO: [APUAPC] D15_APC_1: 0xffffffff
10293 17:16:57.935343 INFO: [APUAPC] D15_APC_2: 0x3fffff
10294 17:16:57.938864 INFO: [APUAPC] D15_APC_3: 0x0
10295 17:16:57.942380 INFO: [APUAPC] APC_CON: 0x4
10296 17:16:57.945535 INFO: [NOCDAPC] D0_APC_0: 0x0
10297 17:16:57.948887 INFO: [NOCDAPC] D0_APC_1: 0x0
10298 17:16:57.951950 INFO: [NOCDAPC] D1_APC_0: 0x0
10299 17:16:57.955587 INFO: [NOCDAPC] D1_APC_1: 0xfff
10300 17:16:57.959023 INFO: [NOCDAPC] D2_APC_0: 0x0
10301 17:16:57.959109 INFO: [NOCDAPC] D2_APC_1: 0xfff
10302 17:16:57.962243
10303 17:16:57.962329 INFO: [NOCDAPC] D3_APC_0: 0x0
10304 17:16:57.965157 INFO: [NOCDAPC] D3_APC_1: 0xfff
10305 17:16:57.968777 INFO: [NOCDAPC] D4_APC_0: 0x0
10306 17:16:57.971736 INFO: [NOCDAPC] D4_APC_1: 0xfff
10307 17:16:57.975125 INFO: [NOCDAPC] D5_APC_0: 0x0
10308 17:16:57.978580 INFO: [NOCDAPC] D5_APC_1: 0xfff
10309 17:16:57.981662 INFO: [NOCDAPC] D6_APC_0: 0x0
10310 17:16:57.985295 INFO: [NOCDAPC] D6_APC_1: 0xfff
10311 17:16:57.988351 INFO: [NOCDAPC] D7_APC_0: 0x0
10312 17:16:57.991602 INFO: [NOCDAPC] D7_APC_1: 0xfff
10313 17:16:57.991688 INFO: [NOCDAPC] D8_APC_0: 0x0
10314 17:16:57.995065
10315 17:16:57.995150 INFO: [NOCDAPC] D8_APC_1: 0xfff
10316 17:16:57.998194 INFO: [NOCDAPC] D9_APC_0: 0x0
10317 17:16:58.001811 INFO: [NOCDAPC] D9_APC_1: 0xfff
10318 17:16:58.005011 INFO: [NOCDAPC] D10_APC_0: 0x0
10319 17:16:58.008540 INFO: [NOCDAPC] D10_APC_1: 0xfff
10320 17:16:58.011555 INFO: [NOCDAPC] D11_APC_0: 0x0
10321 17:16:58.014954 INFO: [NOCDAPC] D11_APC_1: 0xfff
10322 17:16:58.018346 INFO: [NOCDAPC] D12_APC_0: 0x0
10323 17:16:58.021265 INFO: [NOCDAPC] D12_APC_1: 0xfff
10324 17:16:58.025080 INFO: [NOCDAPC] D13_APC_0: 0x0
10325 17:16:58.028076 INFO: [NOCDAPC] D13_APC_1: 0xfff
10326 17:16:58.031577 INFO: [NOCDAPC] D14_APC_0: 0x0
10327 17:16:58.034619 INFO: [NOCDAPC] D14_APC_1: 0xfff
10328 17:16:58.038051 INFO: [NOCDAPC] D15_APC_0: 0x0
10329 17:16:58.041154 INFO: [NOCDAPC] D15_APC_1: 0xfff
10330 17:16:58.041240 INFO: [NOCDAPC] APC_CON: 0x4
10331 17:16:58.044692 INFO: [APUAPC] set_apusys_apc done
10332 17:16:58.048115 INFO: [DEVAPC] devapc_init done
10333 17:16:58.054442 INFO: GICv3 without legacy support detected.
10334 17:16:58.057944 INFO: ARM GICv3 driver initialized in EL3
10335 17:16:58.061459 INFO: Maximum SPI INTID supported: 639
10336 17:16:58.064423 INFO: BL31: Initializing runtime services
10337 17:16:58.070927 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10338 17:16:58.074429 INFO: SPM: enable CPC mode
10339 17:16:58.077745 INFO: mcdi ready for mcusys-off-idle and system suspend
10340 17:16:58.084463 INFO: BL31: Preparing for EL3 exit to normal world
10341 17:16:58.087538 INFO: Entry point address = 0x80000000
10342 17:16:58.087623 INFO: SPSR = 0x8
10343 17:16:58.094646
10344 17:16:58.094736
10345 17:16:58.094803
10346 17:16:58.098326 Starting depthcharge on Spherion...
10347 17:16:58.098411
10348 17:16:58.098512 Wipe memory regions:
10349 17:16:58.098575
10350 17:16:58.099089 end: 2.2.3 depthcharge-start (duration 00:00:35) [common]
10351 17:16:58.099192 start: 2.2.4 bootloader-commands (timeout 00:04:25) [common]
10352 17:16:58.099276 Setting prompt string to ['asurada:']
10353 17:16:58.099352 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:25)
10354 17:16:58.101567 [0x00000040000000, 0x00000054600000)
10355 17:16:58.101662
10356 17:16:58.223820 [0x00000054660000, 0x00000080000000)
10357 17:16:58.226965
10358 17:16:58.483264 [0x000000821a7280, 0x000000ffe64000)
10359 17:16:58.486732
10360 17:16:59.228022 [0x00000100000000, 0x00000240000000)
10361 17:16:59.231332
10362 17:17:01.120407 Initializing XHCI USB controller at 0x11200000.
10363 17:17:01.120564
10364 17:17:02.101974 R8152: Initializing
10365 17:17:02.102124
10366 17:17:02.105399 Version 9 (ocp_data = 6010)
10367 17:17:02.105476
10368 17:17:02.108404 R8152: Done initializing
10369 17:17:02.108474
10370 17:17:02.108536 Adding net device
10371 17:17:02.108596
10372 17:17:02.509657 [firmware-asurada-13885.B-collabora] Dec 14 2021 15:21:43
10373 17:17:02.509790
10374 17:17:02.509860
10375 17:17:02.509922
10376 17:17:02.510251 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10378 17:17:02.610983 asurada: tftpboot 192.168.201.1 8082983/tftp-deploy-tjk8rzjj/kernel/image.itb 8082983/tftp-deploy-tjk8rzjj/kernel/cmdline
10379 17:17:02.611119 Setting prompt string to 'jumping to kernel'
10380 17:17:02.611192 Setting prompt string to ['jumping to kernel']
10381 17:17:02.611260 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10382 17:17:02.611333 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10383 17:17:02.615060 tftpboot 192.168.201.1 8082983/tftp-deploy-tjk8rzjj/kernel/image.ittp-deploy-tjk8rzjj/kernel/cmdline
10384 17:17:02.615148
10385 17:17:02.615216 Waiting for link
10386 17:17:02.615314
10387 17:17:02.817111 done.
10388 17:17:02.817244
10389 17:17:02.817316 MAC: f4:f5:e8:50:de:0a
10390 17:17:02.817387
10391 17:17:02.820427 Sending DHCP discover... done.
10392 17:17:02.820515
10393 17:17:02.823467 Waiting for reply... done.
10394 17:17:02.823553
10395 17:17:02.827123 Sending DHCP request... done.
10396 17:17:02.827209
10397 17:17:02.827277 Waiting for reply... done.
10398 17:17:02.827341
10399 17:17:02.830043 My ip is 192.168.201.14
10400 17:17:02.830128
10401 17:17:02.833091 The DHCP server ip is 192.168.201.1
10402 17:17:02.833177
10403 17:17:02.836529 TFTP server IP predefined by user: 192.168.201.1
10404 17:17:02.836615
10405 17:17:02.843172 Bootfile predefined by user: 8082983/tftp-deploy-tjk8rzjj/kernel/image.itb
10406 17:17:02.843259
10407 17:17:02.846604 Sending tftp read request... done.
10408 17:17:02.846697
10409 17:17:02.850017 Waiting for the transfer...
10410 17:17:02.850104
10411 17:17:03.075532 00000000 ################################################################
10412 17:17:03.075729
10413 17:17:03.298724 00080000 ################################################################
10414 17:17:03.298859
10415 17:17:03.517740 00100000 ################################################################
10416 17:17:03.517904
10417 17:17:03.732832 00180000 ################################################################
10418 17:17:03.732979
10419 17:17:03.950709 00200000 ################################################################
10420 17:17:03.950864
10421 17:17:04.167254 00280000 ################################################################
10422 17:17:04.167403
10423 17:17:04.383989 00300000 ################################################################
10424 17:17:04.384130
10425 17:17:04.600546 00380000 ################################################################
10426 17:17:04.600678
10427 17:17:04.816544 00400000 ################################################################
10428 17:17:04.816685
10429 17:17:05.032996 00480000 ################################################################
10430 17:17:05.033167
10431 17:17:05.248636 00500000 ################################################################
10432 17:17:05.248782
10433 17:17:05.463709 00580000 ################################################################
10434 17:17:05.463851
10435 17:17:05.683397 00600000 ################################################################
10436 17:17:05.683543
10437 17:17:05.899375 00680000 ################################################################
10438 17:17:05.899509
10439 17:17:06.116441 00700000 ################################################################
10440 17:17:06.116582
10441 17:17:06.334632 00780000 ################################################################
10442 17:17:06.334768
10443 17:17:06.556007 00800000 ################################################################
10444 17:17:06.556154
10445 17:17:06.793492 00880000 ################################################################
10446 17:17:06.793626
10447 17:17:07.034062 00900000 ################################################################
10448 17:17:07.034202
10449 17:17:07.273254 00980000 ################################################################
10450 17:17:07.273439
10451 17:17:07.505012 00a00000 ################################################################
10452 17:17:07.505160
10453 17:17:07.739767 00a80000 ################################################################
10454 17:17:07.739902
10455 17:17:07.993742 00b00000 ################################################################
10456 17:17:07.993879
10457 17:17:08.228544 00b80000 ################################################################
10458 17:17:08.228683
10459 17:17:08.487853 00c00000 ################################################################
10460 17:17:08.488004
10461 17:17:08.723585 00c80000 ################################################################
10462 17:17:08.723714
10463 17:17:08.979958 00d00000 ################################################################
10464 17:17:08.980088
10465 17:17:09.219395 00d80000 ################################################################
10466 17:17:09.219529
10467 17:17:09.458035 00e00000 ################################################################
10468 17:17:09.458167
10469 17:17:09.695060 00e80000 ################################################################
10470 17:17:09.695192
10471 17:17:09.926718 00f00000 ################################################################
10472 17:17:09.926847
10473 17:17:10.155599 00f80000 ################################################################
10474 17:17:10.155736
10475 17:17:10.376336 01000000 ################################################################
10476 17:17:10.376474
10477 17:17:10.599278 01080000 ################################################################
10478 17:17:10.599414
10479 17:17:10.824994 01100000 ################################################################
10480 17:17:10.825152
10481 17:17:11.056116 01180000 ################################################################
10482 17:17:11.056251
10483 17:17:11.274150 01200000 ################################################################
10484 17:17:11.274299
10485 17:17:11.493792 01280000 ################################################################
10486 17:17:11.493939
10487 17:17:11.719129 01300000 ################################################################
10488 17:17:11.719279
10489 17:17:11.961456 01380000 ################################################################
10490 17:17:11.961610
10491 17:17:12.212887 01400000 ################################################################
10492 17:17:12.213029
10493 17:17:12.479029 01480000 ################################################################
10494 17:17:12.479174
10495 17:17:12.724975 01500000 ################################################################
10496 17:17:12.725114
10497 17:17:12.980789 01580000 ################################################################
10498 17:17:12.980922
10499 17:17:13.229450 01600000 ################################################################
10500 17:17:13.229588
10501 17:17:13.456334 01680000 ################################################################
10502 17:17:13.456486
10503 17:17:13.693630 01700000 ################################################################
10504 17:17:13.693778
10505 17:17:13.924060 01780000 ################################################################
10506 17:17:13.924204
10507 17:17:14.156580 01800000 ################################################################
10508 17:17:14.156716
10509 17:17:14.393806 01880000 ################################################################
10510 17:17:14.393945
10511 17:17:14.630095 01900000 ################################################################
10512 17:17:14.630244
10513 17:17:14.848965 01980000 ################################################################
10514 17:17:14.849138
10515 17:17:15.067295 01a00000 ######################################################### done.
10516 17:17:15.067432
10517 17:17:15.070644 The bootfile was 27725463 bytes long.
10518 17:17:15.070732
10519 17:17:15.074093 Sending tftp read request... done.
10520 17:17:15.074180
10521 17:17:15.077283 Waiting for the transfer...
10522 17:17:15.077407
10523 17:17:15.077476 00000000 # done.
10524 17:17:15.077542
10525 17:17:15.086956 Command line loaded dynamically from TFTP file: 8082983/tftp-deploy-tjk8rzjj/kernel/cmdline
10526 17:17:15.087044
10527 17:17:15.107311 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10528 17:17:15.107457
10529 17:17:15.107526 Loading FIT.
10530 17:17:15.107591
10531 17:17:15.110129 Image ramdisk-1 has 18637409 bytes.
10532 17:17:15.110217
10533 17:17:15.113636 Image fdt-1 has 46773 bytes.
10534 17:17:15.113725
10535 17:17:15.116946 Image kernel-1 has 9039409 bytes.
10536 17:17:15.117117
10537 17:17:15.123283 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10538 17:17:15.123385
10539 17:17:15.144039 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10540 17:17:15.144495
10541 17:17:15.146811 Choosing best match conf-1 for compat google,spherion-rev2.
10542 17:17:15.147280
10543 17:17:15.156729 Connected to device vid:did:rid of 1ae0:0028:00
10544 17:17:15.157069
10545 17:17:15.167121 tpm_get_response: command 0x17b, return code 0x0
10546 17:17:15.167330
10547 17:17:15.170409 ec_init: CrosEC protocol v3 supported (256, 248)
10548 17:17:15.170566
10549 17:17:15.177292 tpm_cleanup: add release locality here.
10550 17:17:15.177438
10551 17:17:15.177546 Shutting down all USB controllers.
10552 17:17:15.180978
10553 17:17:15.181120 Removing current net device
10554 17:17:15.181228
10555 17:17:15.187195 Exiting depthcharge with code 4 at timestamp: 46491935
10556 17:17:15.187329
10557 17:17:15.190575 LZMA decompressing kernel-1 to 0x821a6718
10558 17:17:15.190693
10559 17:17:15.194156 LZMA decompressing kernel-1 to 0x40000000
10560 17:17:15.194240
10561 17:17:16.321860 jumping to kernel
10562 17:17:16.322012
10563 17:17:16.322467 end: 2.2.4 bootloader-commands (duration 00:00:18) [common]
10564 17:17:16.322567 start: 2.2.5 auto-login-action (timeout 00:04:06) [common]
10565 17:17:16.322643 Setting prompt string to ['Linux version [0-9]']
10566 17:17:16.322712 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10567 17:17:16.322781 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10568 17:17:16.406709 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10569 17:17:16.410383 start: 2.2.5.1 login-action (timeout 00:04:06) [common]
10570 17:17:16.410496 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10571 17:17:16.410584 Setting prompt string to ['-+\\[ cut here \\]-+\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '(Unhandled fault.*)\\r\\n', 'Kernel panic - (.*) end Kernel panic', 'Stack:\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '^[^\\n]+WARNING:.*?$', '^[^\\n]+Oops(?: -|:).*?$', '^[^\\n]+BUG:.*?$']
10572 17:17:16.410664 Using line separator: #'\n'#
10573 17:17:16.410728 No login prompt set.
10574 17:17:16.410792 Parsing kernel messages
10575 17:17:16.410850 ['-+\\[ cut here \\]-+\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '(Unhandled fault.*)\\r\\n', 'Kernel panic - (.*) end Kernel panic', 'Stack:\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '^[^\\n]+WARNING:.*?$', '^[^\\n]+Oops(?: -|:).*?$', '^[^\\n]+BUG:.*?$', '/ #', 'Login timed out', 'Login incorrect']
10576 17:17:16.410952 [login-action] Waiting for messages, (timeout 00:04:06)
10577 17:17:16.429719 [ 0.000000] Linux version 6.1.0-rc6 (KernelCI@build-j93566-arm64-gcc-10-defconfig-arm64-chromebook-6tbsx) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Nov 22 16:59:36 UTC 2022
10578 17:17:16.433203 [ 0.000000] random: crng init done
10579 17:17:16.439770 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10580 17:17:16.439855 [ 0.000000] efi: UEFI not found.
10581 17:17:16.443105
10582 17:17:16.449745 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10583 17:17:16.456272 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10584 17:17:16.466309 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10585 17:17:16.469458 [ 0.000000] printk: bootconsole [mtk8250] enabled
10586 17:17:16.477024 [ 0.000000] NUMA: No NUMA configuration found
10587 17:17:16.483277 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10588 17:17:16.489990 [ 0.000000] NUMA: NODE_DATA [mem 0x23efc8a00-0x23efcafff]
10589 17:17:16.490074 [ 0.000000] Zone ranges:
10590 17:17:16.496415 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10591 17:17:16.500110 [ 0.000000] DMA32 empty
10592 17:17:16.506614 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10593 17:17:16.509601 [ 0.000000] Movable zone start for each node
10594 17:17:16.513164 [ 0.000000] Early memory node ranges
10595 17:17:16.519940 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10596 17:17:16.526346 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10597 17:17:16.533022 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10598 17:17:16.539215 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10599 17:17:16.546126 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10600 17:17:16.552714 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10601 17:17:16.609186 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10602 17:17:16.615798 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10603 17:17:16.622263 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10604 17:17:16.625766 [ 0.000000] psci: probing for conduit method from DT.
10605 17:17:16.632193 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10606 17:17:16.635701 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10607 17:17:16.642445 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10608 17:17:16.645426 [ 0.000000] psci: SMC Calling Convention v1.2
10609 17:17:16.652222 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
10610 17:17:16.655294 [ 0.000000] Detected VIPT I-cache on CPU0
10611 17:17:16.661808 [ 0.000000] CPU features: detected: GIC system register CPU interface
10612 17:17:16.668843 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10613 17:17:16.674947 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10614 17:17:16.681620 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10615 17:17:16.691571 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10616 17:17:16.698045 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10617 17:17:16.701717 [ 0.000000] alternatives: applying boot alternatives
10618 17:17:16.708627 [ 0.000000] Fallback order for Node 0: 0
10619 17:17:16.714810 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10620 17:17:16.718364 [ 0.000000] Policy zone: Normal
10621 17:17:16.738007 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/nfs rw nfsroot=192.168.201.1:/var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep,tcp,hard ip=dhcp tftpserverip=192.168.201.1
10622 17:17:16.747952 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10623 17:17:16.759975 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10624 17:17:16.769615 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10625 17:17:16.776211 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10626 17:17:16.779819 <6>[ 0.000000] software IO TLB: area num 8.
10627 17:17:16.835788 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10628 17:17:16.984926 <6>[ 0.000000] Memory: 7962560K/8385536K available (16256K kernel code, 3786K rwdata, 9016K rodata, 7616K init, 610K bss, 390208K reserved, 32768K cma-reserved)
10629 17:17:16.991629 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10630 17:17:16.998116 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10631 17:17:17.001258 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10632 17:17:17.008118 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10633 17:17:17.014766 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10634 17:17:17.017808 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10635 17:17:17.027503 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10636 17:17:17.033942 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10637 17:17:17.040852 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10638 17:17:17.047388 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10639 17:17:17.050333 <6>[ 0.000000] GICv3: 608 SPIs implemented
10640 17:17:17.053786 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10641 17:17:17.060336 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10642 17:17:17.063674 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10643 17:17:17.070005 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10644 17:17:17.083251 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10645 17:17:17.096618 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10646 17:17:17.103302 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10647 17:17:17.110985 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10648 17:17:17.124496 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10649 17:17:17.131311 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10650 17:17:17.138059 <6>[ 0.009191] Console: colour dummy device 80x25
10651 17:17:17.148243 <6>[ 0.013922] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10652 17:17:17.154294 <6>[ 0.024430] pid_max: default: 32768 minimum: 301
10653 17:17:17.157366 <6>[ 0.029333] LSM: Security Framework initializing
10654 17:17:17.164535 <6>[ 0.034271] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10655 17:17:17.174211 <6>[ 0.042084] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10656 17:17:17.184189 <6>[ 0.051508] cblist_init_generic: Setting adjustable number of callback queues.
10657 17:17:17.187201 <6>[ 0.058961] cblist_init_generic: Setting shift to 3 and lim to 1.
10658 17:17:17.194213 <6>[ 0.065298] cblist_init_generic: Setting shift to 3 and lim to 1.
10659 17:17:17.200430 <6>[ 0.071697] rcu: Hierarchical SRCU implementation.
10660 17:17:17.207436 <6>[ 0.076742] rcu: Max phase no-delay instances is 1000.
10661 17:17:17.213800 <6>[ 0.083759] EFI services will not be available.
10662 17:17:17.217057 <6>[ 0.088702] smp: Bringing up secondary CPUs ...
10663 17:17:17.224782 <6>[ 0.093750] Detected VIPT I-cache on CPU1
10664 17:17:17.231172 <6>[ 0.093819] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10665 17:17:17.238037 <6>[ 0.093850] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10666 17:17:17.240920 <6>[ 0.094179] Detected VIPT I-cache on CPU2
10667 17:17:17.247622 <6>[ 0.094227] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10668 17:17:17.250930
10669 17:17:17.257566 <6>[ 0.094242] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10670 17:17:17.261106 <6>[ 0.094496] Detected VIPT I-cache on CPU3
10671 17:17:17.267765 <6>[ 0.094542] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10672 17:17:17.273775 <6>[ 0.094555] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10673 17:17:17.277083 <6>[ 0.094855] CPU features: detected: Spectre-v4
10674 17:17:17.284016 <6>[ 0.094861] CPU features: detected: Spectre-BHB
10675 17:17:17.287226 <6>[ 0.094867] Detected PIPT I-cache on CPU4
10676 17:17:17.293891 <6>[ 0.094925] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10677 17:17:17.300597 <6>[ 0.094941] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10678 17:17:17.306759 <6>[ 0.095232] Detected PIPT I-cache on CPU5
10679 17:17:17.313161 <6>[ 0.095294] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10680 17:17:17.320026 <6>[ 0.095310] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10681 17:17:17.323521 <6>[ 0.095589] Detected PIPT I-cache on CPU6
10682 17:17:17.330201 <6>[ 0.095655] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10683 17:17:17.337436 <6>[ 0.095671] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10684 17:17:17.343830 <6>[ 0.095947] Detected PIPT I-cache on CPU7
10685 17:17:17.349956 <6>[ 0.096013] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10686 17:17:17.356901 <6>[ 0.096029] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10687 17:17:17.359970 <6>[ 0.096076] smp: Brought up 1 node, 8 CPUs
10688 17:17:17.366192 <6>[ 0.237288] SMP: Total of 8 processors activated.
10689 17:17:17.369671 <6>[ 0.242209] CPU features: detected: 32-bit EL0 Support
10690 17:17:17.379493 <6>[ 0.247571] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10691 17:17:17.385989 <6>[ 0.256371] CPU features: detected: Common not Private translations
10692 17:17:17.392596 <6>[ 0.262847] CPU features: detected: CRC32 instructions
10693 17:17:17.399099 <6>[ 0.268198] CPU features: detected: RCpc load-acquire (LDAPR)
10694 17:17:17.402374 <6>[ 0.274158] CPU features: detected: LSE atomic instructions
10695 17:17:17.408924 <6>[ 0.279975] CPU features: detected: Privileged Access Never
10696 17:17:17.415576 <6>[ 0.285790] CPU features: detected: RAS Extension Support
10697 17:17:17.422464 <6>[ 0.291433] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10698 17:17:17.425476 <6>[ 0.298653] CPU: All CPU(s) started at EL2
10699 17:17:17.432097 <6>[ 0.302970] alternatives: applying system-wide alternatives
10700 17:17:17.442117 <6>[ 0.313553] devtmpfs: initialized
10701 17:17:17.454503 <6>[ 0.322422] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10702 17:17:17.457609
10703 17:17:17.464190 <6>[ 0.332385] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10704 17:17:17.467378 <6>[ 0.340161] pinctrl core: initialized pinctrl subsystem
10705 17:17:17.470743
10706 17:17:17.474243 <6>[ 0.346796] DMI not present or invalid.
10707 17:17:17.480384 <6>[ 0.351205] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10708 17:17:17.490143 <6>[ 0.358060] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10709 17:17:17.497116 <6>[ 0.365639] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10710 17:17:17.506986 <6>[ 0.373845] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10711 17:17:17.510084 <6>[ 0.382091] audit: initializing netlink subsys (disabled)
10712 17:17:17.520231 <5>[ 0.387790] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10713 17:17:17.527132 <6>[ 0.388490] thermal_sys: Registered thermal governor 'step_wise'
10714 17:17:17.533830 <6>[ 0.395758] thermal_sys: Registered thermal governor 'power_allocator'
10715 17:17:17.536718 <6>[ 0.402012] cpuidle: using governor menu
10716 17:17:17.543500 <6>[ 0.413025] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10717 17:17:17.549785 <6>[ 0.420126] ASID allocator initialised with 32768 entries
10718 17:17:17.553365 <6>[ 0.426656] Serial: AMBA PL011 UART driver
10719 17:17:17.564410 <4>[ 0.435642] Trying to register duplicate clock ID: 134
10720 17:17:17.621443 <6>[ 0.495943] KASLR enabled
10721 17:17:17.635132 <6>[ 0.503094] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10722 17:17:17.641567 <6>[ 0.510108] HugeTLB: 16380 KiB vmemmap can be freed for a 1.00 GiB page
10723 17:17:17.648387 <6>[ 0.516944] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10724 17:17:17.654839 <6>[ 0.523948] HugeTLB: 508 KiB vmemmap can be freed for a 32.0 MiB page
10725 17:17:17.661467 <6>[ 0.530605] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10726 17:17:17.667920 <6>[ 0.537610] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page
10727 17:17:17.674873 <6>[ 0.544184] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10728 17:17:17.681428 <6>[ 0.551189] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10729 17:17:17.687624 <6>[ 0.558532] ACPI: Interpreter disabled.
10730 17:17:17.694303 <6>[ 0.564614] iommu: Default domain type: Translated
10731 17:17:17.701036 <6>[ 0.569789] iommu: DMA domain TLB invalidation policy: strict mode
10732 17:17:17.704443 <5>[ 0.576454] SCSI subsystem initialized
10733 17:17:17.710976 <6>[ 0.580715] usbcore: registered new interface driver usbfs
10734 17:17:17.714014 <6>[ 0.586446] usbcore: registered new interface driver hub
10735 17:17:17.717592
10736 17:17:17.720556 <6>[ 0.591999] usbcore: registered new device driver usb
10737 17:17:17.727194 <6>[ 0.598080] pps_core: LinuxPPS API ver. 1 registered
10738 17:17:17.736873 <6>[ 0.603273] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10739 17:17:17.740000 <6>[ 0.612619] PTP clock support registered
10740 17:17:17.743413 <6>[ 0.616860] EDAC MC: Ver: 3.0.0
10741 17:17:17.750114 <6>[ 0.621474] FPGA manager framework
10742 17:17:17.753155 <6>[ 0.625149] Advanced Linux Sound Architecture Driver Initialized.
10743 17:17:17.756742
10744 17:17:17.760211 <6>[ 0.631916] vgaarb: loaded
10745 17:17:17.763402 <6>[ 0.635088] clocksource: Switched to clocksource arch_sys_counter
10746 17:17:17.766968
10747 17:17:17.770138 <5>[ 0.641532] VFS: Disk quotas dquot_6.6.0
10748 17:17:17.776529 <6>[ 0.645714] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10749 17:17:17.779680 <6>[ 0.652899] pnp: PnP ACPI: disabled
10750 17:17:17.788482 <6>[ 0.659494] NET: Registered PF_INET protocol family
10751 17:17:17.797952 <6>[ 0.665076] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10752 17:17:17.809505 <6>[ 0.677366] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10753 17:17:17.819254 <6>[ 0.686177] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10754 17:17:17.825276 <6>[ 0.694149] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10755 17:17:17.835596 <6>[ 0.702845] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10756 17:17:17.841841 <6>[ 0.712582] TCP: Hash tables configured (established 65536 bind 65536)
10757 17:17:17.848679 <6>[ 0.719440] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10758 17:17:17.858369 <6>[ 0.726639] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10759 17:17:17.865044 <6>[ 0.734342] NET: Registered PF_UNIX/PF_LOCAL protocol family
10760 17:17:17.871757 <6>[ 0.740508] RPC: Registered named UNIX socket transport module.
10761 17:17:17.875022 <6>[ 0.746664] RPC: Registered udp transport module.
10762 17:17:17.881584 <6>[ 0.751596] RPC: Registered tcp transport module.
10763 17:17:17.887944 <6>[ 0.756527] RPC: Registered tcp NFSv4.1 backchannel transport module.
10764 17:17:17.891338 <6>[ 0.763192] PCI: CLS 0 bytes, default 64
10765 17:17:17.894990 <6>[ 0.767621] Unpacking initramfs...
10766 17:17:17.904754 <6>[ 0.771364] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10767 17:17:17.911617 <6>[ 0.780032] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10768 17:17:17.918080 <6>[ 0.788887] kvm [1]: IPA Size Limit: 40 bits
10769 17:17:17.921116 <6>[ 0.793417] kvm [1]: GICv3: no GICV resource entry
10770 17:17:17.927957 <6>[ 0.798437] kvm [1]: disabling GICv2 emulation
10771 17:17:17.931404 <6>[ 0.803124] kvm [1]: GIC system register CPU interface enabled
10772 17:17:17.935006
10773 17:17:17.937993 <6>[ 0.809279] kvm [1]: vgic interrupt IRQ18
10774 17:17:17.941276 <6>[ 0.813635] kvm [1]: VHE mode initialized successfully
10775 17:17:17.949143 <5>[ 0.820043] Initialise system trusted keyrings
10776 17:17:17.955082 <6>[ 0.824907] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10777 17:17:17.964124 <6>[ 0.835214] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10778 17:17:17.970659 <5>[ 0.841653] NFS: Registering the id_resolver key type
10779 17:17:17.973812 <5>[ 0.846956] Key type id_resolver registered
10780 17:17:17.980132 <5>[ 0.851368] Key type id_legacy registered
10781 17:17:17.987373 <6>[ 0.855645] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10782 17:17:17.993711 <6>[ 0.862566] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10783 17:17:18.000649 <6>[ 0.870264] 9p: Installing v9fs 9p2000 file system support
10784 17:17:18.037371 <5>[ 0.908656] Key type asymmetric registered
10785 17:17:18.040932 <5>[ 0.912988] Asymmetric key parser 'x509' registered
10786 17:17:18.050375 <6>[ 0.918125] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
10787 17:17:18.053757 <6>[ 0.925738] io scheduler mq-deadline registered
10788 17:17:18.056962 <6>[ 0.930497] io scheduler kyber registered
10789 17:17:18.074306 <6>[ 0.945577] EINJ: ACPI disabled.
10790 17:17:18.097174 <4>[ 0.961664] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10791 17:17:18.106957 <4>[ 0.972291] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10792 17:17:18.118493 <6>[ 0.989909] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10793 17:17:18.126603 <6>[ 0.997971] printk: console [ttyS0] disabled
10794 17:17:18.154734 <6>[ 1.022616] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 254, base_baud = 1625000) is a ST16650V2
10795 17:17:18.161280 <6>[ 1.032086] printk: console [ttyS0] enabled
10796 17:17:18.164631 <6>[ 1.032086] printk: console [ttyS0] enabled
10797 17:17:18.171246 <6>[ 1.040981] printk: bootconsole [mtk8250] disabled
10798 17:17:18.174882 <6>[ 1.040981] printk: bootconsole [mtk8250] disabled
10799 17:17:18.181378 <6>[ 1.051946] SuperH (H)SCI(F) driver initialized
10800 17:17:18.184285 <6>[ 1.057208] msm_serial: driver initialized
10801 17:17:18.192269 <6>[ 1.066990] loop: module loaded
10802 17:17:18.195658
10803 17:17:18.202352 <6>[ 1.072924] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10804 17:17:18.224569 <4>[ 1.096109] mtk-pmic-keys: Failed to locate of_node [id: -1]
10805 17:17:18.231320 <6>[ 1.102710] megasas: 07.719.03.00-rc1
10806 17:17:18.241255 <6>[ 1.112481] tun: Universal TUN/TAP device driver, 1.6
10807 17:17:18.244158 <6>[ 1.118555] thunder_xcv, ver 1.0
10808 17:17:18.247795 <6>[ 1.122062] thunder_bgx, ver 1.0
10809 17:17:18.250761 <6>[ 1.125557] nicpf, ver 1.0
10810 17:17:18.261596 <6>[ 1.129549] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10811 17:17:18.264457 <6>[ 1.137027] hns3: Copyright (c) 2017 Huawei Corporation.
10812 17:17:18.271141 <6>[ 1.142621] hclge is initializing
10813 17:17:18.274747 <6>[ 1.146202] e1000: Intel(R) PRO/1000 Network Driver
10814 17:17:18.281314 <6>[ 1.151331] e1000: Copyright (c) 1999-2006 Intel Corporation.
10815 17:17:18.284239 <6>[ 1.157345] e1000e: Intel(R) PRO/1000 Network Driver
10816 17:17:18.291279 <6>[ 1.162560] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10817 17:17:18.297586 <6>[ 1.168745] igb: Intel(R) Gigabit Ethernet Network Driver
10818 17:17:18.304219 <6>[ 1.174395] igb: Copyright (c) 2007-2014 Intel Corporation.
10819 17:17:18.310717 <6>[ 1.180232] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10820 17:17:18.317533 <6>[ 1.186750] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10821 17:17:18.320622 <6>[ 1.193226] sky2: driver version 1.30
10822 17:17:18.327509 <6>[ 1.198083] VFIO - User Level meta-driver version: 0.3
10823 17:17:18.334572 <6>[ 1.206166] usbcore: registered new interface driver usb-storage
10824 17:17:18.343610 <6>[ 1.215138] mt6397-rtc mt6359-rtc: registered as rtc0
10825 17:17:18.353282 <6>[ 1.220614] mt6397-rtc mt6359-rtc: setting system clock to 2022-11-22T17:17:18 UTC (1669137438)
10826 17:17:18.356912 <6>[ 1.230074] i2c_dev: i2c /dev entries driver
10827 17:17:18.370645 <6>[ 1.239125] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10828 17:17:18.378102 <6>[ 1.249235] sdhci: Secure Digital Host Controller Interface driver
10829 17:17:18.384120 <6>[ 1.255673] sdhci: Copyright(c) Pierre Ossman
10830 17:17:18.391097 <6>[ 1.261030] Synopsys Designware Multimedia Card Interface Driver
10831 17:17:18.397388 <6>[ 1.268152] sdhci-pltfm: SDHCI platform and OF driver helper
10832 17:17:18.404344 <6>[ 1.276186] ledtrig-cpu: registered to indicate activity on CPUs
10833 17:17:18.415120 <6>[ 1.283666] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10834 17:17:18.418658 <6>[ 1.291066] usbcore: registered new interface driver usbhid
10835 17:17:18.425435 <6>[ 1.296896] usbhid: USB HID core driver
10836 17:17:18.431981 <6>[ 1.301138] spi_master spi0: will run message pump with realtime priority
10837 17:17:18.468664 <6>[ 1.333676] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10838 17:17:18.488371 <6>[ 1.350090] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10839 17:17:18.497548 <6>[ 1.369209] cros-ec-spi spi0.0: Chrome EC device registered
10840 17:17:18.519779 <6>[ 1.391553] NET: Registered PF_PACKET protocol family
10841 17:17:18.523449 <6>[ 1.396994] 9pnet: Installing 9P2000 support
10842 17:17:18.526372
10843 17:17:18.529467 <5>[ 1.401568] Key type dns_resolver registered
10844 17:17:18.533174 <6>[ 1.406559] registered taskstats version 1
10845 17:17:18.539559 <5>[ 1.410940] Loading compiled-in X.509 certificates
10846 17:17:18.566488 <4>[ 1.431762] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10847 17:17:18.576336 <4>[ 1.442487] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10848 17:17:18.584593 <6>[ 1.456494] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10849 17:17:18.591358 <6>[ 1.463206] xhci-mtk 11200000.usb: xHCI Host Controller
10850 17:17:18.597924 <6>[ 1.468714] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10851 17:17:18.608104 <6>[ 1.476563] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10852 17:17:18.614610 <6>[ 1.486009] xhci-mtk 11200000.usb: irq 262, io mem 0x11200000
10853 17:17:18.621474 <6>[ 1.492097] xhci-mtk 11200000.usb: xHCI Host Controller
10854 17:17:18.627601 <6>[ 1.497578] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10855 17:17:18.634601 <6>[ 1.505231] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10856 17:17:18.641406 <6>[ 1.513070] hub 1-0:1.0: USB hub found
10857 17:17:18.644575 <6>[ 1.517105] hub 1-0:1.0: 1 port detected
10858 17:17:18.654560 <6>[ 1.521470] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10859 17:17:18.657634 <6>[ 1.530326] hub 2-0:1.0: USB hub found
10860 17:17:18.661243 <6>[ 1.534407] hub 2-0:1.0: 1 port detected
10861 17:17:18.668441 <6>[ 1.540307] Freeing initrd memory: 18196K
10862 17:17:18.688268 <4>[ 1.553331] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10863 17:17:18.698260 <4>[ 1.564000] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10864 17:17:18.723597 <4>[ 1.588681] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10865 17:17:18.733271 <4>[ 1.599394] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10866 17:17:18.752865 <6>[ 1.624508] Trying to probe devices needed for running init ...
10867 17:17:18.766663 <4>[ 1.631344] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10868 17:17:18.776582 <4>[ 1.642075] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10869 17:17:18.785022 <3>[ 1.656147] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10870 17:17:18.791407 <3>[ 1.662691] i2c-mt65xx 11d00000.i2c: cannot get main clock
10871 17:17:18.798255 <3>[ 1.669241] i2c-mt65xx 11d20000.i2c: cannot get main clock
10872 17:17:18.804891 <3>[ 1.675730] i2c-mt65xx 11d21000.i2c: cannot get main clock
10873 17:17:18.811515 <3>[ 1.682247] i2c-mt65xx 11f00000.i2c: cannot get main clock
10874 17:17:18.821425 <6>[ 1.692883] mtk-msdc 11f70000.mmc: Got CD GPIO
10875 17:17:18.831445 <4>[ 1.698674] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10876 17:17:18.844768 <4>[ 1.709367] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10877 17:17:19.051560 <6>[ 1.919512] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10878 17:17:19.077994 <6>[ 1.949244] hub 2-1:1.0: USB hub found
10879 17:17:19.081657 <6>[ 1.953603] hub 2-1:1.0: 3 ports detected
10880 17:17:19.107877 <4>[ 1.972696] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10881 17:17:19.117943 <4>[ 1.983425] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10882 17:17:19.203472 <6>[ 2.071261] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10883 17:17:19.355708 <6>[ 2.227221] hub 1-1:1.0: USB hub found
10884 17:17:19.358857 <6>[ 2.231580] hub 1-1:1.0: 4 ports detected
10885 17:17:19.387002 <4>[ 2.251770] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10886 17:17:19.397156 <4>[ 2.262495] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10887 17:17:19.678918 <6>[ 2.547221] usb 1-1.1: new high-speed USB device number 3 using xhci-mtk
10888 17:17:19.809928 <6>[ 2.681192] hub 1-1.1:1.0: USB hub found
10889 17:17:19.813529 <6>[ 2.685477] hub 1-1.1:1.0: 4 ports detected
10890 17:17:19.840327 <4>[ 2.704757] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10891 17:17:19.850087 <4>[ 2.715483] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10892 17:17:19.940038 <6>[ 2.807362] usb 1-1.4: new high-speed USB device number 4 using xhci-mtk
10893 17:17:20.072471 <6>[ 2.943418] hub 1-1.4:1.0: USB hub found
10894 17:17:20.076613 <6>[ 2.948106] hub 1-1.4:1.0: 2 ports detected
10895 17:17:20.093754 <4>[ 2.957975] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10896 17:17:20.102652 <4>[ 2.968976] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10897 17:17:20.127877 <4>[ 2.993341] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10898 17:17:20.138120 <4>[ 3.004111] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10899 17:17:20.158785 <6>[ 3.027226] usb 1-1.1.1: new high-speed USB device number 5 using xhci-mtk
10900 17:17:20.282626 <4>[ 3.147536] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10901 17:17:20.292102 <4>[ 3.158266] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10902 17:17:20.378648 <6>[ 3.247330] usb 1-1.4.1: new high-speed USB device number 6 using xhci-mtk
10903 17:17:20.506734 <4>[ 3.371774] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10904 17:17:20.517080 <4>[ 3.382499] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10905 17:17:20.571143 <6>[ 3.439336] usb 1-1.4.2: new high-speed USB device number 7 using xhci-mtk
10906 17:17:20.700070 <4>[ 3.565537] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10907 17:17:20.710274 <4>[ 3.576255] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10908 17:17:28.981668 <3>[ 11.853490] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10909 17:17:28.989229 <3>[ 11.860175] i2c-mt65xx 11d00000.i2c: cannot get main clock
10910 17:17:28.996529 <3>[ 11.866551] i2c-mt65xx 11d20000.i2c: cannot get main clock
10911 17:17:29.003810 <3>[ 11.872888] i2c-mt65xx 11d21000.i2c: cannot get main clock
10912 17:17:29.007783 <3>[ 11.879222] i2c-mt65xx 11f00000.i2c: cannot get main clock
10913 17:17:29.029476 <4>[ 11.895259] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10914 17:17:29.032496 <6>[ 11.895673] mtk-msdc 11f70000.mmc: Got CD GPIO
10915 17:17:29.042541 <4>[ 11.905955] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10916 17:17:29.049846 <6>[ 11.922201] platform 14001000.mutex: deferred probe pending
10917 17:17:29.056319 <6>[ 11.928046] platform 1401d000.m4u: deferred probe pending
10918 17:17:29.063352 <6>[ 11.933698] platform 11cb0000.i2c: deferred probe pending
10919 17:17:29.066428 <6>[ 11.939349] platform 11d00000.i2c: deferred probe pending
10920 17:17:29.072807 <6>[ 11.944999] platform 11d20000.i2c: deferred probe pending
10921 17:17:29.079320 <6>[ 11.950657] platform 11d21000.i2c: deferred probe pending
10922 17:17:29.082451 <6>[ 11.956312] platform 11f00000.i2c: deferred probe pending
10923 17:17:29.086109
10924 17:17:29.089266 <6>[ 11.961963] platform pwmleds: deferred probe pending
10925 17:17:29.095795 <6>[ 11.967180] platform 14002000.smi: deferred probe pending
10926 17:17:29.102251 <6>[ 11.972830] platform 14003000.larb: deferred probe pending
10927 17:17:29.105652 <6>[ 11.978568] platform 14004000.larb: deferred probe pending
10928 17:17:29.112196 <6>[ 11.984304] platform 1502e000.larb: deferred probe pending
10929 17:17:29.119258 <6>[ 11.990041] platform 1582e000.larb: deferred probe pending
10930 17:17:29.122247 <6>[ 11.995778] platform 1600d000.larb: deferred probe pending
10931 17:17:29.128613 <6>[ 12.001515] platform 1602e000.larb: deferred probe pending
10932 17:17:29.135788 <6>[ 12.007252] platform 17010000.larb: deferred probe pending
10933 17:17:29.141985 <6>[ 12.012988] platform 1a001000.larb: deferred probe pending
10934 17:17:29.145105 <6>[ 12.018725] platform 1a002000.larb: deferred probe pending
10935 17:17:29.151787 <6>[ 12.024462] platform 1a00f000.larb: deferred probe pending
10936 17:17:29.158833 <6>[ 12.030210] platform 1a010000.larb: deferred probe pending
10937 17:17:29.165523 <6>[ 12.035951] platform 1a011000.larb: deferred probe pending
10938 17:17:29.168713 <6>[ 12.041688] platform 1b00f000.larb: deferred probe pending
10939 17:17:29.175869 <6>[ 12.047424] platform 11f60000.mmc: deferred probe pending
10940 17:17:29.181864 <6>[ 12.053075] platform 1b10f000.larb: deferred probe pending
10941 17:17:29.188361 <6>[ 12.058818] platform 1f002000.larb: deferred probe pending
10942 17:17:29.194729 <6>[ 12.064556] platform 10006000.syscon:power-controller: deferred probe pending
10943 17:17:31.247239 <6>[ 14.123732] ALSA device list:
10944 17:17:31.253890 <6>[ 14.126968] No soundcards found.
10945 17:17:31.265428 <6>[ 14.138607] Freeing unused kernel memory: 7616K
10946 17:17:31.269026 <6>[ 14.143485] Run /init as init process
10947 17:17:31.278609 Loading, please wait...
10948 17:17:31.298146 Starting version 247.3-7+deb11u1
10949 17:17:31.579442 <6>[ 14.449469] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10950 17:17:31.588932 <6>[ 14.462322] remoteproc remoteproc0: scp is available
10951 17:17:31.598775 <4>[ 14.468651] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10952 17:17:31.605766 <6>[ 14.478576] remoteproc remoteproc0: powering up scp
10953 17:17:31.615823 <4>[ 14.483754] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10954 17:17:31.626595 <3>[ 14.499750] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10955 17:17:31.633256 <6>[ 14.502874] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 1
10956 17:17:31.644776 <3>[ 14.503762] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10957 17:17:31.649004 <3>[ 14.504300] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10958 17:17:31.664636 <3>[ 14.504317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10959 17:17:31.667702 <3>[ 14.505546] remoteproc remoteproc0: request_firmware failed: -2
10960 17:17:31.684059 <3>[ 14.505665] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10961 17:17:31.684994 <3>[ 14.505682] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10962 17:17:31.689249 <3>[ 14.505694] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10963 17:17:31.699905 <3>[ 14.505706] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10964 17:17:31.710361 <3>[ 14.505715] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10965 17:17:31.713234 <3>[ 14.505803] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10966 17:17:31.719588 <3>[ 14.505877] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10967 17:17:31.729686 <3>[ 14.505887] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10968 17:17:31.736356 <3>[ 14.505896] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10969 17:17:31.746401 <3>[ 14.505974] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10970 17:17:31.753198 <3>[ 14.505984] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10971 17:17:31.762934 <3>[ 14.505993] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10972 17:17:31.769707 <3>[ 14.506003] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10973 17:17:31.779770 <3>[ 14.506012] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10974 17:17:31.786104 <6>[ 14.506035] sbs-battery 0-000b: sbs-battery: battery gas gauge device registered
10975 17:17:31.793001 <3>[ 14.506063] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10976 17:17:31.799349 <6>[ 14.521667] usbcore: registered new interface driver r8152
10977 17:17:31.806115 <6>[ 14.527953] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10978 17:17:31.812930 <3>[ 14.530414] i2c-mt65xx 11d00000.i2c: cannot get main clock
10979 17:17:31.820187 <4>[ 14.549992] sbs-battery 0-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10980 17:17:31.827034 <4>[ 14.549992] Fallback method does not support PEC.
10981 17:17:31.830148 <3>[ 14.565748] i2c-mt65xx 11d20000.i2c: cannot get main clock
10982 17:17:31.836642 <6>[ 14.585208] mc: Linux media interface: v0.10
10983 17:17:31.846857 <6>[ 14.589389] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10984 17:17:31.853204 <3>[ 14.597907] i2c-mt65xx 11d21000.i2c: cannot get main clock
10985 17:17:31.860075 <3>[ 14.601178] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
10986 17:17:31.863128
10987 17:17:31.866675 <3>[ 14.611280] i2c-mt65xx 11f00000.i2c: cannot get main clock
10988 17:17:31.869962 <6>[ 14.617308] Bluetooth: Core ver 2.22
10989 17:17:31.876406 <6>[ 14.625417] videodev: Linux video capture interface: v2.00
10990 17:17:31.883230 <6>[ 14.632104] NET: Registered PF_BLUETOOTH protocol family
10991 17:17:31.889509 <6>[ 14.632723] usbcore: registered new interface driver cdc_ether
10992 17:17:31.892595 <6>[ 14.641804] usbcore: registered new interface driver r8153_ecm
10993 17:17:31.896289
10994 17:17:31.903067 <6>[ 14.646283] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14005000
10995 17:17:31.913025 <6>[ 14.646358] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14006000
10996 17:17:31.919560 <6>[ 14.646403] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14007000
10997 17:17:31.929639 <6>[ 14.646439] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/color@14009000
10998 17:17:31.936183 <6>[ 14.646475] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ccorr@1400a000
10999 17:17:31.945982 <6>[ 14.646514] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/aal@1400b000
11000 17:17:31.955896 <6>[ 14.646561] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/gamma@1400c000
11001 17:17:31.962650 <6>[ 14.648142] Bluetooth: HCI device and connection manager initialized
11002 17:17:31.965694 <6>[ 14.648205] Bluetooth: HCI socket layer initialized
11003 17:17:31.972466 <6>[ 14.648220] Bluetooth: L2CAP socket layer initialized
11004 17:17:31.975790 <6>[ 14.648265] Bluetooth: SCO socket layer initialized
11005 17:17:31.985726 <6>[ 14.656999] usb 1-1.1.1: reset high-speed USB device number 5 using xhci-mtk
11006 17:17:31.995453 <4>[ 14.660950] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
11007 17:17:32.005415 <4>[ 14.661203] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
11008 17:17:32.009035 <6>[ 14.669678] mtk-msdc 11f70000.mmc: Got CD GPIO
11009 17:17:32.015747 <3>[ 14.669738] i2c-mt65xx 11cb0000.i2c: cannot get main clock
11010 17:17:32.022302 <3>[ 14.671432] i2c-mt65xx 11d00000.i2c: cannot get main clock
11011 17:17:32.028809 <3>[ 14.673603] i2c-mt65xx 11d20000.i2c: cannot get main clock
11012 17:17:32.035436 <3>[ 14.699281] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11013 17:17:32.041913 <3>[ 14.706002] i2c-mt65xx 11d21000.i2c: cannot get main clock
11014 17:17:32.048361 <6>[ 14.710296] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
11015 17:17:32.055220 <6>[ 14.710459] usbcore: registered new interface driver btusb
11016 17:17:32.062229 <3>[ 14.715776] i2c-mt65xx 11f00000.i2c: cannot get main clock
11017 17:17:32.072157 <6>[ 14.726401] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input2
11018 17:17:32.081516 <6>[ 14.738509] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14005000
11019 17:17:32.088290 <6>[ 14.739834] usbcore: registered new interface driver uvcvideo
11020 17:17:32.095099 <6>[ 14.745324] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14006000
11021 17:17:32.105060 <4>[ 14.778963] r8152 1-1.1.1:1.0: Direct firmware load for rtl_nic/rtl8153b-2.fw failed with error -2
11022 17:17:32.114756 <6>[ 14.781131] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14007000
11023 17:17:32.121522 <4>[ 14.789639] r8152 1-1.1.1:1.0: unable to load firmware patch rtl_nic/rtl8153b-2.fw (-2)
11024 17:17:32.131207 <6>[ 14.798256] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/color@14009000
11025 17:17:32.134718 <6>[ 14.844591] r8152 1-1.1.1:1.0 eth0: v1.12.13
11026 17:17:32.144856 <6>[ 14.849929] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ccorr@1400a000
11027 17:17:32.151144 <6>[ 14.863571] r8152 1-1.1.1:1.0 enxf4f5e850de0a: renamed from eth0
11028 17:17:32.157637 <6>[ 14.872985] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/aal@1400b000
11029 17:17:32.167608 <6>[ 15.036469] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/gamma@1400c000
11030 17:17:32.187780 <4>[ 15.054516] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
11031 17:17:32.198229 <4>[ 15.065302] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
11032 17:17:32.206675 <3>[ 15.079695] i2c-mt65xx 11cb0000.i2c: cannot get main clock
11033 17:17:32.217057 Begin: Loading essential drivers<3>[ 15.086828] i2c-mt65xx 11d00000.i2c: cannot get main clock
11034 17:17:32.217396 ... done.
11035 17:17:32.224015 Begin: Running /scri<3>[ 15.096512] i2c-mt65xx 11d20000.i2c: cannot get main clock
11036 17:17:32.230735 pts/init-premoun<6>[ 15.096894] mtk-msdc 11f70000.mmc: Got CD GPIO
11037 17:17:32.234392 t ... done.
11038 17:17:32.237898 Beg<3>[ 15.105345] i2c-mt65xx 11d21000.i2c: cannot get main clock
11039 17:17:32.247522 in: Mounting root file system ..<3>[ 15.118306] i2c-mt65xx 11f00000.i2c: cannot get main clock
11040 17:17:32.250329 . Begin: Running /scripts/nfs-top ... done.
11041 17:17:32.252932 Begin: Running /scripts/nfs-premount ... done.
11042 17:17:32.263206 <6>[ 15.132395] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14005000
11043 17:17:32.272950 <6>[ 15.141162] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14006000
11044 17:17:32.279691 <6>[ 15.149711] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14007000
11045 17:17:32.289493 <6>[ 15.158341] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/color@14009000
11046 17:17:32.295897 <6>[ 15.167048] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ccorr@1400a000
11047 17:17:32.306332 <6>[ 15.175763] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/aal@1400b000
11048 17:17:32.315770 <6>[ 15.184305] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/gamma@1400c000
11049 17:17:32.342449 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
11050 17:17:33.622613 <6>[ 16.493978] r8152 1-1.1.1:1.0 enxf4f5e850de0a: carrier on
11051 17:17:33.843466 <3>[ 16.715140] Bluetooth: hci0: Opcode 0x c03 failed: -110
11052 17:17:33.848708 IP-Config: no response after 2 secs - giving up
11053 17:17:33.892168 IP-Config: enxf4f5e850de0a hardware address f4:f5:e8:50:de:0a mtu 1500 DHCP
11054 17:17:33.897518
11055 17:17:33.897920 IP-Config: enxf4f5e850de0a complete (dhcp from 192.168.201.1):
11056 17:17:33.908022 address: 192.168.201.14 broadcast: 192.168.201.255 netmask: 255.255.255.0
11057 17:17:33.913217 gateway: 192.168.201.1 dns0 : 192.168.201.1 dns1 : 0.0.0.0
11058 17:17:33.920460 host : mt8192-asurada-spherion-r0-cbg-9
11059 17:17:33.926098 domain : lava-rack
11060 17:17:33.929366 rootserver: 192.168.201.1 rootpath:
11061 17:17:33.929555 filename :
11062 17:17:34.026686 done.
11063 17:17:34.035673 Begin: Running /scripts/nfs-bottom ... done.
11064 17:17:34.052652 Begin: Running /scripts/init-bottom ... done.
11065 17:17:35.135905 <6>[ 18.007578] NET: Registered PF_INET6 protocol family
11066 17:17:35.146215 <6>[ 18.014531] Segment Routing with IPv6
11067 17:17:35.146644 <6>[ 18.018518] In-situ OAM (IOAM) with IPv6
11068 17:17:35.258220 <30>[ 18.110366] systemd[1]: systemd 247.3-7+deb11u1 running in system mode. (+PAM +AUDIT +SELINUX +IMA +APPARMOR +SMACK +SYSVINIT +UTMP +LIBCRYPTSETUP +GCRYPT +GNUTLS +ACL +XZ +LZ4 +ZSTD +SECCOMP +BLKID +ELFUTILS +KMOD +IDN2 -IDN +PCRE2 default-hierarchy=unified)
11069 17:17:35.263813 <30>[ 18.134135] systemd[1]: Detected architecture arm64.
11070 17:17:35.280271
11071 17:17:35.283799 Welcome to [1mDebian GNU/Linux 11 (bullseye)[0m!
11072 17:17:35.284037
11073 17:17:35.300431 <30>[ 18.173808] systemd[1]: Set hostname to <debian-bullseye-arm64>.
11074 17:17:35.805341 <30>[ 18.675556] systemd[1]: Queued start job for default target Graphical Interface.
11075 17:17:35.822918 <30>[ 18.696390] systemd[1]: Created slice system-getty.slice.
11076 17:17:35.829302 [[0;32m OK [0m] Created slice [0;1;39msystem-getty.slice[0m.
11077 17:17:35.846361 <30>[ 18.720035] systemd[1]: Created slice system-modprobe.slice.
11078 17:17:35.853358 [[0;32m OK [0m] Created slice [0;1;39msystem-modprobe.slice[0m.
11079 17:17:35.872653 <30>[ 18.743879] systemd[1]: Created slice system-serial\x2dgetty.slice.
11080 17:17:35.883078 [[0;32m OK [0m] Created slice [0;1;39msystem-serial\x2dgetty.slice[0m.
11081 17:17:35.898087 <30>[ 18.768755] systemd[1]: Created slice User and Session Slice.
11082 17:17:35.903662 [[0;32m OK [0m] Created slice [0;1;39mUser and Session Slice[0m.
11083 17:17:35.925088 <30>[ 18.791524] systemd[1]: Started Dispatch Password Requests to Console Directory Watch.
11084 17:17:35.930615 [[0;32m OK [0m] Started [0;1;39mDispatch Password …ts to Console Directory Watch[0m.
11085 17:17:35.936312
11086 17:17:35.947177 <30>[ 18.815511] systemd[1]: Started Forward Password Requests to Wall Directory Watch.
11087 17:17:35.952805 [[0;32m OK [0m] Started [0;1;39mForward Password R…uests to Wall Directory Watch[0m.
11088 17:17:35.973076 <30>[ 18.839474] systemd[1]: Condition check resulted in Arbitrary Executable File Formats File System Automount Point being skipped.
11089 17:17:35.979146 <30>[ 18.851490] systemd[1]: Reached target Local Encrypted Volumes.
11090 17:17:35.985732 [[0;32m OK [0m] Reached target [0;1;39mLocal Encrypted Volumes[0m.
11091 17:17:36.002126 <30>[ 18.875730] systemd[1]: Reached target Paths.
11092 17:17:36.005816 [[0;32m OK [0m] Reached target [0;1;39mPaths[0m.
11093 17:17:36.022233 <30>[ 18.895536] systemd[1]: Reached target Remote File Systems.
11094 17:17:36.028652 [[0;32m OK [0m] Reached target [0;1;39mRemote File Systems[0m.
11095 17:17:36.046181 <30>[ 18.919414] systemd[1]: Reached target Slices.
11096 17:17:36.049414 [[0;32m OK [0m] Reached target [0;1;39mSlices[0m.
11097 17:17:36.065897 <30>[ 18.939410] systemd[1]: Reached target Swap.
11098 17:17:36.069083 [[0;32m OK [0m] Reached target [0;1;39mSwap[0m.
11099 17:17:36.089472 <30>[ 18.959708] systemd[1]: Listening on initctl Compatibility Named Pipe.
11100 17:17:36.096102 [[0;32m OK [0m] Listening on [0;1;39minitctl Compatibility Named Pipe[0m.
11101 17:17:36.102817 <30>[ 18.975024] systemd[1]: Listening on Journal Audit Socket.
11102 17:17:36.109137 [[0;32m OK [0m] Listening on [0;1;39mJournal Audit Socket[0m.
11103 17:17:36.123051 <30>[ 18.996240] systemd[1]: Listening on Journal Socket (/dev/log).
11104 17:17:36.129422 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket (/dev/log)[0m.
11105 17:17:36.147114 <30>[ 19.020108] systemd[1]: Listening on Journal Socket.
11106 17:17:36.153265 [[0;32m OK [0m] Listening on [0;1;39mJournal Socket[0m.
11107 17:17:36.167143 <30>[ 19.040765] systemd[1]: Listening on Network Service Netlink Socket.
11108 17:17:36.170583
11109 17:17:36.177260 [[0;32m OK [0m] Listening on [0;1;39mNetwork Service Netlink Socket[0m.
11110 17:17:36.192468 <30>[ 19.065722] systemd[1]: Listening on udev Control Socket.
11111 17:17:36.198509 [[0;32m OK [0m] Listening on [0;1;39mudev Control Socket[0m.
11112 17:17:36.216568 <30>[ 19.087587] systemd[1]: Listening on udev Kernel Socket.
11113 17:17:36.223948 [[0;32m OK [0m] Listening on [0;1;39mudev Kernel Socket[0m.
11114 17:17:36.253956 <30>[ 19.127583] systemd[1]: Mounting Huge Pages File System...
11115 17:17:36.260640 Mounting [0;1;39mHuge Pages File System[0m...
11116 17:17:36.275937 <30>[ 19.149540] systemd[1]: Mounting POSIX Message Queue File System...
11117 17:17:36.282517 Mounting [0;1;39mPOSIX Message Queue File System[0m...
11118 17:17:36.300133 <30>[ 19.173645] systemd[1]: Mounting Kernel Debug File System...
11119 17:17:36.306675 Mounting [0;1;39mKernel Debug File System[0m...
11120 17:17:36.325120 <30>[ 19.195656] systemd[1]: Condition check resulted in Kernel Trace File System being skipped.
11121 17:17:36.389622 <30>[ 19.259985] systemd[1]: Starting Create list of static device nodes for the current kernel...
11122 17:17:36.395967 Starting [0;1;39mCreate list of st…odes for the current kernel[0m...
11123 17:17:36.416066 <30>[ 19.289899] systemd[1]: Starting Load Kernel Module configfs...
11124 17:17:36.423070 Starting [0;1;39mLoad Kernel Module configfs[0m...
11125 17:17:36.440393 <30>[ 19.313841] systemd[1]: Starting Load Kernel Module drm...
11126 17:17:36.446696 Starting [0;1;39mLoad Kernel Module drm[0m...
11127 17:17:36.464671 <30>[ 19.337992] systemd[1]: Starting Load Kernel Module fuse...
11128 17:17:36.470742 Starting [0;1;39mLoad Kernel Module fuse[0m...
11129 17:17:36.502704 <6>[ 19.374302] fuse: init (API version 7.37)
11130 17:17:36.513534 <30>[ 19.375722] systemd[1]: Condition check resulted in Set Up Additional Binary Formats being skipped.
11131 17:17:36.519063 <30>[ 19.392311] systemd[1]: Starting Journal Service...
11132 17:17:36.524349 Starting [0;1;39mJournal Service[0m...
11133 17:17:36.548513 <30>[ 19.421822] systemd[1]: Starting Load Kernel Modules...
11134 17:17:36.554664 Starting [0;1;39mLoad Kernel Modules[0m...
11135 17:17:36.575105 <30>[ 19.445674] systemd[1]: Starting Remount Root and Kernel File Systems...
11136 17:17:36.581586 Starting [0;1;39mRemount Root and Kernel File Systems[0m...
11137 17:17:36.597594 <30>[ 19.470961] systemd[1]: Starting Coldplug All udev Devices...
11138 17:17:36.603895 Starting [0;1;39mColdplug All udev Devices[0m...
11139 17:17:36.620929 <30>[ 19.494611] systemd[1]: Mounted Huge Pages File System.
11140 17:17:36.627598 [[0;32m OK [0m] Mounted [0;1;39mHuge Pages File System[0m.
11141 17:17:36.642102 <30>[ 19.515868] systemd[1]: Mounted POSIX Message Queue File System.
11142 17:17:36.648981 [[0;32m OK [0m] Mounted [0;1;39mPOSIX Message Queue File System[0m.
11143 17:17:36.666532 <30>[ 19.539683] systemd[1]: Mounted Kernel Debug File System.
11144 17:17:36.676181 <3>[ 19.542771] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11145 17:17:36.683118 [[0;32m OK [0m] Mounted [0;1;39mKernel Debug File System[0m.
11146 17:17:36.703077 <30>[ 19.572560] systemd[1]: Finished Create list of static device nodes for the current kernel.
11147 17:17:36.716132 [[0;32m OK [0m] Finished [0;1;39mCreate lis<3>[ 19.584529] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11148 17:17:36.719669 t of st… nodes for the current kernel[0m.
11149 17:17:36.734669 <30>[ 19.608404] systemd[1]: modprobe@configfs.service: Succeeded.
11150 17:17:36.741797 <30>[ 19.615062] systemd[1]: Finished Load Kernel Module configfs.
11151 17:17:36.748488 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module configfs[0m.
11152 17:17:36.759731 <3>[ 19.630121] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11153 17:17:36.766527 <30>[ 19.640423] systemd[1]: modprobe@drm.service: Succeeded.
11154 17:17:36.773165 <30>[ 19.646684] systemd[1]: Finished Load Kernel Module drm.
11155 17:17:36.779755 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module drm[0m.
11156 17:17:36.796254 <3>[ 19.666615] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11157 17:17:36.803269 <30>[ 19.676801] systemd[1]: modprobe@fuse.service: Succeeded.
11158 17:17:36.809578 <30>[ 19.683144] systemd[1]: Finished Load Kernel Module fuse.
11159 17:17:36.816520 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Module fuse[0m.
11160 17:17:36.832540 <3>[ 19.702566] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11161 17:17:36.839391 <30>[ 19.713176] systemd[1]: Finished Load Kernel Modules.
11162 17:17:36.846145 [[0;32m OK [0m] Finished [0;1;39mLoad Kernel Modules[0m.
11163 17:17:36.868915 <30>[ 19.733098] systemd[1]: Finished Remount Root and Kernel File Systems.
11164 17:17:36.875600 <3>[ 19.739336] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11165 17:17:36.882455 [[0;32m OK [0m] Finished [0;1;39mRemount Root and Kernel File Systems[0m.
11166 17:17:36.906242 <3>[ 19.776466] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11167 17:17:36.918106 <30>[ 19.791221] systemd[1]: Mounting FUSE Control File System...
11168 17:17:36.924961 Mounting [0;1;39mFUSE Control File System[0m...
11169 17:17:36.941362 <3>[ 19.811824] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11170 17:17:36.948145 <30>[ 19.813840] systemd[1]: Mounting Kernel Configuration File System...
11171 17:17:36.954275 Mounting [0;1;39mKernel Configuration File System[0m...
11172 17:17:36.976984 <3>[ 19.847244] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11173 17:17:36.986674 <30>[ 19.847859] systemd[1]: Condition check resulted in Rebuild Hardware Database being skipped.
11174 17:17:36.997290 <30>[ 19.865046] systemd[1]: Condition check resulted in Platform Persistent Storage Archival being skipped.
11175 17:17:37.009044 <3>[ 19.879412] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11176 17:17:37.038803 <30>[ 19.911938] systemd[1]: Starting Load/Save Random Seed...
11177 17:17:37.045902 Starting [0;1;39mLoad/Save Random Seed[0m...
11178 17:17:37.052039 <3>[ 19.922279] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11179 17:17:37.062182 <30>[ 19.935384] systemd[1]: Starting Apply Kernel Variables...
11180 17:17:37.072325 Startin<3>[ 19.941816] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
11181 17:17:37.075503 g [0;1;39mApply Kernel Variables[0m...
11182 17:17:37.093293 <30>[ 19.966728] systemd[1]: Starting Create System Users...
11183 17:17:37.099479 Starting [0;1;39mCreate System Users[0m...
11184 17:17:37.116094 <30>[ 19.989518] systemd[1]: Mounted FUSE Control File System.
11185 17:17:37.122315 [[0;32m OK [0m] Mounted [0;1;39mFUSE Control File System[0m.
11186 17:17:37.138055 <30>[ 20.011808] systemd[1]: Mounted Kernel Configuration File System.
11187 17:17:37.154289 <4>[ 20.014746] synth uevent: /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:i2c-tunnel/i2c-0/0-000b/power_supply/sbs-0-000b: failed to send uevent
11188 17:17:37.161122 <3>[ 20.033923] power_supply sbs-0-000b: uevent: failed to send synthetic uevent: -5
11189 17:17:37.164302
11190 17:17:37.170756 [[0;32m OK [0m] Mounted [0;1;39mKernel Configuration File System[0m.
11191 17:17:37.190006 <30>[ 20.060019] systemd[1]: Started Journal Service.
11192 17:17:37.197196 [[0;32m OK [0m] Started [0;1;39mJournal Service[0m.
11193 17:17:37.212654 [[0;1;31mFAILED[0m] Failed to start [0;1;39mColdplug All udev Devices[0m.
11194 17:17:37.225941 See 'systemctl status systemd-udev-trigger.service' for details.
11195 17:17:37.243193 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Random Seed[0m.
11196 17:17:37.258416 [[0;32m OK [0m] Finished [0;1;39mApply Kernel Variables[0m.
11197 17:17:37.274358 [[0;32m OK [0m] Finished [0;1;39mCreate System Users[0m.
11198 17:17:37.311832 Starting [0;1;39mFlush Journal to Persistent Storage[0m...
11199 17:17:37.328486 Starting [0;1;39mCreate Static Device Nodes in /dev[0m...
11200 17:17:37.359931 <46>[ 20.230701] systemd-journald[264]: Received client request to flush runtime journal.
11201 17:17:37.386920 [[0;32m OK [0m] Finished [0;1;39mCreate Static Device Nodes in /dev[0m.
11202 17:17:37.401934 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems (Pre)[0m.
11203 17:17:37.421994 [[0;32m OK [0m] Reached target [0;1;39mLocal File Systems[0m.
11204 17:17:37.478043 Starting [0;1;39mRule-based Manage…for Device Events and Files[0m...
11205 17:17:38.723544 [[0;32m OK [0m] Finished [0;1;39mFlush Journal to Persistent Storage[0m.
11206 17:17:38.766196 Starting [0;1;39mCreate Volatile Files and Directories[0m...
11207 17:17:38.786421 [[0;32m OK [0m] Started [0;1;39mRule-based Manager for Device Events and Files[0m.
11208 17:17:38.809463 Starting [0;1;39mNetwork Service[0m...
11209 17:17:39.115839 [[0;32m OK [0m] Created slice [0;1;39msystem-systemd\x2dbacklight.slice[0m.
11210 17:17:39.190932 Starting [0;1;39mLoad/Save Screen …of leds:white:kbd_backlight[0m...
11211 17:17:39.218406 [[0;32m OK [0m] Found device [0;1;39m/dev/ttyS0[0m.
11212 17:17:39.354620 [[0;32m OK [0m] Listening on [0;1;39mLoad/Save RF …itch Status /dev/rfkill Watch[0m.
11213 17:17:39.398387 [[0;32m OK [0m] Reached target [0;1;39mBluetooth[0m.
11214 17:17:39.446417 Starting [0;1;39mLoad/Save RF Kill Switch Status[0m...
11215 17:17:39.466912 [[0;32m OK [0m] Started [0;1;39mNetwork Service[0m.
11216 17:17:39.484057 [[0;32m OK [0m] Finished [0;1;39mLoad/Save Screen …s of leds:white:kbd_backlight[0m.
11217 17:17:39.512927 [[0;32m OK [0m] Started [0;1;39mLoad/Save RF Kill Switch Status[0m.
11218 17:17:39.530051 [[0;32m OK [0m] Finished [0;1;39mCreate Volatile Files and Directories[0m.
11219 17:17:39.573661 Starting [0;1;39mNetwork Name Resolution[0m...
11220 17:17:39.596156 Starting [0;1;39mNetwork Time Synchronization[0m...
11221 17:17:39.611812 Starting [0;1;39mUpdate UTMP about System Boot/Shutdown[0m...
11222 17:17:39.648987 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Boot/Shutdown[0m.
11223 17:17:39.835291 [[0;32m OK [0m] Started [0;1;39mNetwork Time Synchronization[0m.
11224 17:17:39.858033 [[0;32m OK [0m] Reached target [0;1;39mSystem Initialization[0m.
11225 17:17:39.873693 [[0;32m OK [0m] Started [0;1;39mDaily Cleanup of Temporary Directories[0m.
11226 17:17:39.887412 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Set[0m.
11227 17:17:39.901228 [[0;32m OK [0m] Reached target [0;1;39mSystem Time Synchronized[0m.
11228 17:17:40.027577 [[0;32m OK [0m] Started [0;1;39mDaily apt download activities[0m.
11229 17:17:40.057131 [[0;32m OK [0m] Started [0;1;39mDaily apt upgrade and clean activities[0m.
11230 17:17:40.081486 [[0;32m OK [0m] Started [0;1;39mPeriodic ext4 Onli…ata Check for All Filesystems[0m.
11231 17:17:40.099005 [[0;32m OK [0m] Started [0;1;39mDiscard unused blocks once a week[0m.
11232 17:17:40.102183
11233 17:17:40.117639 [[0;32m OK [0m] Reached target [0;1;39mTimers[0m.
11234 17:17:40.152771 [[0;32m OK [0m] Listening on [0;1;39mD-Bus System Message Bus Socket[0m.
11235 17:17:40.169675 [[0;32m OK [0m] Reached target [0;1;39mSockets[0m.
11236 17:17:40.193155 [[0;32m OK [0m] Reached target [0;1;39mBasic System[0m.
11237 17:17:40.233827 [[0;32m OK [0m] Started [0;1;39mD-Bus System Message Bus[0m.
11238 17:17:40.264414 Starting [0;1;39mRemove Stale Onli…t4 Metadata Check Snapshots[0m...
11239 17:17:40.330161 Starting [0;1;39mUser Login Management[0m...
11240 17:17:40.346226 [[0;32m OK [0m] Started [0;1;39mNetwork Name Resolution[0m.
11241 17:17:40.362795 [[0;32m OK [0m] Reached target [0;1;39mNetwork[0m.
11242 17:17:40.384685 [[0;32m OK [0m] Reached target [0;1;39mHost and Network Name Lookups[0m.
11243 17:17:40.404017 Starting [0;1;39mPermit User Sessions[0m...
11244 17:17:40.528559 [[0;32m OK [0m] Finished [0;1;39mPermit User Sessions[0m.
11245 17:17:40.555752 [[0;32m OK [0m] Finished [0;1;39mRemove Stale Onli…ext4 Metadata Check Snapshots[0m.
11246 17:17:40.626844 [[0;32m OK [0m] Started [0;1;39mGetty on tty1[0m.
11247 17:17:40.644746 [[0;32m OK [0m] Started [0;1;39mSerial Getty on ttyS0[0m.
11248 17:17:40.659345 [[0;32m OK [0m] Reached target [0;1;39mLogin Prompts[0m.
11249 17:17:40.678602 [[0;32m OK [0m] Started [0;1;39mUser Login Management[0m.
11250 17:17:40.698583 [[0;32m OK [0m] Reached target [0;1;39mMulti-User System[0m.
11251 17:17:40.714300 [[0;32m OK [0m] Reached target [0;1;39mGraphical Interface[0m.
11252 17:17:40.746678 Starting [0;1;39mUpdate UTMP about System Runlevel Changes[0m...
11253 17:17:40.749695
11254 17:17:40.785679 [[0;32m OK [0m] Finished [0;1;39mUpdate UTMP about System Runlevel Changes[0m.
11255 17:17:40.856996
11256 17:17:40.857547
11257 17:17:40.864829 Debian GNU/Linux 11 debian-bullseye-arm64 ttyS0
11258 17:17:40.865212
11259 17:17:40.865586 debian-bullseye-arm64 login: root (automatic login)
11260 17:17:40.865905
11261 17:17:40.866209
11262 17:17:41.103202 Linux debian-bullseye-arm64 6.1.0-rc6 #1 SMP PREEMPT Tue Nov 22 16:59:36 UTC 2022 aarch64
11263 17:17:41.103350
11264 17:17:41.110066 The programs included with the Debian GNU/Linux system are free software;
11265 17:17:41.116501 the exact distribution terms for each program are described in the
11266 17:17:41.119398 individual files in /usr/share/doc/*/copyright.
11267 17:17:41.119489
11268 17:17:41.126534 Debian GNU/Linux comes with ABSOLUTELY NO WARRANTY, to the extent
11269 17:17:41.129558 permitted by applicable law.
11270 17:17:41.176853 Matched prompt #7: / #
11272 17:17:41.177127 Setting prompt string to ['/ #']
11273 17:17:41.177227 end: 2.2.5.1 login-action (duration 00:00:25) [common]
11275 17:17:41.177475 end: 2.2.5 auto-login-action (duration 00:00:25) [common]
11276 17:17:41.177566 start: 2.2.6 expect-shell-connection (timeout 00:03:42) [common]
11277 17:17:41.177643 Setting prompt string to ['/ #']
11278 17:17:41.177744 Forcing a shell prompt, looking for ['/ #']
11280 17:17:41.228267 / #
11281 17:17:41.228415 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
11282 17:17:41.228502 Waiting using forced prompt support (timeout 00:02:30)
11283 17:17:41.232887
11284 17:17:41.233188 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
11285 17:17:41.233299 start: 2.2.7 export-device-env (timeout 00:03:41) [common]
11287 17:17:41.334178 / # export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep'
11288 17:17:41.339973 export NFS_ROOTFS='/var/lib/lava/dispatcher/tmp/8082983/extract-nfsrootfs-x5se3wep'
11290 17:17:41.440875 / # export NFS_SERVER_IP='192.168.201.1'
11291 17:17:41.445996 export NFS_SERVER_IP='192.168.201.1'
11292 17:17:41.446295 end: 2.2.7 export-device-env (duration 00:00:00) [common]
11293 17:17:41.446399 end: 2.2 depthcharge-retry (duration 00:01:19) [common]
11294 17:17:41.446490 end: 2 depthcharge-action (duration 00:01:19) [common]
11295 17:17:41.446582 start: 3 lava-test-retry (timeout 00:01:00) [common]
11296 17:17:41.446837 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
11297 17:17:41.446914 Using namespace: common
11299 17:17:41.547680 / # #
11300 17:17:41.547872 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11301 17:17:41.552499 #
11302 17:17:41.552812 Using /lava-8082983
11304 17:17:41.653704 / # export SHELL=/bin/sh
11305 17:17:41.659112 export SHELL=/bin/sh
11307 17:17:41.760889 / # . /lava-8082983/environment
11308 17:17:41.766595 . /lava-8082983/environment
11310 17:17:41.873247 / # /lava-8082983/bin/lava-test-runner /lava-8082983/0
11311 17:17:41.873918 Test shell timeout: 10s (minimum of the action and connection timeout)
11312 17:17:41.879336 /lava-8082983/bin/lava-test-runner /lava-8082983/0
11313 17:17:42.084077 + export TESTRUN_ID=0_dmesg
11314 17:17:42.087066 + cd /lava-8082983/0/tests/0_dmesg
11315 17:17:42.087509 + cat uuid
11316 17:17:42.090672
11317 17:17:42.105182 + UUID=8082983_1.6<8>[ 24.975908] <LAVA_SIGNAL_STARTRUN 0_dmesg 8082983_1.6.2.3.1>
11318 17:17:42.105652 .2.3.1
11319 17:17:42.105998 + set +x
11320 17:17:42.106568 Received signal: <STARTRUN> 0_dmesg 8082983_1.6.2.3.1
11321 17:17:42.106926 Starting test lava.0_dmesg (8082983_1.6.2.3.1)
11322 17:17:42.107412 Skipping test definition patterns.
11323 17:17:42.111557 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
11324 17:17:42.190102 <8>[ 25.061325] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
11325 17:17:42.190430 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
11327 17:17:42.251673 <8>[ 25.122876] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
11328 17:17:42.251990 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
11330 17:17:42.314736 <8>[ 25.185728] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
11331 17:17:42.315060 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
11333 17:17:42.321239 + <8>[ 25.195127] <LAVA_SIGNAL_ENDRUN 0_dmesg 8082983_1.6.2.3.1>
11334 17:17:42.321374 set +x
11335 17:17:42.321619 Received signal: <ENDRUN> 0_dmesg 8082983_1.6.2.3.1
11336 17:17:42.321711 Ending use of test pattern.
11337 17:17:42.321777 Ending test lava.0_dmesg (8082983_1.6.2.3.1), duration 0.21
11339 17:17:42.325207 <LAVA_TEST_RUNNER EXIT>
11340 17:17:42.325460 ok: lava_test_shell seems to have completed
11341 17:17:42.325614 alert: pass
crit: pass
emerg: pass
11342 17:17:42.325709 end: 3.1 lava-test-shell (duration 00:00:01) [common]
11343 17:17:42.325796 end: 3 lava-test-retry (duration 00:00:01) [common]
11344 17:17:42.325882 start: 4 lava-test-retry (timeout 00:01:00) [common]
11345 17:17:42.325969 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
11346 17:17:42.326037 Using namespace: common
11348 17:17:42.426799 / # #
11349 17:17:42.426977 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
11350 17:17:42.427131 Using /lava-8082983
11352 17:17:42.527633 export SHELL=/bin/sh
11353 17:17:42.527883 #
11355 17:17:42.628793 / # export SHELL=/bin/sh. /lava-8082983/environment
11356 17:17:42.629093
11358 17:17:42.730247 / # . /lava-8082983/environment/lava-8082983/bin/lava-test-runner /lava-8082983/1
11359 17:17:42.730846 Test shell timeout: 10s (minimum of the action and connection timeout)
11360 17:17:42.731433
11361 17:17:42.736749 / # /lava-8082983/bin/lava-test-runner /lava-8082983/1
11362 17:17:42.831145 + export TESTRUN_ID=1_bootrr
11363 17:17:42.834106 + cd /lava-8082983/1/tests/1_bootrr
11364 17:17:42.837469 + cat uuid
11365 17:17:42.849806 + UUID=8082983_1.6<8>[ 25.720247] <LAVA_SIGNAL_STARTRUN 1_bootrr 8082983_1.6.2.3.5>
11366 17:17:42.850331 .2.3.5
11367 17:17:42.850770 + set +x
11368 17:17:42.851426 Received signal: <STARTRUN> 1_bootrr 8082983_1.6.2.3.5
11369 17:17:42.851852 Starting test lava.1_bootrr (8082983_1.6.2.3.5)
11370 17:17:42.852269 Skipping test definition patterns.
11371 17:17:42.859003 + export PATH=/opt/bootrr/helpers:/lava-8082983/1/../bin:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin
11372 17:17:42.862699 + cd /opt/bootrr
11373 17:17:42.865743 + sh helpers/bootrr-auto
11374 17:17:43.925830 /lava-8082983/1/../bin/lava-test-case
11375 17:17:43.929280
11376 17:17:43.953938 <8>[ 26.825184] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
11377 17:17:43.954232 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
11379 17:17:43.979346 + set +x
11380 17:17:43.982641 <8>[ 26.857130] <LAVA_SIGNAL_ENDRUN 1_bootrr 8082983_1.6.2.3.5>
11381 17:17:43.982908 Received signal: <ENDRUN> 1_bootrr 8082983_1.6.2.3.5
11382 17:17:43.983001 Ending use of test pattern.
11383 17:17:43.983085 Ending test lava.1_bootrr (8082983_1.6.2.3.5), duration 1.13
11385 17:17:43.986037
11386 17:17:43.989148 <LAVA_TEST_RUNNER EXIT>
11387 17:17:43.989400 ok: lava_test_shell seems to have completed
11388 17:17:43.989503 deferred-probe-empty: pass
11389 17:17:43.989598 end: 4.1 lava-test-shell (duration 00:00:02) [common]
11390 17:17:43.989686 end: 4 lava-test-retry (duration 00:00:02) [common]
11391 17:17:43.989776 start: 5 finalize (timeout 00:08:16) [common]
11392 17:17:43.989868 start: 5.1 power-off (timeout 00:00:30) [common]
11393 17:17:43.990013 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-9' '--port=1' '--command=off'
11394 17:17:44.009279 >> Command sent successfully.
11395 17:17:44.011432 Returned 0 in 0 seconds
11396 17:17:44.112239 end: 5.1 power-off (duration 00:00:00) [common]
11398 17:17:44.112585 start: 5.2 read-feedback (timeout 00:08:16) [common]
11399 17:17:44.112826 Listened to connection for namespace 'common' for up to 1s
11400 17:17:45.117612 Finalising connection for namespace 'common'
11401 17:17:45.118314 Disconnecting from shell: Finalise
11402 17:17:45.118751 / #
11403 17:17:45.219795 end: 5.2 read-feedback (duration 00:00:01) [common]
11404 17:17:45.219955 end: 5 finalize (duration 00:00:01) [common]
11405 17:17:45.220079 Cleaning after the job
11406 17:17:45.220197 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/ramdisk
11407 17:17:45.221467 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/kernel
11408 17:17:45.224574 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/dtb
11409 17:17:45.224719 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/nfsrootfs
11410 17:17:45.257046 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082983/tftp-deploy-tjk8rzjj/modules
11411 17:17:45.260013 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8082983
11412 17:17:45.368832 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8082983
11413 17:17:45.369017 Job finished correctly