Boot log: mt8192-asurada-spherion-r0
- Kernel Warnings: 38
- Kernel Errors: 47
- Boot result: PASS
- Errors: 0
- Warnings: 1
1 17:15:51.340523 lava-dispatcher, installed at version: 2022.10
2 17:15:51.340726 start: 0 validate
3 17:15:51.340859 Start time: 2022-11-22 17:15:51.340852+00:00 (UTC)
4 17:15:51.341018 Using caching service: 'http://localhost/cache/?uri=%s'
5 17:15:51.341191 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.kernelci.org%2Fimages%2Frootfs%2Fbuildroot%2Fbuildroot-baseline%2F20221116.0%2Farm64%2Frootfs.cpio.gz exists
6 17:15:51.625768 Using caching service: 'http://localhost/cache/?uri=%s'
7 17:15:51.626004 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.staging.kernelci.org%2Fkernelci%2Fstaging-mainline%2Fstaging-mainline-20221122.0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fkernel%2FImage exists
8 17:15:51.628083 Using caching service: 'http://localhost/cache/?uri=%s'
9 17:15:51.628265 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.staging.kernelci.org%2Fkernelci%2Fstaging-mainline%2Fstaging-mainline-20221122.0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fdtbs%2Fmediatek%2Fmt8192-asurada-spherion-r0.dtb exists
10 17:15:51.920519 Using caching service: 'http://localhost/cache/?uri=%s'
11 17:15:51.920719 Validating that http://localhost/cache/?uri=http%3A%2F%2Fstorage.staging.kernelci.org%2Fkernelci%2Fstaging-mainline%2Fstaging-mainline-20221122.0%2Farm64%2Fdefconfig%2Barm64-chromebook%2Fgcc-10%2Fmodules.tar.xz exists
12 17:15:51.930255 validate duration: 0.59
14 17:15:51.930525 start: 1 tftp-deploy (timeout 00:10:00) [common]
15 17:15:51.930628 start: 1.1 download-retry (timeout 00:10:00) [common]
16 17:15:51.930717 start: 1.1.1 http-download (timeout 00:10:00) [common]
17 17:15:51.930833 Not decompressing ramdisk as can be used compressed.
18 17:15:51.930923 downloading http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/20221116.0/arm64/rootfs.cpio.gz
19 17:15:51.930989 saving as /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/ramdisk/rootfs.cpio.gz
20 17:15:51.931052 total size: 8171865 (7MB)
21 17:15:51.933772 progress 0% (0MB)
22 17:15:51.946449 progress 5% (0MB)
23 17:15:51.956381 progress 10% (0MB)
24 17:15:51.969092 progress 15% (1MB)
25 17:15:51.979812 progress 20% (1MB)
26 17:15:51.992663 progress 25% (1MB)
27 17:15:52.004500 progress 30% (2MB)
28 17:15:52.016362 progress 35% (2MB)
29 17:15:52.027268 progress 40% (3MB)
30 17:15:52.038039 progress 45% (3MB)
31 17:15:52.049000 progress 50% (3MB)
32 17:15:52.058740 progress 55% (4MB)
33 17:15:52.069691 progress 60% (4MB)
34 17:15:52.079825 progress 65% (5MB)
35 17:15:52.089745 progress 70% (5MB)
36 17:15:52.101000 progress 75% (5MB)
37 17:15:52.110813 progress 80% (6MB)
38 17:15:52.120827 progress 85% (6MB)
39 17:15:52.131921 progress 90% (7MB)
40 17:15:52.143117 progress 95% (7MB)
41 17:15:52.152164 progress 100% (7MB)
42 17:15:52.152413 7MB downloaded in 0.22s (35.21MB/s)
43 17:15:52.152577 end: 1.1.1 http-download (duration 00:00:00) [common]
45 17:15:52.152839 end: 1.1 download-retry (duration 00:00:00) [common]
46 17:15:52.152935 start: 1.2 download-retry (timeout 00:10:00) [common]
47 17:15:52.153024 start: 1.2.1 http-download (timeout 00:10:00) [common]
48 17:15:52.153131 downloading http://storage.staging.kernelci.org/kernelci/staging-mainline/staging-mainline-20221122.0/arm64/defconfig+arm64-chromebook/gcc-10/kernel/Image
49 17:15:52.153200 saving as /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/kernel/Image
50 17:15:52.153263 total size: 37693952 (35MB)
51 17:15:52.153325 No compression specified
52 17:15:52.178499 progress 0% (0MB)
53 17:15:52.286055 progress 5% (1MB)
54 17:15:52.414713 progress 10% (3MB)
55 17:15:52.693389 progress 15% (5MB)
56 17:15:52.997694 progress 20% (7MB)
57 17:15:53.285655 progress 25% (9MB)
58 17:15:53.554459 progress 30% (10MB)
59 17:15:53.794483 progress 35% (12MB)
60 17:15:54.027796 progress 40% (14MB)
61 17:15:54.269090 progress 45% (16MB)
62 17:15:54.486393 progress 50% (18MB)
63 17:15:54.617670 progress 55% (19MB)
64 17:15:54.712444 progress 60% (21MB)
65 17:15:54.806610 progress 65% (23MB)
66 17:15:54.907189 progress 70% (25MB)
67 17:15:55.071170 progress 75% (26MB)
68 17:15:55.195850 progress 80% (28MB)
69 17:15:55.291423 progress 85% (30MB)
70 17:15:55.385599 progress 90% (32MB)
71 17:15:55.479444 progress 95% (34MB)
72 17:15:55.577754 progress 100% (35MB)
73 17:15:55.578157 35MB downloaded in 3.42s (10.50MB/s)
74 17:15:55.578427 end: 1.2.1 http-download (duration 00:00:03) [common]
76 17:15:55.578875 end: 1.2 download-retry (duration 00:00:03) [common]
77 17:15:55.579034 start: 1.3 download-retry (timeout 00:09:56) [common]
78 17:15:55.579186 start: 1.3.1 http-download (timeout 00:09:56) [common]
79 17:15:55.579363 downloading http://storage.staging.kernelci.org/kernelci/staging-mainline/staging-mainline-20221122.0/arm64/defconfig+arm64-chromebook/gcc-10/dtbs/mediatek/mt8192-asurada-spherion-r0.dtb
80 17:15:55.579488 saving as /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/dtb/mt8192-asurada-spherion-r0.dtb
81 17:15:55.579602 total size: 46773 (0MB)
82 17:15:55.579712 No compression specified
83 17:15:55.593137 progress 70% (0MB)
84 17:15:55.597149 progress 100% (0MB)
85 17:15:55.597520 0MB downloaded in 0.02s (2.49MB/s)
86 17:15:55.597771 end: 1.3.1 http-download (duration 00:00:00) [common]
88 17:15:55.598206 end: 1.3 download-retry (duration 00:00:00) [common]
89 17:15:55.598360 start: 1.4 download-retry (timeout 00:09:56) [common]
90 17:15:55.598511 start: 1.4.1 http-download (timeout 00:09:56) [common]
91 17:15:55.598684 downloading http://storage.staging.kernelci.org/kernelci/staging-mainline/staging-mainline-20221122.0/arm64/defconfig+arm64-chromebook/gcc-10/modules.tar.xz
92 17:15:55.598804 saving as /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/modules/modules.tar
93 17:15:55.598932 total size: 9185096 (8MB)
94 17:15:55.599046 Using unxz to decompress xz
95 17:15:55.626390 progress 0% (0MB)
96 17:15:55.669036 progress 5% (0MB)
97 17:15:55.706472 progress 10% (0MB)
98 17:15:55.750173 progress 15% (1MB)
99 17:15:55.787582 progress 20% (1MB)
100 17:15:55.830608 progress 25% (2MB)
101 17:15:55.865242 progress 30% (2MB)
102 17:15:55.908304 progress 35% (3MB)
103 17:15:55.952029 progress 40% (3MB)
104 17:15:55.987280 progress 45% (3MB)
105 17:15:56.027449 progress 50% (4MB)
106 17:15:56.070779 progress 55% (4MB)
107 17:15:56.118809 progress 60% (5MB)
108 17:15:56.155373 progress 65% (5MB)
109 17:15:56.206163 progress 70% (6MB)
110 17:15:56.254660 progress 75% (6MB)
111 17:15:56.310681 progress 80% (7MB)
112 17:15:56.362815 progress 85% (7MB)
113 17:15:56.405490 progress 90% (7MB)
114 17:15:56.451167 progress 95% (8MB)
115 17:15:56.494336 progress 100% (8MB)
116 17:15:56.497126 8MB downloaded in 0.90s (9.75MB/s)
117 17:15:56.497403 end: 1.4.1 http-download (duration 00:00:01) [common]
119 17:15:56.497688 end: 1.4 download-retry (duration 00:00:01) [common]
120 17:15:56.497786 start: 1.5 prepare-tftp-overlay (timeout 00:09:55) [common]
121 17:15:56.497885 start: 1.5.1 extract-nfsrootfs (timeout 00:09:55) [common]
122 17:15:56.497970 end: 1.5.1 extract-nfsrootfs (duration 00:00:00) [common]
123 17:15:56.498059 start: 1.5.2 lava-overlay (timeout 00:09:55) [common]
124 17:15:56.498237 [common] Preparing overlay tarball in /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548
125 17:15:56.498345 makedir: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin
126 17:15:56.498428 makedir: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/tests
127 17:15:56.498508 makedir: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/results
128 17:15:56.498616 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-add-keys
129 17:15:56.498752 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-add-sources
130 17:15:56.498869 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-background-process-start
131 17:15:56.498994 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-background-process-stop
132 17:15:56.499105 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-common-functions
133 17:15:56.499222 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-echo-ipv4
134 17:15:56.499335 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-install-packages
135 17:15:56.499444 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-installed-packages
136 17:15:56.499550 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-os-build
137 17:15:56.499659 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-probe-channel
138 17:15:56.499767 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-probe-ip
139 17:15:56.499874 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-target-ip
140 17:15:56.499981 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-target-mac
141 17:15:56.500087 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-target-storage
142 17:15:56.500210 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-case
143 17:15:56.500364 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-event
144 17:15:56.500515 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-feedback
145 17:15:56.500671 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-raise
146 17:15:56.500831 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-reference
147 17:15:56.500981 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-runner
148 17:15:56.501139 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-set
149 17:15:56.501294 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-test-shell
150 17:15:56.501434 Updating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-install-packages (oe)
151 17:15:56.501592 Updating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/bin/lava-installed-packages (oe)
152 17:15:56.501708 Creating /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/environment
153 17:15:56.501796 LAVA metadata
154 17:15:56.501866 - LAVA_JOB_ID=8082969
155 17:15:56.501930 - LAVA_DISPATCHER_IP=192.168.201.1
156 17:15:56.502036 start: 1.5.2.1 lava-vland-overlay (timeout 00:09:55) [common]
157 17:15:56.502101 skipped lava-vland-overlay
158 17:15:56.502190 end: 1.5.2.1 lava-vland-overlay (duration 00:00:00) [common]
159 17:15:56.502281 start: 1.5.2.2 lava-multinode-overlay (timeout 00:09:55) [common]
160 17:15:56.502344 skipped lava-multinode-overlay
161 17:15:56.502420 end: 1.5.2.2 lava-multinode-overlay (duration 00:00:00) [common]
162 17:15:56.502502 start: 1.5.2.3 test-definition (timeout 00:09:55) [common]
163 17:15:56.502579 Loading test definitions
164 17:15:56.502672 start: 1.5.2.3.1 inline-repo-action (timeout 00:09:55) [common]
165 17:15:56.502745 Using /lava-8082969 at stage 0
166 17:15:56.503046 uuid=8082969_1.5.2.3.1 testdef=None
167 17:15:56.503140 end: 1.5.2.3.1 inline-repo-action (duration 00:00:00) [common]
168 17:15:56.503233 start: 1.5.2.3.2 test-overlay (timeout 00:09:55) [common]
169 17:15:56.503749 end: 1.5.2.3.2 test-overlay (duration 00:00:00) [common]
171 17:15:56.503983 start: 1.5.2.3.3 test-install-overlay (timeout 00:09:55) [common]
172 17:15:56.504595 end: 1.5.2.3.3 test-install-overlay (duration 00:00:00) [common]
174 17:15:56.504836 start: 1.5.2.3.4 test-runscript-overlay (timeout 00:09:55) [common]
175 17:15:56.505391 runner path: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/0/tests/0_dmesg test_uuid 8082969_1.5.2.3.1
176 17:15:56.505542 end: 1.5.2.3.4 test-runscript-overlay (duration 00:00:00) [common]
178 17:15:56.505774 start: 1.5.2.3.5 inline-repo-action (timeout 00:09:55) [common]
179 17:15:56.505847 Using /lava-8082969 at stage 1
180 17:15:56.506106 uuid=8082969_1.5.2.3.5 testdef=None
181 17:15:56.506198 end: 1.5.2.3.5 inline-repo-action (duration 00:00:00) [common]
182 17:15:56.506307 start: 1.5.2.3.6 test-overlay (timeout 00:09:55) [common]
183 17:15:56.506792 end: 1.5.2.3.6 test-overlay (duration 00:00:00) [common]
185 17:15:56.507028 start: 1.5.2.3.7 test-install-overlay (timeout 00:09:55) [common]
186 17:15:56.507858 end: 1.5.2.3.7 test-install-overlay (duration 00:00:00) [common]
188 17:15:56.508147 start: 1.5.2.3.8 test-runscript-overlay (timeout 00:09:55) [common]
189 17:15:56.508789 runner path: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/1/tests/1_bootrr test_uuid 8082969_1.5.2.3.5
190 17:15:56.508935 end: 1.5.2.3.8 test-runscript-overlay (duration 00:00:00) [common]
192 17:15:56.509149 Creating lava-test-runner.conf files
193 17:15:56.509220 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/0 for stage 0
194 17:15:56.509303 - 0_dmesg
195 17:15:56.509377 Using lava-test-runner path: /var/lib/lava/dispatcher/tmp/8082969/lava-overlay-k2x41548/lava-8082969/1 for stage 1
196 17:15:56.509457 - 1_bootrr
197 17:15:56.509547 end: 1.5.2.3 test-definition (duration 00:00:00) [common]
198 17:15:56.509637 start: 1.5.2.4 compress-overlay (timeout 00:09:55) [common]
199 17:15:56.516228 end: 1.5.2.4 compress-overlay (duration 00:00:00) [common]
200 17:15:56.516385 start: 1.5.2.5 persistent-nfs-overlay (timeout 00:09:55) [common]
201 17:15:56.516481 end: 1.5.2.5 persistent-nfs-overlay (duration 00:00:00) [common]
202 17:15:56.516571 end: 1.5.2 lava-overlay (duration 00:00:00) [common]
203 17:15:56.516660 start: 1.5.3 extract-overlay-ramdisk (timeout 00:09:55) [common]
204 17:15:56.698989 end: 1.5.3 extract-overlay-ramdisk (duration 00:00:00) [common]
205 17:15:56.699325 start: 1.5.4 extract-modules (timeout 00:09:55) [common]
206 17:15:56.699436 extracting modules file /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/modules/modules.tar to /var/lib/lava/dispatcher/tmp/8082969/extract-overlay-ramdisk-1ea1xrkm/ramdisk
207 17:15:56.827072 end: 1.5.4 extract-modules (duration 00:00:00) [common]
208 17:15:56.827240 start: 1.5.5 apply-overlay-tftp (timeout 00:09:55) [common]
209 17:15:56.827337 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8082969/compress-overlay-ers_yqb0/overlay-1.5.2.4.tar.gz to ramdisk
210 17:15:56.827413 [common] Applying overlay /var/lib/lava/dispatcher/tmp/8082969/compress-overlay-ers_yqb0/overlay-1.5.2.4.tar.gz to directory /var/lib/lava/dispatcher/tmp/8082969/extract-overlay-ramdisk-1ea1xrkm/ramdisk
211 17:15:56.831387 end: 1.5.5 apply-overlay-tftp (duration 00:00:00) [common]
212 17:15:56.831514 start: 1.5.6 configure-preseed-file (timeout 00:09:55) [common]
213 17:15:56.831606 end: 1.5.6 configure-preseed-file (duration 00:00:00) [common]
214 17:15:56.831700 start: 1.5.7 compress-ramdisk (timeout 00:09:55) [common]
215 17:15:56.831778 Building ramdisk /var/lib/lava/dispatcher/tmp/8082969/extract-overlay-ramdisk-1ea1xrkm/ramdisk.cpio containing /var/lib/lava/dispatcher/tmp/8082969/extract-overlay-ramdisk-1ea1xrkm/ramdisk
216 17:15:57.026084 >> 151084 blocks
217 17:15:59.215459 rename /var/lib/lava/dispatcher/tmp/8082969/extract-overlay-ramdisk-1ea1xrkm/ramdisk.cpio.gz to /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/ramdisk/ramdisk.cpio.gz
218 17:15:59.216014 end: 1.5.7 compress-ramdisk (duration 00:00:02) [common]
219 17:15:59.216217 start: 1.5.8 prepare-kernel (timeout 00:09:53) [common]
220 17:15:59.216382 start: 1.5.8.1 prepare-fit (timeout 00:09:53) [common]
221 17:15:59.216554 Calling: 'nice' 'lzma' '--keep' '/var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/kernel/Image'
222 17:16:11.009715 Returned 0 in 11 seconds
223 17:16:11.110649 mkimage -D "-I dts -O dtb -p 2048" -f auto -A arm64 -O linux -T kernel -C lzma -d /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/kernel/Image.lzma -a 0 -b /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/dtb/mt8192-asurada-spherion-r0.dtb -i /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/ramdisk/ramdisk.cpio.gz /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/kernel/image.itb
224 17:16:11.148651 output: FIT description: Kernel Image image with one or more FDT blobs
225 17:16:11.148975 output: Created: Tue Nov 22 17:16:11 2022
226 17:16:11.149052 output: Image 0 (kernel-1)
227 17:16:11.149118 output: Description:
228 17:16:11.149180 output: Created: Tue Nov 22 17:16:11 2022
229 17:16:11.149242 output: Type: Kernel Image
230 17:16:11.149299 output: Compression: lzma compressed
231 17:16:11.149357 output: Data Size: 9039409 Bytes = 8827.55 KiB = 8.62 MiB
232 17:16:11.149412 output: Architecture: AArch64
233 17:16:11.149470 output: OS: Linux
234 17:16:11.149525 output: Load Address: 0x00000000
235 17:16:11.149587 output: Entry Point: 0x00000000
236 17:16:11.149643 output: Image 1 (fdt-1)
237 17:16:11.149699 output: Description: mt8192-asurada-spherion-r0
238 17:16:11.149769 output: Created: Tue Nov 22 17:16:11 2022
239 17:16:11.149825 output: Type: Kernel Image
240 17:16:11.149879 output: Compression: uncompressed
241 17:16:11.149960 output: Data Size: 46773 Bytes = 45.68 KiB = 0.04 MiB
242 17:16:11.150026 output: Architecture: AArch64
243 17:16:11.150081 output: OS: Unknown OS
244 17:16:11.150136 output: Load Address: unavailable
245 17:16:11.150194 output: Entry Point: unavailable
246 17:16:11.150253 output: Image 2 (ramdisk-1)
247 17:16:11.150307 output: Description: unavailable
248 17:16:11.150361 output: Created: Tue Nov 22 17:16:11 2022
249 17:16:11.150415 output: Type: RAMDisk Image
250 17:16:11.150468 output: Compression: Unknown Compression
251 17:16:11.150523 output: Data Size: 22225805 Bytes = 21704.89 KiB = 21.20 MiB
252 17:16:11.150579 output: Architecture: Unknown Architecture
253 17:16:11.150633 output: OS: Linux
254 17:16:11.150686 output: Load Address: unavailable
255 17:16:11.150739 output: Entry Point: unavailable
256 17:16:11.150792 output: Default Configuration: 'conf-1'
257 17:16:11.150846 output: Configuration 0 (conf-1)
258 17:16:11.150909 output: Description: mt8192-asurada-spherion-r0
259 17:16:11.150964 output: Kernel: kernel-1
260 17:16:11.151017 output: Init Ramdisk: ramdisk-1
261 17:16:11.151070 output: FDT: fdt-1
262 17:16:11.151123 output:
263 17:16:11.151312 end: 1.5.8.1 prepare-fit (duration 00:00:12) [common]
264 17:16:11.151411 end: 1.5.8 prepare-kernel (duration 00:00:12) [common]
265 17:16:11.151507 end: 1.5 prepare-tftp-overlay (duration 00:00:15) [common]
266 17:16:11.151601 start: 1.6 lxc-create-udev-rule-action (timeout 00:09:41) [common]
267 17:16:11.151678 No LXC device requested
268 17:16:11.151755 end: 1.6 lxc-create-udev-rule-action (duration 00:00:00) [common]
269 17:16:11.151843 start: 1.7 deploy-device-env (timeout 00:09:41) [common]
270 17:16:11.151929 end: 1.7 deploy-device-env (duration 00:00:00) [common]
271 17:16:11.151997 Checking files for TFTP limit of 4294967296 bytes.
272 17:16:11.152491 end: 1 tftp-deploy (duration 00:00:19) [common]
273 17:16:11.152606 start: 2 depthcharge-action (timeout 00:05:00) [common]
274 17:16:11.152702 start: 2.1 depthcharge-overlay (timeout 00:05:00) [common]
275 17:16:11.152837 substitutions:
276 17:16:11.152906 - {DTB}: 8082969/tftp-deploy-q1z0x9j0/dtb/mt8192-asurada-spherion-r0.dtb
277 17:16:11.152970 - {INITRD}: 8082969/tftp-deploy-q1z0x9j0/ramdisk/ramdisk.cpio.gz
278 17:16:11.153042 - {KERNEL}: 8082969/tftp-deploy-q1z0x9j0/kernel/Image
279 17:16:11.153101 - {LAVA_MAC}: None
280 17:16:11.153158 - {PRESEED_CONFIG}: None
281 17:16:11.153214 - {PRESEED_LOCAL}: None
282 17:16:11.153281 - {RAMDISK}: 8082969/tftp-deploy-q1z0x9j0/ramdisk/ramdisk.cpio.gz
283 17:16:11.153338 - {ROOT_PART}: None
284 17:16:11.153399 - {ROOT}: None
285 17:16:11.153455 - {SERVER_IP}: 192.168.201.1
286 17:16:11.153523 - {TEE}: None
287 17:16:11.153579 Parsed boot commands:
288 17:16:11.153633 - tftpboot 192.168.201.1 {DEPTHCHARGE_KERNEL} {CMDLINE} {DEPTHCHARGE_RAMDISK}
289 17:16:11.153823 Parsed boot commands: tftpboot 192.168.201.1 8082969/tftp-deploy-q1z0x9j0/kernel/image.itb 8082969/tftp-deploy-q1z0x9j0/kernel/cmdline
290 17:16:11.153919 end: 2.1 depthcharge-overlay (duration 00:00:00) [common]
291 17:16:11.154006 start: 2.2 depthcharge-retry (timeout 00:05:00) [common]
292 17:16:11.154123 start: 2.2.1 reset-connection (timeout 00:05:00) [common]
293 17:16:11.154217 start: 2.2.1.1 disconnect-device (timeout 00:05:00) [common]
294 17:16:11.154293 Not connected, no need to disconnect.
295 17:16:11.154372 end: 2.2.1.1 disconnect-device (duration 00:00:00) [common]
296 17:16:11.154459 start: 2.2.1.2 connect-device (timeout 00:05:00) [common]
297 17:16:11.154528 [common] connect-device Connecting to device using '/usr/bin/console -k -f -M localhost mt8192-asurada-spherion-r0-cbg-2'
298 17:16:11.157000 Setting prompt string to ['lava-test: # ']
299 17:16:11.157298 end: 2.2.1.2 connect-device (duration 00:00:00) [common]
300 17:16:11.157404 end: 2.2.1 reset-connection (duration 00:00:00) [common]
301 17:16:11.157503 start: 2.2.2 reset-device (timeout 00:05:00) [common]
302 17:16:11.157609 start: 2.2.2.1 pdu-reboot (timeout 00:05:00) [common]
303 17:16:11.157820 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=reboot'
304 17:16:11.177893 >> Command sent successfully.
305 17:16:11.179975 Returned 0 in 0 seconds
306 17:16:11.280774 end: 2.2.2.1 pdu-reboot (duration 00:00:00) [common]
308 17:16:11.281110 end: 2.2.2 reset-device (duration 00:00:00) [common]
309 17:16:11.281211 start: 2.2.3 depthcharge-start (timeout 00:05:00) [common]
310 17:16:11.281300 Setting prompt string to 'Starting depthcharge on Spherion...'
311 17:16:11.281367 Changing prompt to 'Starting depthcharge on Spherion...'
312 17:16:11.281436 depthcharge-start: Wait for prompt Starting depthcharge on Spherion... (timeout 00:05:00)
313 17:16:11.281705 [Enter `^Ec?' for help]
314 17:16:18.128763
315 17:16:18.128924
316 17:16:18.128994 F0: 102B 0000
317 17:16:18.129063
318 17:16:18.129125 F3: 1001 0000 [0200]
319 17:16:18.129185
320 17:16:18.132168 F3: 1001 0000
321 17:16:18.132266
322 17:16:18.132336 F7: 102D 0000
323 17:16:18.132400
324 17:16:18.132460 F1: 0000 0000
325 17:16:18.136107
326 17:16:18.136193 V0: 0000 0000 [0001]
327 17:16:18.136258
328 17:16:18.136331 00: 0007 8000
329 17:16:18.136431
330 17:16:18.139554 01: 0000 0000
331 17:16:18.139641
332 17:16:18.139708 BP: 0C00 0209 [0000]
333 17:16:18.139769
334 17:16:18.143418 G0: 1182 0000
335 17:16:18.143507
336 17:16:18.143573 EC: 0000 0021 [4000]
337 17:16:18.143636
338 17:16:18.146822 S7: 0000 0000 [0000]
339 17:16:18.146919
340 17:16:18.147017 CC: 0000 0000 [0001]
341 17:16:18.147112
342 17:16:18.150759 T0: 0000 0040 [010F]
343 17:16:18.150862
344 17:16:18.150960 Jump to BL
345 17:16:18.151042
346 17:16:18.151122
347 17:16:18.175626
348 17:16:18.175789
349 17:16:18.182849 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 bootblock starting (log level: 8)...
350 17:16:18.186056 ARM64: Exception handlers installed.
351 17:16:18.189698 ARM64: Testing exception
352 17:16:18.193594 ARM64: Done test exception
353 17:16:18.201282 Backing address range [0x00000000:0x1000000000000) with new page table @0x0010d000
354 17:16:18.211642 Mapping address range [0x00000000:0x200000000) as cacheable | read-write | secure | device
355 17:16:18.218268 Backing address range [0x00000000:0x8000000000) with new page table @0x0010e000
356 17:16:18.227737 Mapping address range [0x00100000:0x00120000) as cacheable | read-write | secure | normal
357 17:16:18.234834 Backing address range [0x00000000:0x40000000) with new page table @0x0010f000
358 17:16:18.241187 Backing address range [0x00000000:0x00200000) with new page table @0x00110000
359 17:16:18.252303 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | normal
360 17:16:18.258796 Backing address range [0x00200000:0x00400000) with new page table @0x00111000
361 17:16:18.278413 Mapping address range [0x00114000:0x00115000) as non-cacheable | read-write | secure | normal
362 17:16:18.281612 WDT: Last reset was cold boot
363 17:16:18.284987 SPI1(PAD0) initialized at 2873684 Hz
364 17:16:18.288119 SPI5(PAD0) initialized at 992727 Hz
365 17:16:18.291209 VBOOT: Loading verstage.
366 17:16:18.298398 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
367 17:16:18.301599 FMAP: Found "FLASH" version 1.1 at 0x20000.
368 17:16:18.304725 FMAP: base = 0x0 size = 0x800000 #areas = 25
369 17:16:18.311342 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
370 17:16:18.317603 CBFS: mcache @0x00107c00 built for 77 files, used 0x1104 of 0x1800 bytes
371 17:16:18.324120 CBFS: Found 'fallback/verstage' @0x75500 size 0xa1eb in mcache @0x00108150
372 17:16:18.333681 read SPI 0x96554 0xa1eb: 4592 us, 9026 KB/s, 72.208 Mbps
373 17:16:18.333820
374 17:16:18.333898
375 17:16:18.343137 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 verstage starting (log level: 8)...
376 17:16:18.346453 ARM64: Exception handlers installed.
377 17:16:18.349683 ARM64: Testing exception
378 17:16:18.349788 ARM64: Done test exception
379 17:16:18.356768 FMAP: area RW_NVRAM found @ 57b000 (8192 bytes)
380 17:16:18.360040 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
381 17:16:18.374375 Probing TPM: . done!
382 17:16:18.374521 TPM ready after 0 ms
383 17:16:18.381433 Connected to device vid:did:rid of 1ae0:0028:00
384 17:16:18.389279 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
385 17:16:18.444103 Initialized TPM device CR50 revision 0
386 17:16:18.456005 tlcl_send_startup: Startup return code is 0
387 17:16:18.456144 TPM: setup succeeded
388 17:16:18.467725 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
389 17:16:18.476440 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
390 17:16:18.482963 VB2:secdata_kernel_check_v1() secdata_kernel: incomplete data (missing 27 bytes)
391 17:16:18.496023 src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
392 17:16:18.499243 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
393 17:16:18.511589 in-header: 03 07 00 00 08 00 00 00
394 17:16:18.515499 in-data: aa e4 47 04 13 02 00 00
395 17:16:18.518803 Chrome EC: UHEPI supported
396 17:16:18.525792 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
397 17:16:18.529698 in-header: 03 95 00 00 08 00 00 00
398 17:16:18.533539 in-data: 18 20 20 08 00 00 00 00
399 17:16:18.533660 Phase 1
400 17:16:18.536762 FMAP: area GBB found @ 3f5000 (12032 bytes)
401 17:16:18.544821 VB2:vb2_check_recovery() Recovery reason from previous boot: 0x1b / 0x7
402 17:16:18.548176 VB2:vb2_check_recovery() We have a recovery request: 0x1b / 0x7
403 17:16:18.551924 Recovery requested (1009000e)
404 17:16:18.562472 TPM: Extending digest for VBOOT: boot mode into PCR 0
405 17:16:18.566510 tlcl_extend: response is 0
406 17:16:18.575684 TPM: Extending digest for VBOOT: GBB HWID into PCR 1
407 17:16:18.582005 tlcl_extend: response is 0
408 17:16:18.589276 CBFS: Found 'fallback/romstage' @0x80 size 0x2173b in mcache @0x00107c2c
409 17:16:18.609005 read SPI 0x210d4 0x2173b: 15137 us, 9051 KB/s, 72.408 Mbps
410 17:16:18.614991 BS: bootblock times (exec / console): total (unknown) / 148 ms
411 17:16:18.615126
412 17:16:18.615200
413 17:16:18.625015 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 romstage starting (log level: 8)...
414 17:16:18.628769 ARM64: Exception handlers installed.
415 17:16:18.632017 ARM64: Testing exception
416 17:16:18.632128 ARM64: Done test exception
417 17:16:18.654129 pmic_efuse_setting: Set efuses in 11 msecs
418 17:16:18.657490 pmwrap_interface_init: Select PMIF_VLD_RDY
419 17:16:18.664079 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c9a
420 17:16:18.667213 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M01: 0x1c070c9a
421 17:16:18.674427 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070c9a
422 17:16:18.678223 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M03: 0x1c070c9a
423 17:16:18.681565 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M04: 0x1c070c9a
424 17:16:18.688842 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M05: 0x1c070c9a
425 17:16:18.692101 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M06: 0x1c070c9a
426 17:16:18.695438 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c9a
427 17:16:18.699339
428 17:16:18.703520 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M08: 0xc9c
429 17:16:18.706074 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M09: 0x1c070c9a
430 17:16:18.709957 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M10: 0x1c070c9a
431 17:16:18.717238 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M11: 0xc9c
432 17:16:18.720436 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M12: 0xc9c
433 17:16:18.727521 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M01 FPM SWITCH: 0x1c070c8a
434 17:16:18.731364 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M02 FPM SWITCH: 0x1c070c8a
435 17:16:18.738439 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M03 FPM SWITCH: 0x1c070c8a
436 17:16:18.742468 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M04 FPM SWITCH: 0x1c070c8a
437 17:16:18.748930 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M05 FPM SWITCH: 0x1c070c8a
438 17:16:18.756191 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M06 FPM SWITCH: 0x1c070c8a
439 17:16:18.760065 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M07 FPM SWITCH: 0x1c070c8a
440 17:16:18.767336 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M08 FPM SWITCH: 0xc8c
441 17:16:18.771176 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M09 FPM SWITCH: 0x1c070c8a
442 17:16:18.777830 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M10 FPM SWITCH: 0x1c070c8a
443 17:16:18.781671 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M11 FPM SWITCH: 0xc8c
444 17:16:18.789031 [SRCLKEN_RC]__rc_ctrl_fpm_switch,186: M12 FPM SWITCH: 0xc8c
445 17:16:18.792535 [SRCLKEN_RC]__rc_ctrl_bblpm_switch,193: M02 BBLPM SWITCH: 0x1c070caa
446 17:16:18.799496 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M00: 0x1c070c92
447 17:16:18.803342 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M02: 0x1c070ca2
448 17:16:18.806602 [SRCLKEN_RC]__rc_ctrl_mode_switch,177: M07: 0x1c070c82
449 17:16:18.813714 [SRCLKEN_RC]rc_dump_reg_info,132: SRCLKEN_RC_CFG:0x10
450 17:16:18.817643 [SRCLKEN_RC]rc_dump_reg_info,133: RC_CENTRAL_CFG1:0x401425
451 17:16:18.824705 [SRCLKEN_RC]rc_dump_reg_info,134: RC_CENTRAL_CFG2:0x1010
452 17:16:18.828508 [SRCLKEN_RC]rc_dump_reg_info,135: RC_CENTRAL_CFG3:0x400f
453 17:16:18.831568 [SRCLKEN_RC]rc_dump_reg_info,136: RC_CENTRAL_CFG4:0x20000
454 17:16:18.839351 [SRCLKEN_RC]rc_dump_reg_info,137: RC_DCXO_FPM_CFG:0x8
455 17:16:18.842700 [SRCLKEN_RC]rc_dump_reg_info,138: SUBSYS_INTF_CFG:0x1041efb
456 17:16:18.850023 [SRCLKEN_RC]rc_dump_reg_info,139: RC_SPI_STA_0:0x40010698
457 17:16:18.853381 [SRCLKEN_RC]rc_dump_reg_info,140: RC_PI_PO_STA:0xd15c3
458 17:16:18.857316 [SRCLKEN_RC]rc_dump_reg_info,144: M00: 0x1c070c92
459 17:16:18.861249 [SRCLKEN_RC]rc_dump_reg_info,144: M01: 0x1c070c8a
460 17:16:18.867900 [SRCLKEN_RC]rc_dump_reg_info,144: M02: 0x1c070ca2
461 17:16:18.871805 [SRCLKEN_RC]rc_dump_reg_info,144: M03: 0x1c070c8a
462 17:16:18.875093 [SRCLKEN_RC]rc_dump_reg_info,144: M04: 0x1c070c8a
463 17:16:18.878961 [SRCLKEN_RC]rc_dump_reg_info,144: M05: 0x1c070c8a
464 17:16:18.882797 [SRCLKEN_RC]rc_dump_reg_info,144: M06: 0x1c070c8a
465 17:16:18.889951 [SRCLKEN_RC]rc_dump_reg_info,144: M07: 0x1c070c82
466 17:16:18.893831 [SRCLKEN_RC]rc_dump_reg_info,144: M08: 0xc8c
467 17:16:18.897032 [SRCLKEN_RC]rc_dump_reg_info,144: M09: 0x1c070c8a
468 17:16:18.901029 [SRCLKEN_RC]rc_dump_reg_info,144: M10: 0x1c070c8a
469 17:16:18.904327 [SRCLKEN_RC]rc_dump_reg_info,144: M11: 0xc8c
470 17:16:18.908410 [SRCLKEN_RC]rc_dump_reg_info,144: M12: 0xc8c
471 17:16:18.918725 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x624d 0x53f0 0x8100 0x4c 0xf0f 0x9248
472 17:16:18.925896 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x1 0x1
473 17:16:18.929815 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
474 17:16:18.936767 [CLKBUF]dump_clkbuf_log,60: DCXO_CW00/09/12/13/15/19=0x4005 0x1f0 0x8100 0x4c 0xf0f 0x9248
475 17:16:18.947628 [CLKBUF]dump_clkbuf_log,71: spi_con1/ldo_rf_op/ldo_bb_op/ldo_rf_en/ldo_bb_en=0x1 0x1 0x1 0x0 0x0
476 17:16:18.951524 [CLKBUF]dump_clkbuf_log,74: clk buf vrfck_hv_en=0x0
477 17:16:18.954821 [RTC]rtc_boot,324: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
478 17:16:18.958636 [RTC]rtc_boot,327: PMIC_RG_SCK_TOP_CON0,0x50c:0x1
479 17:16:18.967420 [RTC]rtc_enable_dcxo,68: con=0x486, osc32con=0xde6b, sec=0x0
480 17:16:18.974167 [RTC]rtc_check_state,173: con=486, pwrkey1=a357, pwrkey2=67d2
481 17:16:18.977936 [RTC]rtc_osc_init,62: osc32con val = 0xde6b
482 17:16:18.981255 [RTC]rtc_eosc_cali,20: PMIC_RG_FQMTR_CKSEL=0x4a
483 17:16:18.991886 [RTC]rtc_get_frequency_meter,154: input=15, output=853
484 17:16:19.000987 [RTC]rtc_get_frequency_meter,154: input=7, output=723
485 17:16:19.010808 [RTC]rtc_get_frequency_meter,154: input=11, output=788
486 17:16:19.020098 [RTC]rtc_get_frequency_meter,154: input=13, output=820
487 17:16:19.029740 [RTC]rtc_get_frequency_meter,154: input=12, output=804
488 17:16:19.038867 [RTC]rtc_get_frequency_meter,154: input=11, output=788
489 17:16:19.048576 [RTC]rtc_get_frequency_meter,154: input=12, output=804
490 17:16:19.051893 [RTC]rtc_eosc_cali,47: left: 11, middle: 11, right: 12
491 17:16:19.059690 [RTC]rtc_osc_init,66: EOSC32 cali val = 0xde6b
492 17:16:19.063184 [RTC]rtc_boot_common,202: RTC_STATE_REBOOT
493 17:16:19.067027 [RTC]rtc_boot_common,220: irqsta=0, bbpu=1, con=486
494 17:16:19.070439 [RTC]rtc_bbpu_power_on,298: rtc_write_trigger=1
495 17:16:19.073631 [RTC]rtc_bbpu_power_on,300: done BBPU=0x1
496 17:16:19.077499 ADC[4]: Raw value=904433 ID=7
497 17:16:19.080702 ADC[3]: Raw value=213546 ID=1
498 17:16:19.080828 RAM Code: 0x71
499 17:16:19.084611 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
500 17:16:19.091981 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
501 17:16:19.099320 CBFS: Found 'sdram-lpddr4x-DISCRETE-2RANK-8GB-BYTE-MODE' @0x75280 size 0x8 in mcache @0x00108014
502 17:16:19.106662 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
503 17:16:19.109908 out: cmd=0xd: 03 f0 0d 00 00 00 00 00
504 17:16:19.113739 in-header: 03 07 00 00 08 00 00 00
505 17:16:19.116979 in-data: aa e4 47 04 13 02 00 00
506 17:16:19.117112 Chrome EC: UHEPI supported
507 17:16:19.124222 out: cmd=0xa4: 03 4c a4 00 00 00 0c 00 00 01 00 00 00 00 00 00 00 00 00 00
508 17:16:19.128696 in-header: 03 95 00 00 08 00 00 00
509 17:16:19.132485 in-data: 18 20 20 08 00 00 00 00
510 17:16:19.136363 MRC: failed to locate region type 0.
511 17:16:19.143465 DRAM-K: Invalid data in flash (size: 0xffffffffffffffff, expected: 0xcf0)
512 17:16:19.147317 DRAM-K: Running full calibration
513 17:16:19.151169 DRAM-K: ddr_type: DSC, config_dvfs: 1, ddr_geometry: 2CH_2RK_8GB_4_4_BYTE
514 17:16:19.154462 header.status = 0x0
515 17:16:19.158484 header.version = 0x6 (expected: 0x6)
516 17:16:19.161767 header.size = 0xd00 (expected: 0xd00)
517 17:16:19.161930 header.flags = 0x0
518 17:16:19.168824 CBFS: Found 'fallback/dram' @0x51540 size 0x1c583 in mcache @0x00107e40
519 17:16:19.185825 read SPI 0x72590 0x1c583: 12499 us, 9288 KB/s, 74.304 Mbps
520 17:16:19.193082 dram_init: MediaTek DRAM firmware version: 1.6.3, accepting param version 6
521 17:16:19.197016 dram_init: ddr_geometry: 2
522 17:16:19.197149 [EMI] MDL number = 2
523 17:16:19.200759 [EMI] Get MDL freq = 0
524 17:16:19.200872 dram_init: ddr_type: 0
525 17:16:19.204764 is_discrete_lpddr4: 1
526 17:16:19.207881 [Set_DRAM_Pinmux_Sel] DRAMPinmux = 0
527 17:16:19.208002
528 17:16:19.208077
529 17:16:19.211815 [Bian_co] ETT version 0.0.0.1
530 17:16:19.214987 dram_type 6, R0 cbt_mode 1, R1 cbt_mode 1 VENDOR=6
531 17:16:19.215098
532 17:16:19.218958 dramc_set_vcore_voltage set vcore to 650000
533 17:16:19.222864 Read voltage for 800, 4
534 17:16:19.223003 Vio18 = 0
535 17:16:19.223077 Vcore = 650000
536 17:16:19.223152 Vdram = 0
537 17:16:19.226222 Vddq = 0
538 17:16:19.226325 Vmddr = 0
539 17:16:19.229972 dram_init: config_dvfs: 1
540 17:16:19.233750 [FAST_K] DramcSave_Time_For_Cal_Init SHU6, femmc_Ready=0
541 17:16:19.237578 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
542 17:16:19.240801 [SwImpedanceCal] DRVP=7, DRVN=16, ODTN=9
543 17:16:19.247949 freq_region=0, Reg: DRVP=7, DRVN=16, ODTN=9
544 17:16:19.251188 [SwImpedanceCal] DRVP=12, DRVN=24, ODTN=9
545 17:16:19.255092 freq_region=1, Reg: DRVP=12, DRVN=24, ODTN=9
546 17:16:19.255226 MEM_TYPE=3, freq_sel=18
547 17:16:19.259131 sv_algorithm_assistance_LP4_1600
548 17:16:19.262451 ============ PULL DRAM RESETB DOWN ============
549 17:16:19.266234 ========== PULL DRAM RESETB DOWN end =========
550 17:16:19.273620 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
551 17:16:19.276906 ===================================
552 17:16:19.277041 LPDDR4 DRAM CONFIGURATION
553 17:16:19.280729 ===================================
554 17:16:19.283983 EX_ROW_EN[0] = 0x0
555 17:16:19.284111 EX_ROW_EN[1] = 0x0
556 17:16:19.287328 LP4Y_EN = 0x0
557 17:16:19.287455 WORK_FSP = 0x0
558 17:16:19.291320 WL = 0x2
559 17:16:19.291435 RL = 0x2
560 17:16:19.294705 BL = 0x2
561 17:16:19.294810 RPST = 0x0
562 17:16:19.298657 RD_PRE = 0x0
563 17:16:19.298777 WR_PRE = 0x1
564 17:16:19.301909 WR_PST = 0x0
565 17:16:19.302017 DBI_WR = 0x0
566 17:16:19.305745 DBI_RD = 0x0
567 17:16:19.305865 OTF = 0x1
568 17:16:19.309637 ===================================
569 17:16:19.312867 ===================================
570 17:16:19.312986 ANA top config
571 17:16:19.316080 ===================================
572 17:16:19.319990 DLL_ASYNC_EN = 0
573 17:16:19.323908 ALL_SLAVE_EN = 1
574 17:16:19.324049 NEW_RANK_MODE = 1
575 17:16:19.327256 DLL_IDLE_MODE = 1
576 17:16:19.330958 LP45_APHY_COMB_EN = 1
577 17:16:19.331085 TX_ODT_DIS = 1
578 17:16:19.334793 NEW_8X_MODE = 1
579 17:16:19.338607 ===================================
580 17:16:19.341884 ===================================
581 17:16:19.345075 data_rate = 1600
582 17:16:19.348919 CKR = 1
583 17:16:19.349046 DQ_P2S_RATIO = 8
584 17:16:19.352752 ===================================
585 17:16:19.356025 CA_P2S_RATIO = 8
586 17:16:19.360093 DQ_CA_OPEN = 0
587 17:16:19.360219 DQ_SEMI_OPEN = 0
588 17:16:19.363393 CA_SEMI_OPEN = 0
589 17:16:19.367311 CA_FULL_RATE = 0
590 17:16:19.371457 DQ_CKDIV4_EN = 1
591 17:16:19.371613 CA_CKDIV4_EN = 1
592 17:16:19.374724 CA_PREDIV_EN = 0
593 17:16:19.378566 PH8_DLY = 0
594 17:16:19.381754 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
595 17:16:19.381880 DQ_AAMCK_DIV = 4
596 17:16:19.385595 CA_AAMCK_DIV = 4
597 17:16:19.389591 CA_ADMCK_DIV = 4
598 17:16:19.392902 DQ_TRACK_CA_EN = 0
599 17:16:19.393022 CA_PICK = 800
600 17:16:19.397037 CA_MCKIO = 800
601 17:16:19.400380 MCKIO_SEMI = 0
602 17:16:19.404425 PLL_FREQ = 3068
603 17:16:19.407623 DQ_UI_PI_RATIO = 32
604 17:16:19.407775 CA_UI_PI_RATIO = 0
605 17:16:19.410744 ===================================
606 17:16:19.414713 ===================================
607 17:16:19.418095 memory_type:LPDDR4
608 17:16:19.421946 GP_NUM : 10
609 17:16:19.422074 SRAM_EN : 1
610 17:16:19.425966 MD32_EN : 0
611 17:16:19.429217 ===================================
612 17:16:19.429336 [ANA_INIT] >>>>>>>>>>>>>>
613 17:16:19.433191 <<<<<< [CONFIGURE PHASE]: ANA_TX
614 17:16:19.436410 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
615 17:16:19.440153 ===================================
616 17:16:19.443450 data_rate = 1600,PCW = 0X7600
617 17:16:19.447436 ===================================
618 17:16:19.447582 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
619 17:16:19.454438 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
620 17:16:19.458296 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
621 17:16:19.465582 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
622 17:16:19.469563 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
623 17:16:19.472957 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
624 17:16:19.473080 [ANA_INIT] flow start
625 17:16:19.476902 [ANA_INIT] PLL >>>>>>>>
626 17:16:19.477032 [ANA_INIT] PLL <<<<<<<<
627 17:16:19.480112 [ANA_INIT] MIDPI >>>>>>>>
628 17:16:19.484156 [ANA_INIT] MIDPI <<<<<<<<
629 17:16:19.484290 [ANA_INIT] DLL >>>>>>>>
630 17:16:19.487410 [ANA_INIT] flow end
631 17:16:19.491296 ============ LP4 DIFF to SE enter ============
632 17:16:19.495420 ============ LP4 DIFF to SE exit ============
633 17:16:19.498619 [ANA_INIT] <<<<<<<<<<<<<
634 17:16:19.501964 [Flow] Enable top DCM control >>>>>
635 17:16:19.505963 [Flow] Enable top DCM control <<<<<
636 17:16:19.506088 Enable DLL master slave shuffle
637 17:16:19.513180 ==============================================================
638 17:16:19.513314 Gating Mode config
639 17:16:19.520222 ==============================================================
640 17:16:19.520373 Config description:
641 17:16:19.531030 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
642 17:16:19.538181 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
643 17:16:19.542106 SELPH_MODE 0: By rank 1: By Phase
644 17:16:19.549247 ==============================================================
645 17:16:19.553160 GAT_TRACK_EN = 1
646 17:16:19.553294 RX_GATING_MODE = 2
647 17:16:19.556932 RX_GATING_TRACK_MODE = 2
648 17:16:19.560231 SELPH_MODE = 1
649 17:16:19.563572 PICG_EARLY_EN = 1
650 17:16:19.567414 VALID_LAT_VALUE = 1
651 17:16:19.571439 ==============================================================
652 17:16:19.574657 Enter into Gating configuration >>>>
653 17:16:19.577945 Exit from Gating configuration <<<<
654 17:16:19.581904 Enter into DVFS_PRE_config >>>>>
655 17:16:19.593060 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
656 17:16:19.597076 Exit from DVFS_PRE_config <<<<<
657 17:16:19.600460 Enter into PICG configuration >>>>
658 17:16:19.600583 Exit from PICG configuration <<<<
659 17:16:19.604227
660 17:16:19.604375 [RX_INPUT] configuration >>>>>
661 17:16:19.607513 [RX_INPUT] configuration <<<<<
662 17:16:19.611450 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
663 17:16:19.618399 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
664 17:16:19.626100 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
665 17:16:19.629315 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
666 17:16:19.637122 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
667 17:16:19.644189 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
668 17:16:19.647994 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
669 17:16:19.651394 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
670 17:16:19.655308 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
671 17:16:19.658528 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
672 17:16:19.662378 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
673 17:16:19.666446 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
674 17:16:19.669746 ===================================
675 17:16:19.673702 LPDDR4 DRAM CONFIGURATION
676 17:16:19.677016 ===================================
677 17:16:19.680227 EX_ROW_EN[0] = 0x0
678 17:16:19.680354 EX_ROW_EN[1] = 0x0
679 17:16:19.684095 LP4Y_EN = 0x0
680 17:16:19.684217 WORK_FSP = 0x0
681 17:16:19.687473 WL = 0x2
682 17:16:19.687590 RL = 0x2
683 17:16:19.690634 BL = 0x2
684 17:16:19.690724 RPST = 0x0
685 17:16:19.693939 RD_PRE = 0x0
686 17:16:19.694034 WR_PRE = 0x1
687 17:16:19.697092 WR_PST = 0x0
688 17:16:19.697186 DBI_WR = 0x0
689 17:16:19.700321 DBI_RD = 0x0
690 17:16:19.700415 OTF = 0x1
691 17:16:19.703615 ===================================
692 17:16:19.706918 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
693 17:16:19.713485 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
694 17:16:19.717137 [ModeRegister RLWL Config] data_rate:1600-MR2_RLWL:2
695 17:16:19.720354 ===================================
696 17:16:19.723445 LPDDR4 DRAM CONFIGURATION
697 17:16:19.726748 ===================================
698 17:16:19.726927 EX_ROW_EN[0] = 0x10
699 17:16:19.729982 EX_ROW_EN[1] = 0x0
700 17:16:19.733271 LP4Y_EN = 0x0
701 17:16:19.733419 WORK_FSP = 0x0
702 17:16:19.736512 WL = 0x2
703 17:16:19.736642 RL = 0x2
704 17:16:19.740373 BL = 0x2
705 17:16:19.740511 RPST = 0x0
706 17:16:19.743503 RD_PRE = 0x0
707 17:16:19.743620 WR_PRE = 0x1
708 17:16:19.746733 WR_PST = 0x0
709 17:16:19.746865 DBI_WR = 0x0
710 17:16:19.750099 DBI_RD = 0x0
711 17:16:19.750231 OTF = 0x1
712 17:16:19.753463 ===================================
713 17:16:19.759903 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
714 17:16:19.764545 nWR fixed to 40
715 17:16:19.767876 [ModeRegInit_LP4] CH0 RK0
716 17:16:19.768014 [ModeRegInit_LP4] CH0 RK1
717 17:16:19.770594 [ModeRegInit_LP4] CH1 RK0
718 17:16:19.774495 [ModeRegInit_LP4] CH1 RK1
719 17:16:19.774633 match AC timing 13
720 17:16:19.781149 dramType 5, freq 800, readDBI 0, DivMode 1, cbtMode 1
721 17:16:19.784388 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
722 17:16:19.787627 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
723 17:16:19.794007 [TX_path_calculate] data rate=1600, WL=8, DQS_TotalUI=17
724 17:16:19.797239 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
725 17:16:19.800379 [EMI DOE] emi_dcm 0
726 17:16:19.803851 [UpdateDFSTbltoDDR3200] Get Highest Freq is 1600
727 17:16:19.803997 ==
728 17:16:19.807035 Dram Type= 6, Freq= 0, CH_0, rank 0
729 17:16:19.810305 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
730 17:16:19.810425 ==
731 17:16:19.816711 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
732 17:16:19.823280 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
733 17:16:19.831422 [CA 0] Center 37 (7~68) winsize 62
734 17:16:19.835456 [CA 1] Center 37 (6~68) winsize 63
735 17:16:19.838035 [CA 2] Center 34 (4~65) winsize 62
736 17:16:19.841952 [CA 3] Center 34 (4~65) winsize 62
737 17:16:19.845009 [CA 4] Center 33 (3~64) winsize 62
738 17:16:19.848239 [CA 5] Center 33 (3~64) winsize 62
739 17:16:19.848347
740 17:16:19.851450 [CmdBusTrainingLP45] Vref(ca) range 1: 34
741 17:16:19.851548
742 17:16:19.854519 [CATrainingPosCal] consider 1 rank data
743 17:16:19.857768 u2DelayCellTimex100 = 270/100 ps
744 17:16:19.861074 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
745 17:16:19.868334 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
746 17:16:19.871670 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
747 17:16:19.874289 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
748 17:16:19.877535 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
749 17:16:19.881450 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
750 17:16:19.881574
751 17:16:19.884109 CA PerBit enable=1, Macro0, CA PI delay=33
752 17:16:19.884215
753 17:16:19.887477 [CBTSetCACLKResult] CA Dly = 33
754 17:16:19.891491 CS Dly: 5 (0~36)
755 17:16:19.891615 ==
756 17:16:19.894094 Dram Type= 6, Freq= 0, CH_0, rank 1
757 17:16:19.897537 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
758 17:16:19.897658 ==
759 17:16:19.904029 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
760 17:16:19.907344 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
761 17:16:19.917770 [CA 0] Center 38 (7~69) winsize 63
762 17:16:19.921556 [CA 1] Center 37 (7~68) winsize 62
763 17:16:19.924603 [CA 2] Center 35 (4~66) winsize 63
764 17:16:19.927943 [CA 3] Center 35 (4~66) winsize 63
765 17:16:19.931120 [CA 4] Center 34 (3~65) winsize 63
766 17:16:19.934248 [CA 5] Center 33 (3~64) winsize 62
767 17:16:19.934379
768 17:16:19.937579 [CmdBusTrainingLP45] Vref(ca) range 1: 34
769 17:16:19.937694
770 17:16:19.940973 [CATrainingPosCal] consider 2 rank data
771 17:16:19.944059 u2DelayCellTimex100 = 270/100 ps
772 17:16:19.947442 CA0 delay=37 (7~68),Diff = 4 PI (28 cell)
773 17:16:19.954500 CA1 delay=37 (7~68),Diff = 4 PI (28 cell)
774 17:16:19.957737 CA2 delay=34 (4~65),Diff = 1 PI (7 cell)
775 17:16:19.960965 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
776 17:16:19.964096 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
777 17:16:19.967489 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
778 17:16:19.967610
779 17:16:19.970635 CA PerBit enable=1, Macro0, CA PI delay=33
780 17:16:19.970741
781 17:16:19.973941 [CBTSetCACLKResult] CA Dly = 33
782 17:16:19.977415 CS Dly: 6 (0~38)
783 17:16:19.977548
784 17:16:19.980684 ----->DramcWriteLeveling(PI) begin...
785 17:16:19.980801 ==
786 17:16:19.984610 Dram Type= 6, Freq= 0, CH_0, rank 0
787 17:16:19.987359 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
788 17:16:19.987475 ==
789 17:16:19.991399 Write leveling (Byte 0): 32 => 32
790 17:16:19.994650 Write leveling (Byte 1): 27 => 27
791 17:16:19.998033 DramcWriteLeveling(PI) end<-----
792 17:16:19.998156
793 17:16:19.998231 ==
794 17:16:20.001302 Dram Type= 6, Freq= 0, CH_0, rank 0
795 17:16:20.004517 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
796 17:16:20.004633 ==
797 17:16:20.007717 [Gating] SW mode calibration
798 17:16:20.014930 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
799 17:16:20.018255 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
800 17:16:20.024587 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
801 17:16:20.027800 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
802 17:16:20.031037 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
803 17:16:20.037995 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
804 17:16:20.041285 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
805 17:16:20.044513 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
806 17:16:20.050911 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
807 17:16:20.054225 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
808 17:16:20.057543 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
809 17:16:20.064003 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
810 17:16:20.067139 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
811 17:16:20.070534 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
812 17:16:20.077101 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
813 17:16:20.080545 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
814 17:16:20.083739 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
815 17:16:20.090363 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
816 17:16:20.094210 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
817 17:16:20.096916 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 1)
818 17:16:20.104131 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 1) (1 0)
819 17:16:20.107566 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
820 17:16:20.110161 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
821 17:16:20.117356 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
822 17:16:20.120495 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
823 17:16:20.123773 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
824 17:16:20.130192 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
825 17:16:20.133549 0 9 4 | B1->B0 | 2323 2323 | 0 1 | (0 0) (1 1)
826 17:16:20.136748 0 9 8 | B1->B0 | 2323 3030 | 0 1 | (0 0) (1 1)
827 17:16:20.143295 0 9 12 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
828 17:16:20.146484 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
829 17:16:20.149828 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
830 17:16:20.157018 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
831 17:16:20.160335 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
832 17:16:20.163574 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
833 17:16:20.169842 0 10 4 | B1->B0 | 3434 3131 | 1 1 | (1 1) (1 0)
834 17:16:20.172996 0 10 8 | B1->B0 | 3131 2323 | 0 0 | (0 1) (0 0)
835 17:16:20.176440 0 10 12 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
836 17:16:20.183101 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
837 17:16:20.186315 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
838 17:16:20.190209 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
839 17:16:20.196836 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
840 17:16:20.199346 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
841 17:16:20.203216 0 11 4 | B1->B0 | 2323 2828 | 0 0 | (0 0) (0 0)
842 17:16:20.209761 0 11 8 | B1->B0 | 2929 3d3d | 1 1 | (0 0) (1 1)
843 17:16:20.213063 0 11 12 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
844 17:16:20.216364 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
845 17:16:20.222649 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
846 17:16:20.225881 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
847 17:16:20.229176 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
848 17:16:20.235546 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
849 17:16:20.239382 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
850 17:16:20.242479 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
851 17:16:20.248917 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
852 17:16:20.252148 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
853 17:16:20.255416 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
854 17:16:20.262227 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
855 17:16:20.265423 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
856 17:16:20.269216 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
857 17:16:20.275621 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
858 17:16:20.278960 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
859 17:16:20.282282 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
860 17:16:20.288663 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
861 17:16:20.292013 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
862 17:16:20.295242 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
863 17:16:20.301778 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
864 17:16:20.305026 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
865 17:16:20.308424 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
866 17:16:20.315025 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
867 17:16:20.315194 Total UI for P1: 0, mck2ui 16
868 17:16:20.321498 best dqsien dly found for B0: ( 0, 14, 6)
869 17:16:20.324934 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
870 17:16:20.328133 Total UI for P1: 0, mck2ui 16
871 17:16:20.331405 best dqsien dly found for B1: ( 0, 14, 8)
872 17:16:20.334580 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
873 17:16:20.338449 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
874 17:16:20.338600
875 17:16:20.341593 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
876 17:16:20.344664 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
877 17:16:20.347900 [Gating] SW calibration Done
878 17:16:20.348043 ==
879 17:16:20.351194 Dram Type= 6, Freq= 0, CH_0, rank 0
880 17:16:20.355073 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
881 17:16:20.355216 ==
882 17:16:20.358481 RX Vref Scan: 0
883 17:16:20.358619
884 17:16:20.358723 RX Vref 0 -> 0, step: 1
885 17:16:20.358819
886 17:16:20.362285
887 17:16:20.362422 RX Delay -130 -> 252, step: 16
888 17:16:20.368754 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
889 17:16:20.371932 iDelay=222, Bit 1, Center 93 (-18 ~ 205) 224
890 17:16:20.375139 iDelay=222, Bit 2, Center 93 (-18 ~ 205) 224
891 17:16:20.378536 iDelay=222, Bit 3, Center 93 (-18 ~ 205) 224
892 17:16:20.381747 iDelay=222, Bit 4, Center 93 (-18 ~ 205) 224
893 17:16:20.388322 iDelay=222, Bit 5, Center 77 (-34 ~ 189) 224
894 17:16:20.391819 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
895 17:16:20.394865 iDelay=222, Bit 7, Center 93 (-18 ~ 205) 224
896 17:16:20.398056 iDelay=222, Bit 8, Center 61 (-66 ~ 189) 256
897 17:16:20.401306 iDelay=222, Bit 9, Center 53 (-66 ~ 173) 240
898 17:16:20.408516 iDelay=222, Bit 10, Center 69 (-50 ~ 189) 240
899 17:16:20.411579 iDelay=222, Bit 11, Center 69 (-50 ~ 189) 240
900 17:16:20.414823 iDelay=222, Bit 12, Center 85 (-34 ~ 205) 240
901 17:16:20.418153 iDelay=222, Bit 13, Center 85 (-34 ~ 205) 240
902 17:16:20.424584 iDelay=222, Bit 14, Center 85 (-34 ~ 205) 240
903 17:16:20.427737 iDelay=222, Bit 15, Center 85 (-34 ~ 205) 240
904 17:16:20.427889 ==
905 17:16:20.431700 Dram Type= 6, Freq= 0, CH_0, rank 0
906 17:16:20.434815 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
907 17:16:20.434979 ==
908 17:16:20.435086 DQS Delay:
909 17:16:20.438073 DQS0 = 0, DQS1 = 0
910 17:16:20.438199 DQM Delay:
911 17:16:20.441300 DQM0 = 92, DQM1 = 74
912 17:16:20.441432 DQ Delay:
913 17:16:20.444510 DQ0 =93, DQ1 =93, DQ2 =93, DQ3 =93
914 17:16:20.447753 DQ4 =93, DQ5 =77, DQ6 =101, DQ7 =93
915 17:16:20.450933 DQ8 =61, DQ9 =53, DQ10 =69, DQ11 =69
916 17:16:20.454721 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
917 17:16:20.454863
918 17:16:20.455006
919 17:16:20.455099 ==
920 17:16:20.457941 Dram Type= 6, Freq= 0, CH_0, rank 0
921 17:16:20.461202 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
922 17:16:20.464392
923 17:16:20.464550 ==
924 17:16:20.464666
925 17:16:20.464761
926 17:16:20.464853 TX Vref Scan disable
927 17:16:20.468094 == TX Byte 0 ==
928 17:16:20.471239 Update DQ dly =583 (2 ,1, 39) DQ OEN =(1 ,6)
929 17:16:20.477560 Update DQM dly =583 (2 ,1, 39) DQM OEN =(1 ,6)
930 17:16:20.477756 == TX Byte 1 ==
931 17:16:20.480930 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
932 17:16:20.487433 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
933 17:16:20.487610 ==
934 17:16:20.490829 Dram Type= 6, Freq= 0, CH_0, rank 0
935 17:16:20.494072 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
936 17:16:20.494217 ==
937 17:16:20.507059 TX Vref=22, minBit 1, minWin=27, winSum=442
938 17:16:20.510292 TX Vref=24, minBit 1, minWin=27, winSum=441
939 17:16:20.514199 TX Vref=26, minBit 2, minWin=27, winSum=446
940 17:16:20.517582 TX Vref=28, minBit 5, minWin=27, winSum=449
941 17:16:20.520734 TX Vref=30, minBit 4, minWin=27, winSum=449
942 17:16:20.524077 TX Vref=32, minBit 1, minWin=27, winSum=449
943 17:16:20.527409
944 17:16:20.530626 [TxChooseVref] Worse bit 5, Min win 27, Win sum 449, Final Vref 28
945 17:16:20.530794
946 17:16:20.533811 Final TX Range 1 Vref 28
947 17:16:20.534002
948 17:16:20.534132 ==
949 17:16:20.536950 Dram Type= 6, Freq= 0, CH_0, rank 0
950 17:16:20.540258 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
951 17:16:20.540413 ==
952 17:16:20.543497
953 17:16:20.543640
954 17:16:20.543805
955 17:16:20.543875 TX Vref Scan disable
956 17:16:20.547313 == TX Byte 0 ==
957 17:16:20.550513 Update DQ dly =582 (2 ,1, 38) DQ OEN =(1 ,6)
958 17:16:20.553739 Update DQM dly =582 (2 ,1, 38) DQM OEN =(1 ,6)
959 17:16:20.557065
960 17:16:20.557189 == TX Byte 1 ==
961 17:16:20.560280 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
962 17:16:20.567062 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
963 17:16:20.567199
964 17:16:20.567313 [DATLAT]
965 17:16:20.567379 Freq=800, CH0 RK0
966 17:16:20.567443
967 17:16:20.570104 DATLAT Default: 0xa
968 17:16:20.573301 0, 0xFFFF, sum = 0
969 17:16:20.573405 1, 0xFFFF, sum = 0
970 17:16:20.576544 2, 0xFFFF, sum = 0
971 17:16:20.576638 3, 0xFFFF, sum = 0
972 17:16:20.579768 4, 0xFFFF, sum = 0
973 17:16:20.579877 5, 0xFFFF, sum = 0
974 17:16:20.583068 6, 0xFFFF, sum = 0
975 17:16:20.583174 7, 0xFFFF, sum = 0
976 17:16:20.586382 8, 0xFFFF, sum = 0
977 17:16:20.586478 9, 0x0, sum = 1
978 17:16:20.590246 10, 0x0, sum = 2
979 17:16:20.590353 11, 0x0, sum = 3
980 17:16:20.593467 12, 0x0, sum = 4
981 17:16:20.593577 best_step = 10
982 17:16:20.593664
983 17:16:20.593744 ==
984 17:16:20.596849 Dram Type= 6, Freq= 0, CH_0, rank 0
985 17:16:20.600087 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
986 17:16:20.600196 ==
987 17:16:20.603355 RX Vref Scan: 1
988 17:16:20.603455
989 17:16:20.606616 Set Vref Range= 32 -> 127
990 17:16:20.606709
991 17:16:20.606776 RX Vref 32 -> 127, step: 1
992 17:16:20.606838
993 17:16:20.610092 RX Delay -111 -> 252, step: 8
994 17:16:20.610199
995 17:16:20.613267 Set Vref, RX VrefLevel [Byte0]: 32
996 17:16:20.616521 [Byte1]: 32
997 17:16:20.620466
998 17:16:20.620589 Set Vref, RX VrefLevel [Byte0]: 33
999 17:16:20.623668 [Byte1]: 33
1000 17:16:20.627571
1001 17:16:20.627681 Set Vref, RX VrefLevel [Byte0]: 34
1002 17:16:20.630792 [Byte1]: 34
1003 17:16:20.635359
1004 17:16:20.635487 Set Vref, RX VrefLevel [Byte0]: 35
1005 17:16:20.638537 [Byte1]: 35
1006 17:16:20.643221
1007 17:16:20.643343 Set Vref, RX VrefLevel [Byte0]: 36
1008 17:16:20.646534 [Byte1]: 36
1009 17:16:20.650833
1010 17:16:20.650975 Set Vref, RX VrefLevel [Byte0]: 37
1011 17:16:20.654954 [Byte1]: 37
1012 17:16:20.659033
1013 17:16:20.659167 Set Vref, RX VrefLevel [Byte0]: 38
1014 17:16:20.662066 [Byte1]: 38
1015 17:16:20.666101
1016 17:16:20.666219 Set Vref, RX VrefLevel [Byte0]: 39
1017 17:16:20.669282
1018 17:16:20.672588 [Byte1]: 39
1019 17:16:20.672732
1020 17:16:20.676292 Set Vref, RX VrefLevel [Byte0]: 40
1021 17:16:20.679497 [Byte1]: 40
1022 17:16:20.679630
1023 17:16:20.683470 Set Vref, RX VrefLevel [Byte0]: 41
1024 17:16:20.686675 [Byte1]: 41
1025 17:16:20.686793
1026 17:16:20.689750 Set Vref, RX VrefLevel [Byte0]: 42
1027 17:16:20.693045 [Byte1]: 42
1028 17:16:20.696460
1029 17:16:20.696577 Set Vref, RX VrefLevel [Byte0]: 43
1030 17:16:20.699739 [Byte1]: 43
1031 17:16:20.704354
1032 17:16:20.704483 Set Vref, RX VrefLevel [Byte0]: 44
1033 17:16:20.707584 [Byte1]: 44
1034 17:16:20.711572
1035 17:16:20.711697 Set Vref, RX VrefLevel [Byte0]: 45
1036 17:16:20.715451 [Byte1]: 45
1037 17:16:20.719282
1038 17:16:20.719403 Set Vref, RX VrefLevel [Byte0]: 46
1039 17:16:20.722568 [Byte1]: 46
1040 17:16:20.727069
1041 17:16:20.727191 Set Vref, RX VrefLevel [Byte0]: 47
1042 17:16:20.730282 [Byte1]: 47
1043 17:16:20.734855
1044 17:16:20.734996 Set Vref, RX VrefLevel [Byte0]: 48
1045 17:16:20.738103 [Byte1]: 48
1046 17:16:20.742631
1047 17:16:20.742762 Set Vref, RX VrefLevel [Byte0]: 49
1048 17:16:20.745966 [Byte1]: 49
1049 17:16:20.750391
1050 17:16:20.750523 Set Vref, RX VrefLevel [Byte0]: 50
1051 17:16:20.753605 [Byte1]: 50
1052 17:16:20.757479
1053 17:16:20.757592 Set Vref, RX VrefLevel [Byte0]: 51
1054 17:16:20.761495 [Byte1]: 51
1055 17:16:20.765339
1056 17:16:20.765452 Set Vref, RX VrefLevel [Byte0]: 52
1057 17:16:20.768643 [Byte1]: 52
1058 17:16:20.773112
1059 17:16:20.773247 Set Vref, RX VrefLevel [Byte0]: 53
1060 17:16:20.776275 [Byte1]: 53
1061 17:16:20.780810
1062 17:16:20.780949 Set Vref, RX VrefLevel [Byte0]: 54
1063 17:16:20.783946 [Byte1]: 54
1064 17:16:20.788656
1065 17:16:20.788785 Set Vref, RX VrefLevel [Byte0]: 55
1066 17:16:20.791664 [Byte1]: 55
1067 17:16:20.796362
1068 17:16:20.796490 Set Vref, RX VrefLevel [Byte0]: 56
1069 17:16:20.798937 [Byte1]: 56
1070 17:16:20.803537
1071 17:16:20.803675 Set Vref, RX VrefLevel [Byte0]: 57
1072 17:16:20.806824 [Byte1]: 57
1073 17:16:20.811499
1074 17:16:20.811623 Set Vref, RX VrefLevel [Byte0]: 58
1075 17:16:20.814748 [Byte1]: 58
1076 17:16:20.818589
1077 17:16:20.818716 Set Vref, RX VrefLevel [Byte0]: 59
1078 17:16:20.822624 [Byte1]: 59
1079 17:16:20.826546
1080 17:16:20.826670 Set Vref, RX VrefLevel [Byte0]: 60
1081 17:16:20.829772 [Byte1]: 60
1082 17:16:20.834346
1083 17:16:20.834502 Set Vref, RX VrefLevel [Byte0]: 61
1084 17:16:20.837605 [Byte1]: 61
1085 17:16:20.841520
1086 17:16:20.841650 Set Vref, RX VrefLevel [Byte0]: 62
1087 17:16:20.845122 [Byte1]: 62
1088 17:16:20.849755
1089 17:16:20.849879 Set Vref, RX VrefLevel [Byte0]: 63
1090 17:16:20.852928 [Byte1]: 63
1091 17:16:20.857455
1092 17:16:20.857582 Set Vref, RX VrefLevel [Byte0]: 64
1093 17:16:20.860528 [Byte1]: 64
1094 17:16:20.865189
1095 17:16:20.865306 Set Vref, RX VrefLevel [Byte0]: 65
1096 17:16:20.868398 [Byte1]: 65
1097 17:16:20.872211
1098 17:16:20.872321 Set Vref, RX VrefLevel [Byte0]: 66
1099 17:16:20.875513 [Byte1]: 66
1100 17:16:20.880081
1101 17:16:20.880210 Set Vref, RX VrefLevel [Byte0]: 67
1102 17:16:20.883164 [Byte1]: 67
1103 17:16:20.887876
1104 17:16:20.888018 Set Vref, RX VrefLevel [Byte0]: 68
1105 17:16:20.890903 [Byte1]: 68
1106 17:16:20.895569
1107 17:16:20.895690 Set Vref, RX VrefLevel [Byte0]: 69
1108 17:16:20.898733 [Byte1]: 69
1109 17:16:20.902713
1110 17:16:20.902830 Set Vref, RX VrefLevel [Byte0]: 70
1111 17:16:20.905983 [Byte1]: 70
1112 17:16:20.910481
1113 17:16:20.910604 Set Vref, RX VrefLevel [Byte0]: 71
1114 17:16:20.913738 [Byte1]: 71
1115 17:16:20.918065
1116 17:16:20.918181 Set Vref, RX VrefLevel [Byte0]: 72
1117 17:16:20.921690 [Byte1]: 72
1118 17:16:20.925688
1119 17:16:20.925805 Set Vref, RX VrefLevel [Byte0]: 73
1120 17:16:20.929017 [Byte1]: 73
1121 17:16:20.933697
1122 17:16:20.933825 Final RX Vref Byte 0 = 56 to rank0
1123 17:16:20.936977 Final RX Vref Byte 1 = 60 to rank0
1124 17:16:20.940245 Final RX Vref Byte 0 = 56 to rank1
1125 17:16:20.943455 Final RX Vref Byte 1 = 60 to rank1==
1126 17:16:20.947227 Dram Type= 6, Freq= 0, CH_0, rank 0
1127 17:16:20.953710 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1128 17:16:20.953861 ==
1129 17:16:20.953962 DQS Delay:
1130 17:16:20.954043 DQS0 = 0, DQS1 = 0
1131 17:16:20.956468
1132 17:16:20.956562 DQM Delay:
1133 17:16:20.956649 DQM0 = 88, DQM1 = 76
1134 17:16:20.960412 DQ Delay:
1135 17:16:20.963101 DQ0 =88, DQ1 =88, DQ2 =84, DQ3 =84
1136 17:16:20.966366 DQ4 =88, DQ5 =80, DQ6 =96, DQ7 =96
1137 17:16:20.970490 DQ8 =64, DQ9 =60, DQ10 =76, DQ11 =72
1138 17:16:20.972954 DQ12 =84, DQ13 =84, DQ14 =84, DQ15 =84
1139 17:16:20.973064
1140 17:16:20.973152
1141 17:16:20.979985 [DQSOSCAuto] RK0, (LSB)MR18= 0x2922, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 399 ps
1142 17:16:20.983134 CH0 RK0: MR19=606, MR18=2922
1143 17:16:20.989455 CH0_RK0: MR19=0x606, MR18=0x2922, DQSOSC=399, MR23=63, INC=92, DEC=61
1144 17:16:20.989596
1145 17:16:20.992868 ----->DramcWriteLeveling(PI) begin...
1146 17:16:20.992993 ==
1147 17:16:20.996241 Dram Type= 6, Freq= 0, CH_0, rank 1
1148 17:16:21.000074 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1149 17:16:21.000205 ==
1150 17:16:21.003193 Write leveling (Byte 0): 29 => 29
1151 17:16:21.006546 Write leveling (Byte 1): 26 => 26
1152 17:16:21.009771 DramcWriteLeveling(PI) end<-----
1153 17:16:21.009892
1154 17:16:21.009975 ==
1155 17:16:21.013105 Dram Type= 6, Freq= 0, CH_0, rank 1
1156 17:16:21.016392 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1157 17:16:21.016502 ==
1158 17:16:21.019667 [Gating] SW mode calibration
1159 17:16:21.026299 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1160 17:16:21.033037 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1161 17:16:21.036545 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1162 17:16:21.042400 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1163 17:16:21.087006 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1164 17:16:21.087404 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1165 17:16:21.087489 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1166 17:16:21.087555 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1167 17:16:21.087615 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1168 17:16:21.087867 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1169 17:16:21.087942 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1170 17:16:21.088033 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1171 17:16:21.088300 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1172 17:16:21.088368 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1173 17:16:21.121783 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1174 17:16:21.121933 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1175 17:16:21.122246
1176 17:16:21.122342 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1177 17:16:21.122409 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1178 17:16:21.122471 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1179 17:16:21.122731 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1180 17:16:21.122799 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1181 17:16:21.122868 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1182 17:16:21.125801 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1183 17:16:21.129073 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1184 17:16:21.132391 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1185 17:16:21.138822 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1186 17:16:21.142197 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1187 17:16:21.145300 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1188 17:16:21.152423 0 9 8 | B1->B0 | 2323 3434 | 1 1 | (1 1) (1 1)
1189 17:16:21.155053 0 9 12 | B1->B0 | 3333 3434 | 0 1 | (0 0) (1 1)
1190 17:16:21.158817 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1191 17:16:21.165319 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1192 17:16:21.168488 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1193 17:16:21.171691 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1194 17:16:21.178643 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1195 17:16:21.182040 0 10 4 | B1->B0 | 3434 3030 | 1 0 | (1 0) (1 0)
1196 17:16:21.185225 0 10 8 | B1->B0 | 2f2f 2626 | 1 0 | (1 0) (0 0)
1197 17:16:21.191622 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1198 17:16:21.194756 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1199 17:16:21.198049 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1200 17:16:21.204578 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1201 17:16:21.207779 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1202 17:16:21.211532 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1203 17:16:21.218071 0 11 4 | B1->B0 | 2323 3030 | 0 0 | (0 0) (1 1)
1204 17:16:21.221255 0 11 8 | B1->B0 | 3131 4343 | 0 0 | (1 1) (0 0)
1205 17:16:21.224435 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1206 17:16:21.231717 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1207 17:16:21.235702 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1208 17:16:21.239421 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1209 17:16:21.242740 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1210 17:16:21.249392 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1211 17:16:21.251939 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1212 17:16:21.255833 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1213 17:16:21.262906 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1214 17:16:21.266223 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1215 17:16:21.269361 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1216 17:16:21.272707 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1217 17:16:21.279496 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1218 17:16:21.282752 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1219 17:16:21.285926 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1220 17:16:21.289106
1221 17:16:21.292347 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1222 17:16:21.295326 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1223 17:16:21.298577 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1224 17:16:21.302419
1225 17:16:21.305757 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1226 17:16:21.308413 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1227 17:16:21.312392 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1228 17:16:21.315759
1229 17:16:21.319150 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1230 17:16:21.322425 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1231 17:16:21.325563 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1232 17:16:21.328805 Total UI for P1: 0, mck2ui 16
1233 17:16:21.331961 best dqsien dly found for B0: ( 0, 14, 6)
1234 17:16:21.338633 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1235 17:16:21.341776 Total UI for P1: 0, mck2ui 16
1236 17:16:21.345016 best dqsien dly found for B1: ( 0, 14, 8)
1237 17:16:21.348310 best DQS0 dly(MCK, UI, PI) = (0, 14, 6)
1238 17:16:21.351634 best DQS1 dly(MCK, UI, PI) = (0, 14, 8)
1239 17:16:21.351751
1240 17:16:21.355499 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 6)
1241 17:16:21.358718 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 8)
1242 17:16:21.361902 [Gating] SW calibration Done
1243 17:16:21.362055 ==
1244 17:16:21.365102 Dram Type= 6, Freq= 0, CH_0, rank 1
1245 17:16:21.368733 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1246 17:16:21.368859 ==
1247 17:16:21.371993 RX Vref Scan: 0
1248 17:16:21.372104
1249 17:16:21.372175 RX Vref 0 -> 0, step: 1
1250 17:16:21.372239
1251 17:16:21.375305
1252 17:16:21.375407 RX Delay -130 -> 252, step: 16
1253 17:16:21.381782 iDelay=206, Bit 0, Center 85 (-34 ~ 205) 240
1254 17:16:21.385042 iDelay=206, Bit 1, Center 85 (-34 ~ 205) 240
1255 17:16:21.388333 iDelay=206, Bit 2, Center 77 (-34 ~ 189) 224
1256 17:16:21.391519 iDelay=206, Bit 3, Center 85 (-34 ~ 205) 240
1257 17:16:21.394747 iDelay=206, Bit 4, Center 93 (-18 ~ 205) 224
1258 17:16:21.401373 iDelay=206, Bit 5, Center 77 (-34 ~ 189) 224
1259 17:16:21.404834 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1260 17:16:21.408208 iDelay=206, Bit 7, Center 93 (-18 ~ 205) 224
1261 17:16:21.411419 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1262 17:16:21.414668 iDelay=206, Bit 9, Center 61 (-50 ~ 173) 224
1263 17:16:21.421236 iDelay=206, Bit 10, Center 85 (-34 ~ 205) 240
1264 17:16:21.424486 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1265 17:16:21.428517 iDelay=206, Bit 12, Center 85 (-34 ~ 205) 240
1266 17:16:21.431745 iDelay=206, Bit 13, Center 85 (-34 ~ 205) 240
1267 17:16:21.434502 iDelay=206, Bit 14, Center 85 (-34 ~ 205) 240
1268 17:16:21.441101 iDelay=206, Bit 15, Center 85 (-34 ~ 205) 240
1269 17:16:21.441242 ==
1270 17:16:21.444999 Dram Type= 6, Freq= 0, CH_0, rank 1
1271 17:16:21.448066 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1272 17:16:21.448197 ==
1273 17:16:21.448272 DQS Delay:
1274 17:16:21.451363 DQS0 = 0, DQS1 = 0
1275 17:16:21.451479 DQM Delay:
1276 17:16:21.454478 DQM0 = 86, DQM1 = 78
1277 17:16:21.454577 DQ Delay:
1278 17:16:21.457708 DQ0 =85, DQ1 =85, DQ2 =77, DQ3 =85
1279 17:16:21.461099 DQ4 =93, DQ5 =77, DQ6 =93, DQ7 =93
1280 17:16:21.465106 DQ8 =69, DQ9 =61, DQ10 =85, DQ11 =69
1281 17:16:21.467539 DQ12 =85, DQ13 =85, DQ14 =85, DQ15 =85
1282 17:16:21.467636
1283 17:16:21.467704
1284 17:16:21.467771 ==
1285 17:16:21.471378 Dram Type= 6, Freq= 0, CH_0, rank 1
1286 17:16:21.474595 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1287 17:16:21.474713 ==
1288 17:16:21.477963
1289 17:16:21.478071
1290 17:16:21.478140
1291 17:16:21.478203 TX Vref Scan disable
1292 17:16:21.481105 == TX Byte 0 ==
1293 17:16:21.484360 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1294 17:16:21.487802 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1295 17:16:21.491063 == TX Byte 1 ==
1296 17:16:21.494155 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1297 17:16:21.497294 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1298 17:16:21.501413 ==
1299 17:16:21.501539 Dram Type= 6, Freq= 0, CH_0, rank 1
1300 17:16:21.507190 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1301 17:16:21.507325 ==
1302 17:16:21.519548 TX Vref=22, minBit 0, minWin=27, winSum=442
1303 17:16:21.523391 TX Vref=24, minBit 0, minWin=27, winSum=443
1304 17:16:21.526700 TX Vref=26, minBit 1, minWin=27, winSum=446
1305 17:16:21.529357 TX Vref=28, minBit 3, minWin=27, winSum=449
1306 17:16:21.533237 TX Vref=30, minBit 6, minWin=27, winSum=452
1307 17:16:21.539916 TX Vref=32, minBit 2, minWin=27, winSum=449
1308 17:16:21.543097 [TxChooseVref] Worse bit 6, Min win 27, Win sum 452, Final Vref 30
1309 17:16:21.543223
1310 17:16:21.546418 Final TX Range 1 Vref 30
1311 17:16:21.546505
1312 17:16:21.546570 ==
1313 17:16:21.549678 Dram Type= 6, Freq= 0, CH_0, rank 1
1314 17:16:21.552839 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1315 17:16:21.552942 ==
1316 17:16:21.556096
1317 17:16:21.556195
1318 17:16:21.556263
1319 17:16:21.556326 TX Vref Scan disable
1320 17:16:21.559935 == TX Byte 0 ==
1321 17:16:21.563255 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1322 17:16:21.569774 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1323 17:16:21.569916 == TX Byte 1 ==
1324 17:16:21.573069 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1325 17:16:21.579471 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1326 17:16:21.579613
1327 17:16:21.579683 [DATLAT]
1328 17:16:21.579745 Freq=800, CH0 RK1
1329 17:16:21.579806
1330 17:16:21.582848 DATLAT Default: 0xa
1331 17:16:21.582970 0, 0xFFFF, sum = 0
1332 17:16:21.586144
1333 17:16:21.586235 1, 0xFFFF, sum = 0
1334 17:16:21.589363 2, 0xFFFF, sum = 0
1335 17:16:21.589459 3, 0xFFFF, sum = 0
1336 17:16:21.592676 4, 0xFFFF, sum = 0
1337 17:16:21.592767 5, 0xFFFF, sum = 0
1338 17:16:21.595856 6, 0xFFFF, sum = 0
1339 17:16:21.595953 7, 0xFFFF, sum = 0
1340 17:16:21.599133 8, 0xFFFF, sum = 0
1341 17:16:21.599228 9, 0x0, sum = 1
1342 17:16:21.602440 10, 0x0, sum = 2
1343 17:16:21.602531 11, 0x0, sum = 3
1344 17:16:21.602602 12, 0x0, sum = 4
1345 17:16:21.605682
1346 17:16:21.605774 best_step = 10
1347 17:16:21.605845
1348 17:16:21.605908 ==
1349 17:16:21.609039 Dram Type= 6, Freq= 0, CH_0, rank 1
1350 17:16:21.612451 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1351 17:16:21.612563 ==
1352 17:16:21.616343 RX Vref Scan: 0
1353 17:16:21.616445
1354 17:16:21.619608 RX Vref 0 -> 0, step: 1
1355 17:16:21.619703
1356 17:16:21.619770 RX Delay -95 -> 252, step: 8
1357 17:16:21.626128 iDelay=209, Bit 0, Center 84 (-23 ~ 192) 216
1358 17:16:21.629995 iDelay=209, Bit 1, Center 92 (-15 ~ 200) 216
1359 17:16:21.633089 iDelay=209, Bit 2, Center 80 (-31 ~ 192) 224
1360 17:16:21.636422 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
1361 17:16:21.643080 iDelay=209, Bit 4, Center 88 (-23 ~ 200) 224
1362 17:16:21.646262 iDelay=209, Bit 5, Center 76 (-39 ~ 192) 232
1363 17:16:21.648972 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
1364 17:16:21.652746 iDelay=209, Bit 7, Center 96 (-15 ~ 208) 224
1365 17:16:21.655907 iDelay=209, Bit 8, Center 64 (-47 ~ 176) 224
1366 17:16:21.662426 iDelay=209, Bit 9, Center 64 (-47 ~ 176) 224
1367 17:16:21.665889 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
1368 17:16:21.668988 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
1369 17:16:21.672211 iDelay=209, Bit 12, Center 84 (-23 ~ 192) 216
1370 17:16:21.675333 iDelay=209, Bit 13, Center 80 (-31 ~ 192) 224
1371 17:16:21.679114
1372 17:16:21.682328 iDelay=209, Bit 14, Center 88 (-23 ~ 200) 224
1373 17:16:21.685559 iDelay=209, Bit 15, Center 84 (-31 ~ 200) 232
1374 17:16:21.685678 ==
1375 17:16:21.688848 Dram Type= 6, Freq= 0, CH_0, rank 1
1376 17:16:21.692068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1377 17:16:21.692179 ==
1378 17:16:21.695278 DQS Delay:
1379 17:16:21.695411 DQS0 = 0, DQS1 = 0
1380 17:16:21.698504 DQM Delay:
1381 17:16:21.698601 DQM0 = 86, DQM1 = 77
1382 17:16:21.698690 DQ Delay:
1383 17:16:21.701695 DQ0 =84, DQ1 =92, DQ2 =80, DQ3 =80
1384 17:16:21.704927 DQ4 =88, DQ5 =76, DQ6 =96, DQ7 =96
1385 17:16:21.708291 DQ8 =64, DQ9 =64, DQ10 =80, DQ11 =72
1386 17:16:21.712188 DQ12 =84, DQ13 =80, DQ14 =88, DQ15 =84
1387 17:16:21.712372
1388 17:16:21.712454
1389 17:16:21.721462 [DQSOSCAuto] RK1, (LSB)MR18= 0x2421, (MSB)MR19= 0x606, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
1390 17:16:21.724726 CH0 RK1: MR19=606, MR18=2421
1391 17:16:21.731305 CH0_RK1: MR19=0x606, MR18=0x2421, DQSOSC=400, MR23=63, INC=92, DEC=61
1392 17:16:21.731453 [RxdqsGatingPostProcess] freq 800
1393 17:16:21.738441 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
1394 17:16:21.741478 Pre-setting of DQS Precalculation
1395 17:16:21.748051 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
1396 17:16:21.748200 ==
1397 17:16:21.751716 Dram Type= 6, Freq= 0, CH_1, rank 0
1398 17:16:21.754380 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1399 17:16:21.754489 ==
1400 17:16:21.761387 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1401 17:16:21.764661 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1402 17:16:21.775115 [CA 0] Center 36 (6~67) winsize 62
1403 17:16:21.778750 [CA 1] Center 37 (6~68) winsize 63
1404 17:16:21.781161 [CA 2] Center 35 (5~65) winsize 61
1405 17:16:21.784442 [CA 3] Center 34 (4~65) winsize 62
1406 17:16:21.787644 [CA 4] Center 34 (4~65) winsize 62
1407 17:16:21.790991 [CA 5] Center 33 (3~64) winsize 62
1408 17:16:21.791116
1409 17:16:21.794913 [CmdBusTrainingLP45] Vref(ca) range 1: 34
1410 17:16:21.795030
1411 17:16:21.798139 [CATrainingPosCal] consider 1 rank data
1412 17:16:21.801354 u2DelayCellTimex100 = 270/100 ps
1413 17:16:21.804516 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1414 17:16:21.810905 CA1 delay=37 (6~68),Diff = 4 PI (28 cell)
1415 17:16:21.814195 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1416 17:16:21.817367 CA3 delay=34 (4~65),Diff = 1 PI (7 cell)
1417 17:16:21.821297 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1418 17:16:21.824596 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1419 17:16:21.824711
1420 17:16:21.827832 CA PerBit enable=1, Macro0, CA PI delay=33
1421 17:16:21.827925
1422 17:16:21.831222 [CBTSetCACLKResult] CA Dly = 33
1423 17:16:21.834418 CS Dly: 4 (0~35)
1424 17:16:21.834523 ==
1425 17:16:21.837598 Dram Type= 6, Freq= 0, CH_1, rank 1
1426 17:16:21.841088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1427 17:16:21.841206 ==
1428 17:16:21.846920 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
1429 17:16:21.850690 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=24, u1VrefScanEnd=34
1430 17:16:21.861213 [CA 0] Center 36 (6~67) winsize 62
1431 17:16:21.864504 [CA 1] Center 36 (6~67) winsize 62
1432 17:16:21.867789 [CA 2] Center 34 (4~65) winsize 62
1433 17:16:21.871126 [CA 3] Center 33 (3~64) winsize 62
1434 17:16:21.874432 [CA 4] Center 34 (4~65) winsize 62
1435 17:16:21.877574 [CA 5] Center 33 (3~64) winsize 62
1436 17:16:21.877704
1437 17:16:21.880682 [CmdBusTrainingLP45] Vref(ca) range 1: 32
1438 17:16:21.880802
1439 17:16:21.884473 [CATrainingPosCal] consider 2 rank data
1440 17:16:21.887667 u2DelayCellTimex100 = 270/100 ps
1441 17:16:21.891047 CA0 delay=36 (6~67),Diff = 3 PI (21 cell)
1442 17:16:21.894287 CA1 delay=36 (6~67),Diff = 3 PI (21 cell)
1443 17:16:21.897929 CA2 delay=35 (5~65),Diff = 2 PI (14 cell)
1444 17:16:21.901292 CA3 delay=34 (4~64),Diff = 1 PI (7 cell)
1445 17:16:21.905218 CA4 delay=34 (4~65),Diff = 1 PI (7 cell)
1446 17:16:21.909118 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
1447 17:16:21.909245
1448 17:16:21.912475
1449 17:16:21.915734 CA PerBit enable=1, Macro0, CA PI delay=33
1450 17:16:21.915849
1451 17:16:21.915920 [CBTSetCACLKResult] CA Dly = 33
1452 17:16:21.919826 CS Dly: 5 (0~37)
1453 17:16:21.919936
1454 17:16:21.923068 ----->DramcWriteLeveling(PI) begin...
1455 17:16:21.923177 ==
1456 17:16:21.926509 Dram Type= 6, Freq= 0, CH_1, rank 0
1457 17:16:21.930374 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1458 17:16:21.930512 ==
1459 17:16:21.933678 Write leveling (Byte 0): 29 => 29
1460 17:16:21.936925 Write leveling (Byte 1): 29 => 29
1461 17:16:21.940193 DramcWriteLeveling(PI) end<-----
1462 17:16:21.940304
1463 17:16:21.940385 ==
1464 17:16:21.943402 Dram Type= 6, Freq= 0, CH_1, rank 0
1465 17:16:21.946665 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1466 17:16:21.946780 ==
1467 17:16:21.950025 [Gating] SW mode calibration
1468 17:16:21.956686 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1469 17:16:21.963011 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1470 17:16:21.966815 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 1)
1471 17:16:21.970144 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1472 17:16:21.976468 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1473 17:16:21.979914 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1474 17:16:21.983049 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1475 17:16:21.989998 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1476 17:16:21.993371 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1477 17:16:21.996686 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1478 17:16:22.003032 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1479 17:16:22.006249 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1480 17:16:22.009397 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1481 17:16:22.016521 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1482 17:16:22.019800 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1483 17:16:22.023079 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1484 17:16:22.029430 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1485 17:16:22.032698 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1486 17:16:22.036267 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1487 17:16:22.042643 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 1) (0 1)
1488 17:16:22.046029 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
1489 17:16:22.049335 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1490 17:16:22.055900 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1491 17:16:22.059024 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1492 17:16:22.062894 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1493 17:16:22.069271 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1494 17:16:22.072622 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1495 17:16:22.075951 0 9 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1496 17:16:22.082360 0 9 8 | B1->B0 | 2c2c 3434 | 1 1 | (1 1) (1 1)
1497 17:16:22.085513 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1498 17:16:22.089091 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1499 17:16:22.095614 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1500 17:16:22.098950 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1501 17:16:22.102071 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1502 17:16:22.108542 0 10 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1503 17:16:22.111791 0 10 4 | B1->B0 | 3434 3333 | 0 0 | (0 0) (0 0)
1504 17:16:22.115107 0 10 8 | B1->B0 | 2c2c 2424 | 0 0 | (1 0) (0 0)
1505 17:16:22.122283 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1506 17:16:22.125557 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1507 17:16:22.128647 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1508 17:16:22.135295 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1509 17:16:22.138361 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1510 17:16:22.141656 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1511 17:16:22.148255 0 11 4 | B1->B0 | 2828 3434 | 0 0 | (0 0) (0 0)
1512 17:16:22.151453 0 11 8 | B1->B0 | 3939 4242 | 1 0 | (0 0) (0 0)
1513 17:16:22.154654 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1514 17:16:22.161386 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1515 17:16:22.164531 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1516 17:16:22.168346 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1517 17:16:22.174824 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1518 17:16:22.178184 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1519 17:16:22.181313 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
1520 17:16:22.188218 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1521 17:16:22.191323 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1522 17:16:22.194506 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1523 17:16:22.200967 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1524 17:16:22.204191 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1525 17:16:22.207914 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1526 17:16:22.214292 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1527 17:16:22.217378 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1528 17:16:22.220664 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1529 17:16:22.227188 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1530 17:16:22.230998 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1531 17:16:22.234185 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1532 17:16:22.240774 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1533 17:16:22.243993 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1534 17:16:22.247209 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1535 17:16:22.253767 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1536 17:16:22.253902 Total UI for P1: 0, mck2ui 16
1537 17:16:22.260387 best dqsien dly found for B0: ( 0, 14, 2)
1538 17:16:22.263710 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1539 17:16:22.267363 Total UI for P1: 0, mck2ui 16
1540 17:16:22.270535 best dqsien dly found for B1: ( 0, 14, 4)
1541 17:16:22.273782 best DQS0 dly(MCK, UI, PI) = (0, 14, 2)
1542 17:16:22.277008 best DQS1 dly(MCK, UI, PI) = (0, 14, 4)
1543 17:16:22.277120
1544 17:16:22.280377 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 2)
1545 17:16:22.283643 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 4)
1546 17:16:22.286874 [Gating] SW calibration Done
1547 17:16:22.286999 ==
1548 17:16:22.290614 Dram Type= 6, Freq= 0, CH_1, rank 0
1549 17:16:22.293751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1550 17:16:22.293872 ==
1551 17:16:22.296756 RX Vref Scan: 0
1552 17:16:22.296861
1553 17:16:22.300039 RX Vref 0 -> 0, step: 1
1554 17:16:22.300147
1555 17:16:22.300217 RX Delay -130 -> 252, step: 16
1556 17:16:22.307053 iDelay=222, Bit 0, Center 93 (-18 ~ 205) 224
1557 17:16:22.310240 iDelay=222, Bit 1, Center 85 (-34 ~ 205) 240
1558 17:16:22.313526 iDelay=222, Bit 2, Center 69 (-50 ~ 189) 240
1559 17:16:22.316725 iDelay=222, Bit 3, Center 85 (-34 ~ 205) 240
1560 17:16:22.319955 iDelay=222, Bit 4, Center 85 (-34 ~ 205) 240
1561 17:16:22.326632 iDelay=222, Bit 5, Center 101 (-18 ~ 221) 240
1562 17:16:22.329891 iDelay=222, Bit 6, Center 101 (-18 ~ 221) 240
1563 17:16:22.333220 iDelay=222, Bit 7, Center 85 (-34 ~ 205) 240
1564 17:16:22.336411 iDelay=222, Bit 8, Center 69 (-50 ~ 189) 240
1565 17:16:22.342868 iDelay=222, Bit 9, Center 69 (-50 ~ 189) 240
1566 17:16:22.346578 iDelay=222, Bit 10, Center 85 (-34 ~ 205) 240
1567 17:16:22.349943 iDelay=222, Bit 11, Center 77 (-34 ~ 189) 224
1568 17:16:22.353212 iDelay=222, Bit 12, Center 93 (-18 ~ 205) 224
1569 17:16:22.356472 iDelay=222, Bit 13, Center 93 (-18 ~ 205) 224
1570 17:16:22.363023 iDelay=222, Bit 14, Center 93 (-18 ~ 205) 224
1571 17:16:22.366277 iDelay=222, Bit 15, Center 93 (-18 ~ 205) 224
1572 17:16:22.366397 ==
1573 17:16:22.369404 Dram Type= 6, Freq= 0, CH_1, rank 0
1574 17:16:22.372481 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1575 17:16:22.372606 ==
1576 17:16:22.376246 DQS Delay:
1577 17:16:22.376352 DQS0 = 0, DQS1 = 0
1578 17:16:22.376422 DQM Delay:
1579 17:16:22.379522 DQM0 = 88, DQM1 = 84
1580 17:16:22.379623 DQ Delay:
1581 17:16:22.382762 DQ0 =93, DQ1 =85, DQ2 =69, DQ3 =85
1582 17:16:22.386061 DQ4 =85, DQ5 =101, DQ6 =101, DQ7 =85
1583 17:16:22.389261 DQ8 =69, DQ9 =69, DQ10 =85, DQ11 =77
1584 17:16:22.392423 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1585 17:16:22.392580
1586 17:16:22.392686
1587 17:16:22.392784 ==
1588 17:16:22.395635
1589 17:16:22.395773 Dram Type= 6, Freq= 0, CH_1, rank 0
1590 17:16:22.402216 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1591 17:16:22.402397 ==
1592 17:16:22.402507
1593 17:16:22.402606
1594 17:16:22.405485 TX Vref Scan disable
1595 17:16:22.405623 == TX Byte 0 ==
1596 17:16:22.409395 Update DQ dly =581 (2 ,1, 37) DQ OEN =(1 ,6)
1597 17:16:22.415796 Update DQM dly =581 (2 ,1, 37) DQM OEN =(1 ,6)
1598 17:16:22.415937 == TX Byte 1 ==
1599 17:16:22.418938 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1600 17:16:22.422229
1601 17:16:22.425547 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1602 17:16:22.425666 ==
1603 17:16:22.428736 Dram Type= 6, Freq= 0, CH_1, rank 0
1604 17:16:22.432010 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1605 17:16:22.432120 ==
1606 17:16:22.445623 TX Vref=22, minBit 5, minWin=26, winSum=439
1607 17:16:22.448797 TX Vref=24, minBit 3, minWin=27, winSum=448
1608 17:16:22.452080 TX Vref=26, minBit 1, minWin=27, winSum=450
1609 17:16:22.455241 TX Vref=28, minBit 1, minWin=27, winSum=453
1610 17:16:22.458521 TX Vref=30, minBit 1, minWin=27, winSum=454
1611 17:16:22.465028 TX Vref=32, minBit 1, minWin=27, winSum=453
1612 17:16:22.468235 [TxChooseVref] Worse bit 1, Min win 27, Win sum 454, Final Vref 30
1613 17:16:22.468342
1614 17:16:22.471523 Final TX Range 1 Vref 30
1615 17:16:22.471615
1616 17:16:22.471683 ==
1617 17:16:22.474717 Dram Type= 6, Freq= 0, CH_1, rank 0
1618 17:16:22.478593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1619 17:16:22.478694 ==
1620 17:16:22.478761
1621 17:16:22.482067
1622 17:16:22.482172
1623 17:16:22.482242 TX Vref Scan disable
1624 17:16:22.485319 == TX Byte 0 ==
1625 17:16:22.488551 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
1626 17:16:22.495017 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
1627 17:16:22.495162 == TX Byte 1 ==
1628 17:16:22.498265 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1629 17:16:22.505316 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1630 17:16:22.505473
1631 17:16:22.505552 [DATLAT]
1632 17:16:22.505615 Freq=800, CH1 RK0
1633 17:16:22.505676
1634 17:16:22.508627 DATLAT Default: 0xa
1635 17:16:22.508717 0, 0xFFFF, sum = 0
1636 17:16:22.511653 1, 0xFFFF, sum = 0
1637 17:16:22.514918 2, 0xFFFF, sum = 0
1638 17:16:22.515041 3, 0xFFFF, sum = 0
1639 17:16:22.518164 4, 0xFFFF, sum = 0
1640 17:16:22.518258 5, 0xFFFF, sum = 0
1641 17:16:22.521928 6, 0xFFFF, sum = 0
1642 17:16:22.522024 7, 0xFFFF, sum = 0
1643 17:16:22.525387 8, 0xFFFF, sum = 0
1644 17:16:22.525481 9, 0x0, sum = 1
1645 17:16:22.527928 10, 0x0, sum = 2
1646 17:16:22.528018 11, 0x0, sum = 3
1647 17:16:22.528087 12, 0x0, sum = 4
1648 17:16:22.531964 best_step = 10
1649 17:16:22.532069
1650 17:16:22.532141 ==
1651 17:16:22.534520 Dram Type= 6, Freq= 0, CH_1, rank 0
1652 17:16:22.537933 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1653 17:16:22.538027 ==
1654 17:16:22.541780 RX Vref Scan: 1
1655 17:16:22.541874
1656 17:16:22.544402 Set Vref Range= 32 -> 127
1657 17:16:22.544484
1658 17:16:22.544549 RX Vref 32 -> 127, step: 1
1659 17:16:22.544610
1660 17:16:22.548268 RX Delay -95 -> 252, step: 8
1661 17:16:22.548363
1662 17:16:22.551367 Set Vref, RX VrefLevel [Byte0]: 32
1663 17:16:22.554727 [Byte1]: 32
1664 17:16:22.557794
1665 17:16:22.557888 Set Vref, RX VrefLevel [Byte0]: 33
1666 17:16:22.561012 [Byte1]: 33
1667 17:16:22.565731
1668 17:16:22.565834 Set Vref, RX VrefLevel [Byte0]: 34
1669 17:16:22.569074 [Byte1]: 34
1670 17:16:22.572852
1671 17:16:22.576091 Set Vref, RX VrefLevel [Byte0]: 35
1672 17:16:22.576185 [Byte1]: 35
1673 17:16:22.579452
1674 17:16:22.579545
1675 17:16:22.582611 Set Vref, RX VrefLevel [Byte0]: 36
1676 17:16:22.586442 [Byte1]: 36
1677 17:16:22.586554
1678 17:16:22.589662 Set Vref, RX VrefLevel [Byte0]: 37
1679 17:16:22.593038 [Byte1]: 37
1680 17:16:22.593134
1681 17:16:22.596068
1682 17:16:22.596152 Set Vref, RX VrefLevel [Byte0]: 38
1683 17:16:22.599344 [Byte1]: 38
1684 17:16:22.603888
1685 17:16:22.603990 Set Vref, RX VrefLevel [Byte0]: 39
1686 17:16:22.607119 [Byte1]: 39
1687 17:16:22.610859
1688 17:16:22.610974 Set Vref, RX VrefLevel [Byte0]: 40
1689 17:16:22.614187 [Byte1]: 40
1690 17:16:22.618623
1691 17:16:22.618731 Set Vref, RX VrefLevel [Byte0]: 41
1692 17:16:22.621720 [Byte1]: 41
1693 17:16:22.626319
1694 17:16:22.626445 Set Vref, RX VrefLevel [Byte0]: 42
1695 17:16:22.629545 [Byte1]: 42
1696 17:16:22.634241
1697 17:16:22.634338 Set Vref, RX VrefLevel [Byte0]: 43
1698 17:16:22.637402 [Byte1]: 43
1699 17:16:22.641426
1700 17:16:22.641525 Set Vref, RX VrefLevel [Byte0]: 44
1701 17:16:22.644610 [Byte1]: 44
1702 17:16:22.649221
1703 17:16:22.649345 Set Vref, RX VrefLevel [Byte0]: 45
1704 17:16:22.652480 [Byte1]: 45
1705 17:16:22.656984
1706 17:16:22.657111 Set Vref, RX VrefLevel [Byte0]: 46
1707 17:16:22.660400 [Byte1]: 46
1708 17:16:22.664130
1709 17:16:22.664240 Set Vref, RX VrefLevel [Byte0]: 47
1710 17:16:22.667410 [Byte1]: 47
1711 17:16:22.672081
1712 17:16:22.672199 Set Vref, RX VrefLevel [Byte0]: 48
1713 17:16:22.675173 [Byte1]: 48
1714 17:16:22.679699
1715 17:16:22.679819 Set Vref, RX VrefLevel [Byte0]: 49
1716 17:16:22.682876 [Byte1]: 49
1717 17:16:22.687599
1718 17:16:22.687722 Set Vref, RX VrefLevel [Byte0]: 50
1719 17:16:22.690631 [Byte1]: 50
1720 17:16:22.694754
1721 17:16:22.694857 Set Vref, RX VrefLevel [Byte0]: 51
1722 17:16:22.698312 [Byte1]: 51
1723 17:16:22.702200
1724 17:16:22.702304 Set Vref, RX VrefLevel [Byte0]: 52
1725 17:16:22.705512 [Byte1]: 52
1726 17:16:22.710079
1727 17:16:22.710194 Set Vref, RX VrefLevel [Byte0]: 53
1728 17:16:22.713412 [Byte1]: 53
1729 17:16:22.717317
1730 17:16:22.717418 Set Vref, RX VrefLevel [Byte0]: 54
1731 17:16:22.720640 [Byte1]: 54
1732 17:16:22.725057
1733 17:16:22.725198 Set Vref, RX VrefLevel [Byte0]: 55
1734 17:16:22.728129 [Byte1]: 55
1735 17:16:22.732736
1736 17:16:22.732841 Set Vref, RX VrefLevel [Byte0]: 56
1737 17:16:22.736005 [Byte1]: 56
1738 17:16:22.740685
1739 17:16:22.740786 Set Vref, RX VrefLevel [Byte0]: 57
1740 17:16:22.743394 [Byte1]: 57
1741 17:16:22.747903
1742 17:16:22.748009 Set Vref, RX VrefLevel [Byte0]: 58
1743 17:16:22.751183 [Byte1]: 58
1744 17:16:22.755282
1745 17:16:22.755382 Set Vref, RX VrefLevel [Byte0]: 59
1746 17:16:22.758966 [Byte1]: 59
1747 17:16:22.762851
1748 17:16:22.762959 Set Vref, RX VrefLevel [Byte0]: 60
1749 17:16:22.766169 [Byte1]: 60
1750 17:16:22.770619
1751 17:16:22.770728 Set Vref, RX VrefLevel [Byte0]: 61
1752 17:16:22.773886 [Byte1]: 61
1753 17:16:22.778349
1754 17:16:22.778469 Set Vref, RX VrefLevel [Byte0]: 62
1755 17:16:22.781419 [Byte1]: 62
1756 17:16:22.785966
1757 17:16:22.786084 Set Vref, RX VrefLevel [Byte0]: 63
1758 17:16:22.789208 [Byte1]: 63
1759 17:16:22.793592
1760 17:16:22.793707 Set Vref, RX VrefLevel [Byte0]: 64
1761 17:16:22.797001 [Byte1]: 64
1762 17:16:22.800844
1763 17:16:22.800956 Set Vref, RX VrefLevel [Byte0]: 65
1764 17:16:22.804585 [Byte1]: 65
1765 17:16:22.808505
1766 17:16:22.808604 Set Vref, RX VrefLevel [Byte0]: 66
1767 17:16:22.812274 [Byte1]: 66
1768 17:16:22.816084
1769 17:16:22.816192 Set Vref, RX VrefLevel [Byte0]: 67
1770 17:16:22.819382 [Byte1]: 67
1771 17:16:22.824011
1772 17:16:22.824113 Set Vref, RX VrefLevel [Byte0]: 68
1773 17:16:22.827048 [Byte1]: 68
1774 17:16:22.831575
1775 17:16:22.831681 Set Vref, RX VrefLevel [Byte0]: 69
1776 17:16:22.834834 [Byte1]: 69
1777 17:16:22.839393
1778 17:16:22.839492 Set Vref, RX VrefLevel [Byte0]: 70
1779 17:16:22.842037 [Byte1]: 70
1780 17:16:22.846773
1781 17:16:22.846874 Set Vref, RX VrefLevel [Byte0]: 71
1782 17:16:22.849982 [Byte1]: 71
1783 17:16:22.853932
1784 17:16:22.854034 Set Vref, RX VrefLevel [Byte0]: 72
1785 17:16:22.857760 [Byte1]: 72
1786 17:16:22.861640
1787 17:16:22.861749 Set Vref, RX VrefLevel [Byte0]: 73
1788 17:16:22.865608 [Byte1]: 73
1789 17:16:22.869559
1790 17:16:22.869672 Set Vref, RX VrefLevel [Byte0]: 74
1791 17:16:22.872722 [Byte1]: 74
1792 17:16:22.877202
1793 17:16:22.877314 Set Vref, RX VrefLevel [Byte0]: 75
1794 17:16:22.880430 [Byte1]: 75
1795 17:16:22.884379
1796 17:16:22.884492 Set Vref, RX VrefLevel [Byte0]: 76
1797 17:16:22.888140 [Byte1]: 76
1798 17:16:22.892057
1799 17:16:22.892170 Final RX Vref Byte 0 = 59 to rank0
1800 17:16:22.895868 Final RX Vref Byte 1 = 53 to rank0
1801 17:16:22.899103 Final RX Vref Byte 0 = 59 to rank1
1802 17:16:22.901779 Final RX Vref Byte 1 = 53 to rank1==
1803 17:16:22.905496 Dram Type= 6, Freq= 0, CH_1, rank 0
1804 17:16:22.911870 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1805 17:16:22.911992 ==
1806 17:16:22.912063 DQS Delay:
1807 17:16:22.915135 DQS0 = 0, DQS1 = 0
1808 17:16:22.915249 DQM Delay:
1809 17:16:22.915323 DQM0 = 86, DQM1 = 80
1810 17:16:22.918273 DQ Delay:
1811 17:16:22.921476 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =84
1812 17:16:22.925393 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
1813 17:16:22.928517 DQ8 =64, DQ9 =72, DQ10 =80, DQ11 =76
1814 17:16:22.931826 DQ12 =88, DQ13 =88, DQ14 =88, DQ15 =88
1815 17:16:22.931929
1816 17:16:22.932000
1817 17:16:22.938408 [DQSOSCAuto] RK0, (LSB)MR18= 0x1c2f, (MSB)MR19= 0x606, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
1818 17:16:22.941719 CH1 RK0: MR19=606, MR18=1C2F
1819 17:16:22.948319 CH1_RK0: MR19=0x606, MR18=0x1C2F, DQSOSC=397, MR23=63, INC=93, DEC=62
1820 17:16:22.948440
1821 17:16:22.951606 ----->DramcWriteLeveling(PI) begin...
1822 17:16:22.951707 ==
1823 17:16:22.954998 Dram Type= 6, Freq= 0, CH_1, rank 1
1824 17:16:22.958102 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1825 17:16:22.958225 ==
1826 17:16:22.961378 Write leveling (Byte 0): 25 => 25
1827 17:16:22.964704 Write leveling (Byte 1): 29 => 29
1828 17:16:22.967801 DramcWriteLeveling(PI) end<-----
1829 17:16:22.967919
1830 17:16:22.968015 ==
1831 17:16:22.971076 Dram Type= 6, Freq= 0, CH_1, rank 1
1832 17:16:22.974478 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1833 17:16:22.977655 ==
1834 17:16:22.977787 [Gating] SW mode calibration
1835 17:16:22.988060 [GatingStartPos] MR0_LatencyMode 0, u1RealRL 14 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
1836 17:16:22.990720 RX_Path_delay_UI(22) -3 - DQSINCTL_UI(16) = u1StartUI(6)
1837 17:16:22.993845 0 6 0 | B1->B0 | 2323 2323 | 0 0 | (1 1) (1 0)
1838 17:16:23.001114 0 6 4 | B1->B0 | 2323 2323 | 0 0 | (1 1) (0 0)
1839 17:16:23.004332 0 6 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1840 17:16:23.007364 0 6 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1841 17:16:23.013758 0 6 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1842 17:16:23.016974 0 6 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1843 17:16:23.020450 0 6 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1844 17:16:23.026761 0 6 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1845 17:16:23.030526 0 7 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1846 17:16:23.033766 0 7 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1847 17:16:23.040333 0 7 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1848 17:16:23.043631 0 7 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1849 17:16:23.046791 0 7 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1850 17:16:23.053437 0 7 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1851 17:16:23.056630 0 7 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1852 17:16:23.059828 0 7 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1853 17:16:23.066988 0 8 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 1)
1854 17:16:23.070120 0 8 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (1 0)
1855 17:16:23.073431 0 8 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1856 17:16:23.080051 0 8 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1857 17:16:23.083377 0 8 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1858 17:16:23.086474 0 8 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1859 17:16:23.093085 0 8 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1860 17:16:23.096206 0 8 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1861 17:16:23.099555 0 9 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1862 17:16:23.106757 0 9 4 | B1->B0 | 2323 2f2f | 0 1 | (0 0) (1 1)
1863 17:16:23.109767 0 9 8 | B1->B0 | 3030 3434 | 0 1 | (0 0) (1 1)
1864 17:16:23.113073 0 9 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1865 17:16:23.119686 0 9 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1866 17:16:23.123121 0 9 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1867 17:16:23.126201 0 9 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1868 17:16:23.133136 0 9 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
1869 17:16:23.136401 0 10 0 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
1870 17:16:23.139706 0 10 4 | B1->B0 | 3333 2c2c | 1 1 | (0 1) (1 1)
1871 17:16:23.146190 0 10 8 | B1->B0 | 2828 2323 | 0 0 | (0 0) (0 0)
1872 17:16:23.149587 0 10 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1873 17:16:23.152909 0 10 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1874 17:16:23.159465 0 10 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1875 17:16:23.162816 0 10 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1876 17:16:23.166110 0 10 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1877 17:16:23.172651 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
1878 17:16:23.175889 0 11 4 | B1->B0 | 2323 3737 | 0 0 | (0 0) (0 0)
1879 17:16:23.179048 0 11 8 | B1->B0 | 3737 4646 | 0 0 | (1 1) (0 0)
1880 17:16:23.185678 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1881 17:16:23.188777 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1882 17:16:23.191981 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1883 17:16:23.198550 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1884 17:16:23.202417 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1885 17:16:23.205621 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1886 17:16:23.211804 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1887 17:16:23.215046 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
1888 17:16:23.218845 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1889 17:16:23.225452 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1890 17:16:23.228556 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1891 17:16:23.231725 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1892 17:16:23.238135 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1893 17:16:23.242122 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1894 17:16:23.245440 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1895 17:16:23.251867 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1896 17:16:23.255061 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1897 17:16:23.258371 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1898 17:16:23.264908 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1899 17:16:23.268228 0 13 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1900 17:16:23.271447 0 13 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
1901 17:16:23.277873 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
1902 17:16:23.281226 0 14 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1903 17:16:23.284569 Total UI for P1: 0, mck2ui 16
1904 17:16:23.287642 best dqsien dly found for B0: ( 0, 14, 0)
1905 17:16:23.290792 0 14 8 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
1906 17:16:23.297823 0 14 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
1907 17:16:23.297968 Total UI for P1: 0, mck2ui 16
1908 17:16:23.304213 best dqsien dly found for B1: ( 0, 14, 6)
1909 17:16:23.308013 best DQS0 dly(MCK, UI, PI) = (0, 14, 0)
1910 17:16:23.311204 best DQS1 dly(MCK, UI, PI) = (0, 14, 6)
1911 17:16:23.311316
1912 17:16:23.314208 best DQS0 P1 dly(MCK, UI, PI) = (1, 2, 0)
1913 17:16:23.317565 best DQS1 P1 dly(MCK, UI, PI) = (1, 2, 6)
1914 17:16:23.320708 [Gating] SW calibration Done
1915 17:16:23.320823 ==
1916 17:16:23.324609 Dram Type= 6, Freq= 0, CH_1, rank 1
1917 17:16:23.327840 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1918 17:16:23.327936 ==
1919 17:16:23.330930 RX Vref Scan: 0
1920 17:16:23.331027
1921 17:16:23.331095 RX Vref 0 -> 0, step: 1
1922 17:16:23.331157
1923 17:16:23.334166 RX Delay -130 -> 252, step: 16
1924 17:16:23.337440 iDelay=206, Bit 0, Center 93 (-18 ~ 205) 224
1925 17:16:23.343927 iDelay=206, Bit 1, Center 77 (-50 ~ 205) 256
1926 17:16:23.347115 iDelay=206, Bit 2, Center 69 (-50 ~ 189) 240
1927 17:16:23.350297 iDelay=206, Bit 3, Center 77 (-34 ~ 189) 224
1928 17:16:23.353640 iDelay=206, Bit 4, Center 85 (-34 ~ 205) 240
1929 17:16:23.356896 iDelay=206, Bit 5, Center 93 (-18 ~ 205) 224
1930 17:16:23.363434 iDelay=206, Bit 6, Center 93 (-18 ~ 205) 224
1931 17:16:23.367249 iDelay=206, Bit 7, Center 77 (-50 ~ 205) 256
1932 17:16:23.370590 iDelay=206, Bit 8, Center 69 (-50 ~ 189) 240
1933 17:16:23.373787 iDelay=206, Bit 9, Center 69 (-50 ~ 189) 240
1934 17:16:23.377014 iDelay=206, Bit 10, Center 93 (-18 ~ 205) 224
1935 17:16:23.383560 iDelay=206, Bit 11, Center 69 (-50 ~ 189) 240
1936 17:16:23.386979 iDelay=206, Bit 12, Center 93 (-18 ~ 205) 224
1937 17:16:23.390321 iDelay=206, Bit 13, Center 93 (-18 ~ 205) 224
1938 17:16:23.393817 iDelay=206, Bit 14, Center 93 (-18 ~ 205) 224
1939 17:16:23.400230 iDelay=206, Bit 15, Center 93 (-18 ~ 205) 224
1940 17:16:23.400364 ==
1941 17:16:23.403628 Dram Type= 6, Freq= 0, CH_1, rank 1
1942 17:16:23.406873 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1943 17:16:23.406998 ==
1944 17:16:23.407070 DQS Delay:
1945 17:16:23.410051 DQS0 = 0, DQS1 = 0
1946 17:16:23.410145 DQM Delay:
1947 17:16:23.413297 DQM0 = 83, DQM1 = 84
1948 17:16:23.413398 DQ Delay:
1949 17:16:23.416472 DQ0 =93, DQ1 =77, DQ2 =69, DQ3 =77
1950 17:16:23.420375 DQ4 =85, DQ5 =93, DQ6 =93, DQ7 =77
1951 17:16:23.423712 DQ8 =69, DQ9 =69, DQ10 =93, DQ11 =69
1952 17:16:23.426369 DQ12 =93, DQ13 =93, DQ14 =93, DQ15 =93
1953 17:16:23.426477
1954 17:16:23.426549
1955 17:16:23.426613 ==
1956 17:16:23.429600 Dram Type= 6, Freq= 0, CH_1, rank 1
1957 17:16:23.433524 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1958 17:16:23.433632 ==
1959 17:16:23.436518
1960 17:16:23.436616
1961 17:16:23.436686
1962 17:16:23.436750 TX Vref Scan disable
1963 17:16:23.439658 == TX Byte 0 ==
1964 17:16:23.442935 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
1965 17:16:23.446294 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
1966 17:16:23.449548 == TX Byte 1 ==
1967 17:16:23.452856 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1968 17:16:23.456146 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1969 17:16:23.456265 ==
1970 17:16:23.459373
1971 17:16:23.459481 Dram Type= 6, Freq= 0, CH_1, rank 1
1972 17:16:23.465914 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1973 17:16:23.466031 ==
1974 17:16:23.478994 TX Vref=22, minBit 1, minWin=27, winSum=447
1975 17:16:23.482440 TX Vref=24, minBit 1, minWin=27, winSum=449
1976 17:16:23.485604 TX Vref=26, minBit 0, minWin=28, winSum=454
1977 17:16:23.488543 TX Vref=28, minBit 6, minWin=27, winSum=455
1978 17:16:23.491746 TX Vref=30, minBit 0, minWin=28, winSum=456
1979 17:16:23.498224 TX Vref=32, minBit 0, minWin=28, winSum=455
1980 17:16:23.502090 [TxChooseVref] Worse bit 0, Min win 28, Win sum 456, Final Vref 30
1981 17:16:23.502220
1982 17:16:23.505194 Final TX Range 1 Vref 30
1983 17:16:23.505295
1984 17:16:23.505367 ==
1985 17:16:23.508524 Dram Type= 6, Freq= 0, CH_1, rank 1
1986 17:16:23.511832 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
1987 17:16:23.515052 ==
1988 17:16:23.515157
1989 17:16:23.515228
1990 17:16:23.515292 TX Vref Scan disable
1991 17:16:23.518776 == TX Byte 0 ==
1992 17:16:23.522128 Update DQ dly =576 (2 ,1, 32) DQ OEN =(1 ,6)
1993 17:16:23.525284 Update DQM dly =576 (2 ,1, 32) DQM OEN =(1 ,6)
1994 17:16:23.528563 == TX Byte 1 ==
1995 17:16:23.532537 Update DQ dly =579 (2 ,1, 35) DQ OEN =(1 ,6)
1996 17:16:23.538977 Update DQM dly =579 (2 ,1, 35) DQM OEN =(1 ,6)
1997 17:16:23.539130
1998 17:16:23.539234 [DATLAT]
1999 17:16:23.539297 Freq=800, CH1 RK1
2000 17:16:23.539357
2001 17:16:23.542095 DATLAT Default: 0xa
2002 17:16:23.542214 0, 0xFFFF, sum = 0
2003 17:16:23.545330 1, 0xFFFF, sum = 0
2004 17:16:23.548518 2, 0xFFFF, sum = 0
2005 17:16:23.548655 3, 0xFFFF, sum = 0
2006 17:16:23.551708 4, 0xFFFF, sum = 0
2007 17:16:23.551832 5, 0xFFFF, sum = 0
2008 17:16:23.555023 6, 0xFFFF, sum = 0
2009 17:16:23.555116 7, 0xFFFF, sum = 0
2010 17:16:23.558443 8, 0xFFFF, sum = 0
2011 17:16:23.558571 9, 0x0, sum = 1
2012 17:16:23.561546 10, 0x0, sum = 2
2013 17:16:23.561643 11, 0x0, sum = 3
2014 17:16:23.564883 12, 0x0, sum = 4
2015 17:16:23.565044 best_step = 10
2016 17:16:23.565112
2017 17:16:23.565177 ==
2018 17:16:23.568227 Dram Type= 6, Freq= 0, CH_1, rank 1
2019 17:16:23.571572 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2020 17:16:23.571690 ==
2021 17:16:23.574663 RX Vref Scan: 0
2022 17:16:23.574760
2023 17:16:23.577817 RX Vref 0 -> 0, step: 1
2024 17:16:23.577914
2025 17:16:23.577984 RX Delay -95 -> 252, step: 8
2026 17:16:23.585586 iDelay=209, Bit 0, Center 92 (-23 ~ 208) 232
2027 17:16:23.588773 iDelay=209, Bit 1, Center 80 (-39 ~ 200) 240
2028 17:16:23.591979 iDelay=209, Bit 2, Center 76 (-39 ~ 192) 232
2029 17:16:23.595297 iDelay=209, Bit 3, Center 80 (-31 ~ 192) 224
2030 17:16:23.598460 iDelay=209, Bit 4, Center 84 (-31 ~ 200) 232
2031 17:16:23.605361 iDelay=209, Bit 5, Center 96 (-15 ~ 208) 224
2032 17:16:23.608812 iDelay=209, Bit 6, Center 96 (-15 ~ 208) 224
2033 17:16:23.612009 iDelay=209, Bit 7, Center 84 (-31 ~ 200) 232
2034 17:16:23.615216 iDelay=209, Bit 8, Center 68 (-39 ~ 176) 216
2035 17:16:23.618342 iDelay=209, Bit 9, Center 72 (-39 ~ 184) 224
2036 17:16:23.621688
2037 17:16:23.624823 iDelay=209, Bit 10, Center 80 (-31 ~ 192) 224
2038 17:16:23.627955 iDelay=209, Bit 11, Center 72 (-39 ~ 184) 224
2039 17:16:23.631829 iDelay=209, Bit 12, Center 88 (-23 ~ 200) 224
2040 17:16:23.634986 iDelay=209, Bit 13, Center 92 (-15 ~ 200) 216
2041 17:16:23.641480 iDelay=209, Bit 14, Center 92 (-15 ~ 200) 216
2042 17:16:23.644669 iDelay=209, Bit 15, Center 88 (-23 ~ 200) 224
2043 17:16:23.644782 ==
2044 17:16:23.648044 Dram Type= 6, Freq= 0, CH_1, rank 1
2045 17:16:23.651465 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2046 17:16:23.651569 ==
2047 17:16:23.654826 DQS Delay:
2048 17:16:23.654944 DQS0 = 0, DQS1 = 0
2049 17:16:23.655011 DQM Delay:
2050 17:16:23.658181 DQM0 = 86, DQM1 = 81
2051 17:16:23.658257 DQ Delay:
2052 17:16:23.661417 DQ0 =92, DQ1 =80, DQ2 =76, DQ3 =80
2053 17:16:23.664599 DQ4 =84, DQ5 =96, DQ6 =96, DQ7 =84
2054 17:16:23.667962 DQ8 =68, DQ9 =72, DQ10 =80, DQ11 =72
2055 17:16:23.671304 DQ12 =88, DQ13 =92, DQ14 =92, DQ15 =88
2056 17:16:23.671443
2057 17:16:23.671539
2058 17:16:23.680965 [DQSOSCAuto] RK1, (LSB)MR18= 0x213c, (MSB)MR19= 0x606, tDQSOscB0 = 394 ps tDQSOscB1 = 401 ps
2059 17:16:23.684217 CH1 RK1: MR19=606, MR18=213C
2060 17:16:23.687534 CH1_RK1: MR19=0x606, MR18=0x213C, DQSOSC=394, MR23=63, INC=95, DEC=63
2061 17:16:23.690778 [RxdqsGatingPostProcess] freq 800
2062 17:16:23.697361 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
2063 17:16:23.700595 Pre-setting of DQS Precalculation
2064 17:16:23.703940 [DualRankRxdatlatCal] RK0: 10, RK1: 10, Final_Datlat 10
2065 17:16:23.713826 sync_frequency_calibration_params sync calibration params of frequency 800 to shu:4
2066 17:16:23.720828 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
2067 17:16:23.720964
2068 17:16:23.721035
2069 17:16:23.723845 [Calibration Summary] 1600 Mbps
2070 17:16:23.723941 CH 0, Rank 0
2071 17:16:23.727164 SW Impedance : PASS
2072 17:16:23.727269 DUTY Scan : NO K
2073 17:16:23.730463 ZQ Calibration : PASS
2074 17:16:23.733686 Jitter Meter : NO K
2075 17:16:23.733807 CBT Training : PASS
2076 17:16:23.736745 Write leveling : PASS
2077 17:16:23.740440 RX DQS gating : PASS
2078 17:16:23.740548 RX DQ/DQS(RDDQC) : PASS
2079 17:16:23.743508 TX DQ/DQS : PASS
2080 17:16:23.746773 RX DATLAT : PASS
2081 17:16:23.746885 RX DQ/DQS(Engine): PASS
2082 17:16:23.750019 TX OE : NO K
2083 17:16:23.750119 All Pass.
2084 17:16:23.750188
2085 17:16:23.753299 CH 0, Rank 1
2086 17:16:23.753423 SW Impedance : PASS
2087 17:16:23.756516 DUTY Scan : NO K
2088 17:16:23.759724 ZQ Calibration : PASS
2089 17:16:23.759847 Jitter Meter : NO K
2090 17:16:23.762926 CBT Training : PASS
2091 17:16:23.766747 Write leveling : PASS
2092 17:16:23.766851 RX DQS gating : PASS
2093 17:16:23.770044 RX DQ/DQS(RDDQC) : PASS
2094 17:16:23.773394 TX DQ/DQS : PASS
2095 17:16:23.773510 RX DATLAT : PASS
2096 17:16:23.776621 RX DQ/DQS(Engine): PASS
2097 17:16:23.779766 TX OE : NO K
2098 17:16:23.779885 All Pass.
2099 17:16:23.779959
2100 17:16:23.780049 CH 1, Rank 0
2101 17:16:23.782947 SW Impedance : PASS
2102 17:16:23.786199 DUTY Scan : NO K
2103 17:16:23.786323 ZQ Calibration : PASS
2104 17:16:23.789526 Jitter Meter : NO K
2105 17:16:23.792741 CBT Training : PASS
2106 17:16:23.792865 Write leveling : PASS
2107 17:16:23.795998 RX DQS gating : PASS
2108 17:16:23.799848 RX DQ/DQS(RDDQC) : PASS
2109 17:16:23.799980 TX DQ/DQS : PASS
2110 17:16:23.803029 RX DATLAT : PASS
2111 17:16:23.803134 RX DQ/DQS(Engine): PASS
2112 17:16:23.806188 TX OE : NO K
2113 17:16:23.806278 All Pass.
2114 17:16:23.806355
2115 17:16:23.809544 CH 1, Rank 1
2116 17:16:23.809646 SW Impedance : PASS
2117 17:16:23.812866
2118 17:16:23.812980 DUTY Scan : NO K
2119 17:16:23.816117 ZQ Calibration : PASS
2120 17:16:23.816221 Jitter Meter : NO K
2121 17:16:23.819232 CBT Training : PASS
2122 17:16:23.822479 Write leveling : PASS
2123 17:16:23.822602 RX DQS gating : PASS
2124 17:16:23.825649 RX DQ/DQS(RDDQC) : PASS
2125 17:16:23.829392 TX DQ/DQS : PASS
2126 17:16:23.829531 RX DATLAT : PASS
2127 17:16:23.832688 RX DQ/DQS(Engine): PASS
2128 17:16:23.835814 TX OE : NO K
2129 17:16:23.835928 All Pass.
2130 17:16:23.836027
2131 17:16:23.839004 DramC Write-DBI off
2132 17:16:23.839156 PER_BANK_REFRESH: Hybrid Mode
2133 17:16:23.842208 TX_TRACKING: ON
2134 17:16:23.845405 [GetDramInforAfterCalByMRR] Vendor 6.
2135 17:16:23.849200 [GetDramInforAfterCalByMRR] Revision 606.
2136 17:16:23.852446 [GetDramInforAfterCalByMRR] Revision 2 0.
2137 17:16:23.852605 MR0 0x3b3b
2138 17:16:23.855538 MR8 0x5151
2139 17:16:23.858761 RK0, DieNum 2, Density 16Gb, RKsize 32Gb.
2140 17:16:23.858930
2141 17:16:23.859034 MR0 0x3b3b
2142 17:16:23.862102 MR8 0x5151
2143 17:16:23.865393 RK1, DieNum 2, Density 16Gb, RKsize 32Gb.
2144 17:16:23.865509
2145 17:16:23.871937 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
2146 17:16:23.875190 [FAST_K] Save calibration result to emmc
2147 17:16:23.882354 [FAST_K] Save calibration result to emmc
2148 17:16:23.882521 dram_init: config_dvfs: 1
2149 17:16:23.885492 dramc_set_vcore_voltage set vcore to 662500
2150 17:16:23.888884 Read voltage for 1200, 2
2151 17:16:23.889025 Vio18 = 0
2152 17:16:23.892099 Vcore = 662500
2153 17:16:23.892203 Vdram = 0
2154 17:16:23.892276 Vddq = 0
2155 17:16:23.895293 Vmddr = 0
2156 17:16:23.898547 [FAST_K] DramcSave_Time_For_Cal_Init SHU5, femmc_Ready=0
2157 17:16:23.904959 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
2158 17:16:23.905146 MEM_TYPE=3, freq_sel=15
2159 17:16:23.908234 sv_algorithm_assistance_LP4_1600
2160 17:16:23.914766 ============ PULL DRAM RESETB DOWN ============
2161 17:16:23.918115 ========== PULL DRAM RESETB DOWN end =========
2162 17:16:23.921643 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2163 17:16:23.924920 ===================================
2164 17:16:23.928293 LPDDR4 DRAM CONFIGURATION
2165 17:16:23.931527 ===================================
2166 17:16:23.934615 EX_ROW_EN[0] = 0x0
2167 17:16:23.934719 EX_ROW_EN[1] = 0x0
2168 17:16:23.937764 LP4Y_EN = 0x0
2169 17:16:23.937855 WORK_FSP = 0x0
2170 17:16:23.941598 WL = 0x4
2171 17:16:23.941700 RL = 0x4
2172 17:16:23.944808 BL = 0x2
2173 17:16:23.944909 RPST = 0x0
2174 17:16:23.948078 RD_PRE = 0x0
2175 17:16:23.948179 WR_PRE = 0x1
2176 17:16:23.951402 WR_PST = 0x0
2177 17:16:23.951516 DBI_WR = 0x0
2178 17:16:23.954541 DBI_RD = 0x0
2179 17:16:23.954642 OTF = 0x1
2180 17:16:23.957689 ===================================
2181 17:16:23.961061 ===================================
2182 17:16:23.964455 ANA top config
2183 17:16:23.967655 ===================================
2184 17:16:23.970989 DLL_ASYNC_EN = 0
2185 17:16:23.971111 ALL_SLAVE_EN = 0
2186 17:16:23.974182 NEW_RANK_MODE = 1
2187 17:16:23.977448 DLL_IDLE_MODE = 1
2188 17:16:23.981279 LP45_APHY_COMB_EN = 1
2189 17:16:23.984578 TX_ODT_DIS = 1
2190 17:16:23.984720 NEW_8X_MODE = 1
2191 17:16:23.987828 ===================================
2192 17:16:23.990910 ===================================
2193 17:16:23.994221 data_rate = 2400
2194 17:16:23.997540 CKR = 1
2195 17:16:24.000846 DQ_P2S_RATIO = 8
2196 17:16:24.004043 ===================================
2197 17:16:24.007694 CA_P2S_RATIO = 8
2198 17:16:24.011047 DQ_CA_OPEN = 0
2199 17:16:24.011167 DQ_SEMI_OPEN = 0
2200 17:16:24.014161 CA_SEMI_OPEN = 0
2201 17:16:24.017425 CA_FULL_RATE = 0
2202 17:16:24.020678 DQ_CKDIV4_EN = 0
2203 17:16:24.023932 CA_CKDIV4_EN = 0
2204 17:16:24.026954 CA_PREDIV_EN = 0
2205 17:16:24.027081 PH8_DLY = 17
2206 17:16:24.030233
2207 17:16:24.030355 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
2208 17:16:24.033428 DQ_AAMCK_DIV = 4
2209 17:16:24.036823 CA_AAMCK_DIV = 4
2210 17:16:24.039990 CA_ADMCK_DIV = 4
2211 17:16:24.043299 DQ_TRACK_CA_EN = 0
2212 17:16:24.047135 CA_PICK = 1200
2213 17:16:24.050341 CA_MCKIO = 1200
2214 17:16:24.050534 MCKIO_SEMI = 0
2215 17:16:24.053668 PLL_FREQ = 2366
2216 17:16:24.056811 DQ_UI_PI_RATIO = 32
2217 17:16:24.059953 CA_UI_PI_RATIO = 0
2218 17:16:24.063151 ===================================
2219 17:16:24.066431 ===================================
2220 17:16:24.069699 memory_type:LPDDR4
2221 17:16:24.069805 GP_NUM : 10
2222 17:16:24.073075 SRAM_EN : 1
2223 17:16:24.076414 MD32_EN : 0
2224 17:16:24.079670 ===================================
2225 17:16:24.079830 [ANA_INIT] >>>>>>>>>>>>>>
2226 17:16:24.082854 <<<<<< [CONFIGURE PHASE]: ANA_TX
2227 17:16:24.086146 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
2228 17:16:24.090077 ===================================
2229 17:16:24.093244 data_rate = 2400,PCW = 0X5b00
2230 17:16:24.096576 ===================================
2231 17:16:24.099739 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
2232 17:16:24.106243 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2233 17:16:24.109395 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
2234 17:16:24.115964 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
2235 17:16:24.119182 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
2236 17:16:24.122501 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
2237 17:16:24.122613 [ANA_INIT] flow start
2238 17:16:24.126353 [ANA_INIT] PLL >>>>>>>>
2239 17:16:24.129551 [ANA_INIT] PLL <<<<<<<<
2240 17:16:24.132764 [ANA_INIT] MIDPI >>>>>>>>
2241 17:16:24.132875 [ANA_INIT] MIDPI <<<<<<<<
2242 17:16:24.136083 [ANA_INIT] DLL >>>>>>>>
2243 17:16:24.138936 [ANA_INIT] DLL <<<<<<<<
2244 17:16:24.139046 [ANA_INIT] flow end
2245 17:16:24.142701 ============ LP4 DIFF to SE enter ============
2246 17:16:24.149196 ============ LP4 DIFF to SE exit ============
2247 17:16:24.149337 [ANA_INIT] <<<<<<<<<<<<<
2248 17:16:24.152269 [Flow] Enable top DCM control >>>>>
2249 17:16:24.155989 [Flow] Enable top DCM control <<<<<
2250 17:16:24.159097 Enable DLL master slave shuffle
2251 17:16:24.165686 ==============================================================
2252 17:16:24.169066 Gating Mode config
2253 17:16:24.172378 ==============================================================
2254 17:16:24.175503 Config description:
2255 17:16:24.185373 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
2256 17:16:24.191843 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
2257 17:16:24.195836 SELPH_MODE 0: By rank 1: By Phase
2258 17:16:24.202280 ==============================================================
2259 17:16:24.205485 GAT_TRACK_EN = 1
2260 17:16:24.208672 RX_GATING_MODE = 2
2261 17:16:24.211913 RX_GATING_TRACK_MODE = 2
2262 17:16:24.212030 SELPH_MODE = 1
2263 17:16:24.215149 PICG_EARLY_EN = 1
2264 17:16:24.218384 VALID_LAT_VALUE = 1
2265 17:16:24.225107 ==============================================================
2266 17:16:24.228290 Enter into Gating configuration >>>>
2267 17:16:24.231440 Exit from Gating configuration <<<<
2268 17:16:24.235303 Enter into DVFS_PRE_config >>>>>
2269 17:16:24.244894 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
2270 17:16:24.248108 Exit from DVFS_PRE_config <<<<<
2271 17:16:24.251352 Enter into PICG configuration >>>>
2272 17:16:24.254607 Exit from PICG configuration <<<<
2273 17:16:24.257726 [RX_INPUT] configuration >>>>>
2274 17:16:24.261642 [RX_INPUT] configuration <<<<<
2275 17:16:24.264851 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
2276 17:16:24.271414 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
2277 17:16:24.277862 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
2278 17:16:24.284318 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
2279 17:16:24.290814 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
2280 17:16:24.298094 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
2281 17:16:24.300777 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
2282 17:16:24.304078 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
2283 17:16:24.307912 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
2284 17:16:24.311117 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
2285 17:16:24.314242
2286 17:16:24.317541 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
2287 17:16:24.320668 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2288 17:16:24.324043 ===================================
2289 17:16:24.327278 LPDDR4 DRAM CONFIGURATION
2290 17:16:24.330405 ===================================
2291 17:16:24.330593 EX_ROW_EN[0] = 0x0
2292 17:16:24.334205 EX_ROW_EN[1] = 0x0
2293 17:16:24.334374 LP4Y_EN = 0x0
2294 17:16:24.337480
2295 17:16:24.337619 WORK_FSP = 0x0
2296 17:16:24.340694 WL = 0x4
2297 17:16:24.340787 RL = 0x4
2298 17:16:24.344091 BL = 0x2
2299 17:16:24.344188 RPST = 0x0
2300 17:16:24.347280 RD_PRE = 0x0
2301 17:16:24.347373 WR_PRE = 0x1
2302 17:16:24.350438 WR_PST = 0x0
2303 17:16:24.350529 DBI_WR = 0x0
2304 17:16:24.353588 DBI_RD = 0x0
2305 17:16:24.353683 OTF = 0x1
2306 17:16:24.356838 ===================================
2307 17:16:24.360090 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
2308 17:16:24.367345 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
2309 17:16:24.370670 [ModeRegister RLWL Config] data_rate:2400-MR2_RLWL:4
2310 17:16:24.373864 ===================================
2311 17:16:24.377119 LPDDR4 DRAM CONFIGURATION
2312 17:16:24.379777 ===================================
2313 17:16:24.379906 EX_ROW_EN[0] = 0x10
2314 17:16:24.383744 EX_ROW_EN[1] = 0x0
2315 17:16:24.386344 LP4Y_EN = 0x0
2316 17:16:24.386474 WORK_FSP = 0x0
2317 17:16:24.389612 WL = 0x4
2318 17:16:24.389705 RL = 0x4
2319 17:16:24.393401 BL = 0x2
2320 17:16:24.393502 RPST = 0x0
2321 17:16:24.396602 RD_PRE = 0x0
2322 17:16:24.396706 WR_PRE = 0x1
2323 17:16:24.399822 WR_PST = 0x0
2324 17:16:24.399972 DBI_WR = 0x0
2325 17:16:24.403200 DBI_RD = 0x0
2326 17:16:24.403319 OTF = 0x1
2327 17:16:24.406458 ===================================
2328 17:16:24.413055 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
2329 17:16:24.413178 ==
2330 17:16:24.416751 Dram Type= 6, Freq= 0, CH_0, rank 0
2331 17:16:24.419886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2332 17:16:24.423093 ==
2333 17:16:24.423197 [Duty_Offset_Calibration]
2334 17:16:24.426452 B0:2 B1:0 CA:4
2335 17:16:24.426547
2336 17:16:24.429755 [DutyScan_Calibration_Flow] k_type=0
2337 17:16:24.437384
2338 17:16:24.437506 ==CLK 0==
2339 17:16:24.440625 Final CLK duty delay cell = -4
2340 17:16:24.443952 [-4] MAX Duty = 5062%(X100), DQS PI = 32
2341 17:16:24.447175 [-4] MIN Duty = 4844%(X100), DQS PI = 8
2342 17:16:24.450355 [-4] AVG Duty = 4953%(X100)
2343 17:16:24.450469
2344 17:16:24.453452 CH0 CLK Duty spec in!! Max-Min= 218%
2345 17:16:24.457285 [DutyScan_Calibration_Flow] ====Done====
2346 17:16:24.457402
2347 17:16:24.460594 [DutyScan_Calibration_Flow] k_type=1
2348 17:16:24.476082
2349 17:16:24.476226 ==DQS 0 ==
2350 17:16:24.479342 Final DQS duty delay cell = -4
2351 17:16:24.482524 [-4] MAX Duty = 4969%(X100), DQS PI = 14
2352 17:16:24.485732 [-4] MIN Duty = 4876%(X100), DQS PI = 2
2353 17:16:24.489013 [-4] AVG Duty = 4922%(X100)
2354 17:16:24.489124
2355 17:16:24.489201 ==DQS 1 ==
2356 17:16:24.492312 Final DQS duty delay cell = 0
2357 17:16:24.495496 [0] MAX Duty = 5125%(X100), DQS PI = 48
2358 17:16:24.498762 [0] MIN Duty = 5000%(X100), DQS PI = 0
2359 17:16:24.502071 [0] AVG Duty = 5062%(X100)
2360 17:16:24.502177
2361 17:16:24.505936 CH0 DQS 0 Duty spec in!! Max-Min= 93%
2362 17:16:24.506030
2363 17:16:24.509188 CH0 DQS 1 Duty spec in!! Max-Min= 125%
2364 17:16:24.512538 [DutyScan_Calibration_Flow] ====Done====
2365 17:16:24.512640
2366 17:16:24.515706 [DutyScan_Calibration_Flow] k_type=3
2367 17:16:24.533012
2368 17:16:24.533155 ==DQM 0 ==
2369 17:16:24.536173 Final DQM duty delay cell = 0
2370 17:16:24.539483 [0] MAX Duty = 5125%(X100), DQS PI = 20
2371 17:16:24.542562 [0] MIN Duty = 4844%(X100), DQS PI = 54
2372 17:16:24.545740 [0] AVG Duty = 4984%(X100)
2373 17:16:24.545848
2374 17:16:24.545916 ==DQM 1 ==
2375 17:16:24.548976 Final DQM duty delay cell = 0
2376 17:16:24.552830 [0] MAX Duty = 4969%(X100), DQS PI = 0
2377 17:16:24.555989 [0] MIN Duty = 4907%(X100), DQS PI = 10
2378 17:16:24.559187 [0] AVG Duty = 4938%(X100)
2379 17:16:24.559353
2380 17:16:24.562773 CH0 DQM 0 Duty spec in!! Max-Min= 281%
2381 17:16:24.562866
2382 17:16:24.566041 CH0 DQM 1 Duty spec in!! Max-Min= 62%
2383 17:16:24.569208 [DutyScan_Calibration_Flow] ====Done====
2384 17:16:24.569315
2385 17:16:24.572423 [DutyScan_Calibration_Flow] k_type=2
2386 17:16:24.589472
2387 17:16:24.589687 ==DQ 0 ==
2388 17:16:24.592682 Final DQ duty delay cell = 0
2389 17:16:24.595987 [0] MAX Duty = 5125%(X100), DQS PI = 18
2390 17:16:24.599198 [0] MIN Duty = 4969%(X100), DQS PI = 38
2391 17:16:24.599297 [0] AVG Duty = 5047%(X100)
2392 17:16:24.602522
2393 17:16:24.602613 ==DQ 1 ==
2394 17:16:24.605793 Final DQ duty delay cell = 0
2395 17:16:24.609134 [0] MAX Duty = 5125%(X100), DQS PI = 4
2396 17:16:24.612423 [0] MIN Duty = 4938%(X100), DQS PI = 16
2397 17:16:24.612520 [0] AVG Duty = 5031%(X100)
2398 17:16:24.612586
2399 17:16:24.615866
2400 17:16:24.618773 CH0 DQ 0 Duty spec in!! Max-Min= 156%
2401 17:16:24.618870
2402 17:16:24.621897 CH0 DQ 1 Duty spec in!! Max-Min= 187%
2403 17:16:24.625326 [DutyScan_Calibration_Flow] ====Done====
2404 17:16:24.625430 ==
2405 17:16:24.628594 Dram Type= 6, Freq= 0, CH_1, rank 0
2406 17:16:24.631848 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2407 17:16:24.631948 ==
2408 17:16:24.635100 [Duty_Offset_Calibration]
2409 17:16:24.635211 B0:0 B1:-1 CA:3
2410 17:16:24.635304
2411 17:16:24.638273 [DutyScan_Calibration_Flow] k_type=0
2412 17:16:24.648490
2413 17:16:24.648642 ==CLK 0==
2414 17:16:24.651704 Final CLK duty delay cell = -4
2415 17:16:24.655132 [-4] MAX Duty = 5000%(X100), DQS PI = 2
2416 17:16:24.658420 [-4] MIN Duty = 4876%(X100), DQS PI = 36
2417 17:16:24.661481 [-4] AVG Duty = 4938%(X100)
2418 17:16:24.661579
2419 17:16:24.664580 CH1 CLK Duty spec in!! Max-Min= 124%
2420 17:16:24.668496 [DutyScan_Calibration_Flow] ====Done====
2421 17:16:24.668628
2422 17:16:24.671610 [DutyScan_Calibration_Flow] k_type=1
2423 17:16:24.687319
2424 17:16:24.687470 ==DQS 0 ==
2425 17:16:24.690631 Final DQS duty delay cell = 0
2426 17:16:24.693717 [0] MAX Duty = 5187%(X100), DQS PI = 18
2427 17:16:24.697030 [0] MIN Duty = 4907%(X100), DQS PI = 38
2428 17:16:24.700343 [0] AVG Duty = 5047%(X100)
2429 17:16:24.700448
2430 17:16:24.700518 ==DQS 1 ==
2431 17:16:24.703595 Final DQS duty delay cell = -4
2432 17:16:24.706864 [-4] MAX Duty = 5000%(X100), DQS PI = 10
2433 17:16:24.710087 [-4] MIN Duty = 4875%(X100), DQS PI = 2
2434 17:16:24.713322 [-4] AVG Duty = 4937%(X100)
2435 17:16:24.713423
2436 17:16:24.716663 CH1 DQS 0 Duty spec in!! Max-Min= 280%
2437 17:16:24.716762
2438 17:16:24.719846 CH1 DQS 1 Duty spec in!! Max-Min= 125%
2439 17:16:24.723729 [DutyScan_Calibration_Flow] ====Done====
2440 17:16:24.723826
2441 17:16:24.726841 [DutyScan_Calibration_Flow] k_type=3
2442 17:16:24.744260
2443 17:16:24.744408 ==DQM 0 ==
2444 17:16:24.747496 Final DQM duty delay cell = 0
2445 17:16:24.750624 [0] MAX Duty = 5031%(X100), DQS PI = 28
2446 17:16:24.753443 [0] MIN Duty = 4782%(X100), DQS PI = 38
2447 17:16:24.757329 [0] AVG Duty = 4906%(X100)
2448 17:16:24.757443
2449 17:16:24.757517 ==DQM 1 ==
2450 17:16:24.760447 Final DQM duty delay cell = 0
2451 17:16:24.763730 [0] MAX Duty = 5000%(X100), DQS PI = 34
2452 17:16:24.766909 [0] MIN Duty = 4844%(X100), DQS PI = 0
2453 17:16:24.770173 [0] AVG Duty = 4922%(X100)
2454 17:16:24.770278
2455 17:16:24.773401 CH1 DQM 0 Duty spec in!! Max-Min= 249%
2456 17:16:24.773499
2457 17:16:24.776697 CH1 DQM 1 Duty spec in!! Max-Min= 156%
2458 17:16:24.780078 [DutyScan_Calibration_Flow] ====Done====
2459 17:16:24.780179
2460 17:16:24.783401 [DutyScan_Calibration_Flow] k_type=2
2461 17:16:24.799603
2462 17:16:24.799748 ==DQ 0 ==
2463 17:16:24.802740 Final DQ duty delay cell = -4
2464 17:16:24.805978 [-4] MAX Duty = 5031%(X100), DQS PI = 30
2465 17:16:24.809189 [-4] MIN Duty = 4844%(X100), DQS PI = 36
2466 17:16:24.813221 [-4] AVG Duty = 4937%(X100)
2467 17:16:24.813321
2468 17:16:24.813392 ==DQ 1 ==
2469 17:16:24.816503 Final DQ duty delay cell = 0
2470 17:16:24.819644 [0] MAX Duty = 5031%(X100), DQS PI = 34
2471 17:16:24.822900 [0] MIN Duty = 4844%(X100), DQS PI = 62
2472 17:16:24.826202 [0] AVG Duty = 4937%(X100)
2473 17:16:24.826320
2474 17:16:24.829351 CH1 DQ 0 Duty spec in!! Max-Min= 187%
2475 17:16:24.829452
2476 17:16:24.832513 CH1 DQ 1 Duty spec in!! Max-Min= 187%
2477 17:16:24.835831 [DutyScan_Calibration_Flow] ====Done====
2478 17:16:24.839094 nWR fixed to 30
2479 17:16:24.842811 [ModeRegInit_LP4] CH0 RK0
2480 17:16:24.842922 [ModeRegInit_LP4] CH0 RK1
2481 17:16:24.845970 [ModeRegInit_LP4] CH1 RK0
2482 17:16:24.849009 [ModeRegInit_LP4] CH1 RK1
2483 17:16:24.849120 match AC timing 7
2484 17:16:24.855685 dramType 5, freq 1200, readDBI 0, DivMode 1, cbtMode 1
2485 17:16:24.859553 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
2486 17:16:24.862809 [WriteLatency GET] Version:0-MR_RL_field_value:4-WL:12
2487 17:16:24.869058 [TX_path_calculate] data rate=2400, WL=12, DQS_TotalUI=25
2488 17:16:24.872264 [TX_path_calculate] DQS = (3,1) DQS_OE = (2,6)
2489 17:16:24.872393 ==
2490 17:16:24.875464 Dram Type= 6, Freq= 0, CH_0, rank 0
2491 17:16:24.878799 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2492 17:16:24.878910 ==
2493 17:16:24.885466 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2494 17:16:24.891841 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2495 17:16:24.899732 [CA 0] Center 39 (9~70) winsize 62
2496 17:16:24.903482 [CA 1] Center 39 (9~69) winsize 61
2497 17:16:24.906647 [CA 2] Center 35 (5~66) winsize 62
2498 17:16:24.910018 [CA 3] Center 35 (5~66) winsize 62
2499 17:16:24.913360 [CA 4] Center 33 (3~64) winsize 62
2500 17:16:24.916691 [CA 5] Center 33 (3~64) winsize 62
2501 17:16:24.916799
2502 17:16:24.919941 [CmdBusTrainingLP45] Vref(ca) range 1: 35
2503 17:16:24.920038
2504 17:16:24.923099 [CATrainingPosCal] consider 1 rank data
2505 17:16:24.926258 u2DelayCellTimex100 = 270/100 ps
2506 17:16:24.929463 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2507 17:16:24.936593 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2508 17:16:24.939879 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2509 17:16:24.943080 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2510 17:16:24.946222 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
2511 17:16:24.949426 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2512 17:16:24.949537
2513 17:16:24.952766 CA PerBit enable=1, Macro0, CA PI delay=33
2514 17:16:24.952906
2515 17:16:24.956121 [CBTSetCACLKResult] CA Dly = 33
2516 17:16:24.959339 CS Dly: 7 (0~38)
2517 17:16:24.959434 ==
2518 17:16:24.962630 Dram Type= 6, Freq= 0, CH_0, rank 1
2519 17:16:24.965775 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2520 17:16:24.965916 ==
2521 17:16:24.972890 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
2522 17:16:24.975500 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
2523 17:16:24.986095 [CA 0] Center 39 (9~70) winsize 62
2524 17:16:24.989368 [CA 1] Center 39 (9~70) winsize 62
2525 17:16:24.992612 [CA 2] Center 35 (5~66) winsize 62
2526 17:16:24.995860 [CA 3] Center 35 (5~66) winsize 62
2527 17:16:24.999162 [CA 4] Center 34 (4~65) winsize 62
2528 17:16:25.002388 [CA 5] Center 33 (3~64) winsize 62
2529 17:16:25.002512
2530 17:16:25.005568 [CmdBusTrainingLP45] Vref(ca) range 1: 37
2531 17:16:25.005694
2532 17:16:25.008753 [CATrainingPosCal] consider 2 rank data
2533 17:16:25.012152 u2DelayCellTimex100 = 270/100 ps
2534 17:16:25.015514 CA0 delay=39 (9~70),Diff = 6 PI (28 cell)
2535 17:16:25.022120 CA1 delay=39 (9~69),Diff = 6 PI (28 cell)
2536 17:16:25.025250 CA2 delay=35 (5~66),Diff = 2 PI (9 cell)
2537 17:16:25.028568 CA3 delay=35 (5~66),Diff = 2 PI (9 cell)
2538 17:16:25.031785 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
2539 17:16:25.034928 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
2540 17:16:25.035060
2541 17:16:25.038123 CA PerBit enable=1, Macro0, CA PI delay=33
2542 17:16:25.038243
2543 17:16:25.042145 [CBTSetCACLKResult] CA Dly = 33
2544 17:16:25.045232 CS Dly: 8 (0~41)
2545 17:16:25.045366
2546 17:16:25.048341 ----->DramcWriteLeveling(PI) begin...
2547 17:16:25.048467 ==
2548 17:16:25.051601 Dram Type= 6, Freq= 0, CH_0, rank 0
2549 17:16:25.055447 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2550 17:16:25.055586 ==
2551 17:16:25.058023 Write leveling (Byte 0): 34 => 34
2552 17:16:25.061401 Write leveling (Byte 1): 26 => 26
2553 17:16:25.065149 DramcWriteLeveling(PI) end<-----
2554 17:16:25.065278
2555 17:16:25.065380 ==
2556 17:16:25.068470 Dram Type= 6, Freq= 0, CH_0, rank 0
2557 17:16:25.071660 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2558 17:16:25.071787 ==
2559 17:16:25.074831 [Gating] SW mode calibration
2560 17:16:25.081347 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2561 17:16:25.088093 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2562 17:16:25.091460 0 15 0 | B1->B0 | 2323 3434 | 0 1 | (0 0) (1 1)
2563 17:16:25.094596 0 15 4 | B1->B0 | 2a2a 3434 | 0 1 | (0 0) (1 1)
2564 17:16:25.101158 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2565 17:16:25.104462 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2566 17:16:25.107602 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2567 17:16:25.114157 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2568 17:16:25.117490 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2569 17:16:25.120812 0 15 28 | B1->B0 | 3434 2929 | 1 0 | (1 1) (1 0)
2570 17:16:25.127275 1 0 0 | B1->B0 | 3333 2323 | 1 0 | (1 1) (0 0)
2571 17:16:25.131145 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
2572 17:16:25.134345 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2573 17:16:25.140800 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2574 17:16:25.144149 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2575 17:16:25.147265 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2576 17:16:25.154258 1 0 24 | B1->B0 | 2323 2929 | 0 0 | (0 0) (0 0)
2577 17:16:25.157463 1 0 28 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
2578 17:16:25.160765 1 1 0 | B1->B0 | 2929 4646 | 0 0 | (0 0) (0 0)
2579 17:16:25.167127 1 1 4 | B1->B0 | 4343 4646 | 1 0 | (0 0) (0 0)
2580 17:16:25.170300 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2581 17:16:25.173408 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2582 17:16:25.180438 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2583 17:16:25.183959 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2584 17:16:25.187150 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2585 17:16:25.193703 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2586 17:16:25.197089 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2587 17:16:25.200411 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2588 17:16:25.206836 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2589 17:16:25.210000 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2590 17:16:25.213326 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2591 17:16:25.219898 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2592 17:16:25.223139 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2593 17:16:25.226346 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2594 17:16:25.233316 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2595 17:16:25.236441 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2596 17:16:25.239768 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2597 17:16:25.246264 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2598 17:16:25.249535 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2599 17:16:25.252641 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2600 17:16:25.259079 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2601 17:16:25.262269 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2602 17:16:25.266083 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2603 17:16:25.269318 Total UI for P1: 0, mck2ui 16
2604 17:16:25.272470 best dqsien dly found for B0: ( 1, 3, 26)
2605 17:16:25.279095 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2606 17:16:25.282284 Total UI for P1: 0, mck2ui 16
2607 17:16:25.285619 best dqsien dly found for B1: ( 1, 4, 0)
2608 17:16:25.288687 best DQS0 dly(MCK, UI, PI) = (1, 3, 26)
2609 17:16:25.292007 best DQS1 dly(MCK, UI, PI) = (1, 4, 0)
2610 17:16:25.292122
2611 17:16:25.295365 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 26)
2612 17:16:25.298654 best DQS1 P1 dly(MCK, UI, PI) = (1, 8, 0)
2613 17:16:25.301787 [Gating] SW calibration Done
2614 17:16:25.301911 ==
2615 17:16:25.305143 Dram Type= 6, Freq= 0, CH_0, rank 0
2616 17:16:25.308437 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2617 17:16:25.308553 ==
2618 17:16:25.311755 RX Vref Scan: 0
2619 17:16:25.311865
2620 17:16:25.315044 RX Vref 0 -> 0, step: 1
2621 17:16:25.315154
2622 17:16:25.315251 RX Delay -40 -> 252, step: 8
2623 17:16:25.321702 iDelay=200, Bit 0, Center 115 (40 ~ 191) 152
2624 17:16:25.325062 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2625 17:16:25.328302 iDelay=200, Bit 2, Center 119 (48 ~ 191) 144
2626 17:16:25.332197 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2627 17:16:25.335361 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2628 17:16:25.341636 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2629 17:16:25.344985 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
2630 17:16:25.348260 iDelay=200, Bit 7, Center 127 (56 ~ 199) 144
2631 17:16:25.351477 iDelay=200, Bit 8, Center 95 (24 ~ 167) 144
2632 17:16:25.354609 iDelay=200, Bit 9, Center 95 (24 ~ 167) 144
2633 17:16:25.361645 iDelay=200, Bit 10, Center 107 (40 ~ 175) 136
2634 17:16:25.364796 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2635 17:16:25.367941 iDelay=200, Bit 12, Center 119 (48 ~ 191) 144
2636 17:16:25.371110 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2637 17:16:25.377468 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
2638 17:16:25.381446 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2639 17:16:25.381564 ==
2640 17:16:25.384637 Dram Type= 6, Freq= 0, CH_0, rank 0
2641 17:16:25.387966 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2642 17:16:25.388085 ==
2643 17:16:25.388184 DQS Delay:
2644 17:16:25.391186
2645 17:16:25.391297 DQS0 = 0, DQS1 = 0
2646 17:16:25.391395 DQM Delay:
2647 17:16:25.394508 DQM0 = 118, DQM1 = 108
2648 17:16:25.394618 DQ Delay:
2649 17:16:25.397729 DQ0 =115, DQ1 =119, DQ2 =119, DQ3 =111
2650 17:16:25.400985 DQ4 =119, DQ5 =111, DQ6 =123, DQ7 =127
2651 17:16:25.404145 DQ8 =95, DQ9 =95, DQ10 =107, DQ11 =103
2652 17:16:25.407472 DQ12 =119, DQ13 =115, DQ14 =119, DQ15 =115
2653 17:16:25.410653
2654 17:16:25.410770
2655 17:16:25.410868
2656 17:16:25.411000 ==
2657 17:16:25.413931 Dram Type= 6, Freq= 0, CH_0, rank 0
2658 17:16:25.417752 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2659 17:16:25.417882 ==
2660 17:16:25.417986
2661 17:16:25.418095
2662 17:16:25.421075 TX Vref Scan disable
2663 17:16:25.421185 == TX Byte 0 ==
2664 17:16:25.427483 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2665 17:16:25.430726 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2666 17:16:25.430838 == TX Byte 1 ==
2667 17:16:25.437201 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2668 17:16:25.440399 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2669 17:16:25.440514 ==
2670 17:16:25.443686 Dram Type= 6, Freq= 0, CH_0, rank 0
2671 17:16:25.446813 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2672 17:16:25.446963 ==
2673 17:16:25.460750 TX Vref=22, minBit 1, minWin=25, winSum=408
2674 17:16:25.463972 TX Vref=24, minBit 10, minWin=24, winSum=410
2675 17:16:25.467280 TX Vref=26, minBit 7, minWin=25, winSum=422
2676 17:16:25.470560 TX Vref=28, minBit 1, minWin=26, winSum=426
2677 17:16:25.474320 TX Vref=30, minBit 4, minWin=26, winSum=431
2678 17:16:25.480764 TX Vref=32, minBit 4, minWin=26, winSum=427
2679 17:16:25.484041 [TxChooseVref] Worse bit 4, Min win 26, Win sum 431, Final Vref 30
2680 17:16:25.484162
2681 17:16:25.487236 Final TX Range 1 Vref 30
2682 17:16:25.487355
2683 17:16:25.487453 ==
2684 17:16:25.490655 Dram Type= 6, Freq= 0, CH_0, rank 0
2685 17:16:25.493862 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2686 17:16:25.497086 ==
2687 17:16:25.497198
2688 17:16:25.497296
2689 17:16:25.497390 TX Vref Scan disable
2690 17:16:25.500368 == TX Byte 0 ==
2691 17:16:25.503692 Update DQ dly =853 (3 ,2, 21) DQ OEN =(2 ,7)
2692 17:16:25.507488 Update DQM dly =853 (3 ,2, 21) DQM OEN =(2 ,7)
2693 17:16:25.510761
2694 17:16:25.510874 == TX Byte 1 ==
2695 17:16:25.514007 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2696 17:16:25.520528 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2697 17:16:25.520649
2698 17:16:25.520748 [DATLAT]
2699 17:16:25.520843 Freq=1200, CH0 RK0
2700 17:16:25.520937
2701 17:16:25.523790 DATLAT Default: 0xd
2702 17:16:25.523899 0, 0xFFFF, sum = 0
2703 17:16:25.527115
2704 17:16:25.527239 1, 0xFFFF, sum = 0
2705 17:16:25.530405 2, 0xFFFF, sum = 0
2706 17:16:25.530517 3, 0xFFFF, sum = 0
2707 17:16:25.533646 4, 0xFFFF, sum = 0
2708 17:16:25.533759 5, 0xFFFF, sum = 0
2709 17:16:25.537011 6, 0xFFFF, sum = 0
2710 17:16:25.537143 7, 0xFFFF, sum = 0
2711 17:16:25.540078 8, 0xFFFF, sum = 0
2712 17:16:25.540190 9, 0xFFFF, sum = 0
2713 17:16:25.543479 10, 0xFFFF, sum = 0
2714 17:16:25.543591 11, 0xFFFF, sum = 0
2715 17:16:25.546515 12, 0x0, sum = 1
2716 17:16:25.546626 13, 0x0, sum = 2
2717 17:16:25.549819 14, 0x0, sum = 3
2718 17:16:25.549931 15, 0x0, sum = 4
2719 17:16:25.553078 best_step = 13
2720 17:16:25.553187
2721 17:16:25.553285 ==
2722 17:16:25.556335 Dram Type= 6, Freq= 0, CH_0, rank 0
2723 17:16:25.559563 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2724 17:16:25.559674 ==
2725 17:16:25.563203 RX Vref Scan: 1
2726 17:16:25.563313
2727 17:16:25.563410 Set Vref Range= 32 -> 127
2728 17:16:25.563504
2729 17:16:25.566474 RX Vref 32 -> 127, step: 1
2730 17:16:25.566583
2731 17:16:25.569616 RX Delay -21 -> 252, step: 4
2732 17:16:25.569726
2733 17:16:25.572915 Set Vref, RX VrefLevel [Byte0]: 32
2734 17:16:25.576104 [Byte1]: 32
2735 17:16:25.576216
2736 17:16:25.580005 Set Vref, RX VrefLevel [Byte0]: 33
2737 17:16:25.583329 [Byte1]: 33
2738 17:16:25.587146
2739 17:16:25.587264 Set Vref, RX VrefLevel [Byte0]: 34
2740 17:16:25.590365 [Byte1]: 34
2741 17:16:25.594745
2742 17:16:25.594858 Set Vref, RX VrefLevel [Byte0]: 35
2743 17:16:25.598648 [Byte1]: 35
2744 17:16:25.603170
2745 17:16:25.603284 Set Vref, RX VrefLevel [Byte0]: 36
2746 17:16:25.606385 [Byte1]: 36
2747 17:16:25.610776
2748 17:16:25.610925 Set Vref, RX VrefLevel [Byte0]: 37
2749 17:16:25.614271 [Byte1]: 37
2750 17:16:25.618568
2751 17:16:25.618682 Set Vref, RX VrefLevel [Byte0]: 38
2752 17:16:25.621852 [Byte1]: 38
2753 17:16:25.627076
2754 17:16:25.627191 Set Vref, RX VrefLevel [Byte0]: 39
2755 17:16:25.630269 [Byte1]: 39
2756 17:16:25.634775
2757 17:16:25.634895 Set Vref, RX VrefLevel [Byte0]: 40
2758 17:16:25.637935 [Byte1]: 40
2759 17:16:25.642389
2760 17:16:25.642503 Set Vref, RX VrefLevel [Byte0]: 41
2761 17:16:25.645537 [Byte1]: 41
2762 17:16:25.650746
2763 17:16:25.650863 Set Vref, RX VrefLevel [Byte0]: 42
2764 17:16:25.653916 [Byte1]: 42
2765 17:16:25.658268
2766 17:16:25.658380 Set Vref, RX VrefLevel [Byte0]: 43
2767 17:16:25.661439 [Byte1]: 43
2768 17:16:25.666560
2769 17:16:25.666677 Set Vref, RX VrefLevel [Byte0]: 44
2770 17:16:25.669835 [Byte1]: 44
2771 17:16:25.674412
2772 17:16:25.674529 Set Vref, RX VrefLevel [Byte0]: 45
2773 17:16:25.677644 [Byte1]: 45
2774 17:16:25.682063
2775 17:16:25.682180 Set Vref, RX VrefLevel [Byte0]: 46
2776 17:16:25.685412 [Byte1]: 46
2777 17:16:25.690560
2778 17:16:25.690688 Set Vref, RX VrefLevel [Byte0]: 47
2779 17:16:25.693740 [Byte1]: 47
2780 17:16:25.698308
2781 17:16:25.698423 Set Vref, RX VrefLevel [Byte0]: 48
2782 17:16:25.701543 [Byte1]: 48
2783 17:16:25.706048
2784 17:16:25.706163 Set Vref, RX VrefLevel [Byte0]: 49
2785 17:16:25.709234 [Byte1]: 49
2786 17:16:25.713719
2787 17:16:25.713838 Set Vref, RX VrefLevel [Byte0]: 50
2788 17:16:25.716973 [Byte1]: 50
2789 17:16:25.722047
2790 17:16:25.722166 Set Vref, RX VrefLevel [Byte0]: 51
2791 17:16:25.725188 [Byte1]: 51
2792 17:16:25.729714
2793 17:16:25.729830 Set Vref, RX VrefLevel [Byte0]: 52
2794 17:16:25.732943 [Byte1]: 52
2795 17:16:25.738064
2796 17:16:25.738178 Set Vref, RX VrefLevel [Byte0]: 53
2797 17:16:25.741149 [Byte1]: 53
2798 17:16:25.745633
2799 17:16:25.745748 Set Vref, RX VrefLevel [Byte0]: 54
2800 17:16:25.748821 [Byte1]: 54
2801 17:16:25.753336
2802 17:16:25.753456 Set Vref, RX VrefLevel [Byte0]: 55
2803 17:16:25.756666 [Byte1]: 55
2804 17:16:25.761794
2805 17:16:25.761911 Set Vref, RX VrefLevel [Byte0]: 56
2806 17:16:25.765029 [Byte1]: 56
2807 17:16:25.769551
2808 17:16:25.769664 Set Vref, RX VrefLevel [Byte0]: 57
2809 17:16:25.772939 [Byte1]: 57
2810 17:16:25.777178
2811 17:16:25.777293 Set Vref, RX VrefLevel [Byte0]: 58
2812 17:16:25.780243 [Byte1]: 58
2813 17:16:25.785474
2814 17:16:25.785596 Set Vref, RX VrefLevel [Byte0]: 59
2815 17:16:25.788684 [Byte1]: 59
2816 17:16:25.793241
2817 17:16:25.793362 Set Vref, RX VrefLevel [Byte0]: 60
2818 17:16:25.796459 [Byte1]: 60
2819 17:16:25.801008
2820 17:16:25.801122 Set Vref, RX VrefLevel [Byte0]: 61
2821 17:16:25.804364 [Byte1]: 61
2822 17:16:25.808934
2823 17:16:25.809056 Set Vref, RX VrefLevel [Byte0]: 62
2824 17:16:25.812014 [Byte1]: 62
2825 17:16:25.817228
2826 17:16:25.817346 Set Vref, RX VrefLevel [Byte0]: 63
2827 17:16:25.819895 [Byte1]: 63
2828 17:16:25.825012
2829 17:16:25.825128 Set Vref, RX VrefLevel [Byte0]: 64
2830 17:16:25.827797 [Byte1]: 64
2831 17:16:25.832309
2832 17:16:25.832422 Set Vref, RX VrefLevel [Byte0]: 65
2833 17:16:25.836131
2834 17:16:25.836241 [Byte1]: 65
2835 17:16:25.839389
2836 17:16:25.839500
2837 17:16:25.842619 Set Vref, RX VrefLevel [Byte0]: 66
2838 17:16:25.845787 [Byte1]: 66
2839 17:16:25.845936
2840 17:16:25.848976 Set Vref, RX VrefLevel [Byte0]: 67
2841 17:16:25.852815 [Byte1]: 67
2842 17:16:25.856615
2843 17:16:25.856771 Set Vref, RX VrefLevel [Byte0]: 68
2844 17:16:25.859995 [Byte1]: 68
2845 17:16:25.864282
2846 17:16:25.864398 Final RX Vref Byte 0 = 57 to rank0
2847 17:16:25.867476 Final RX Vref Byte 1 = 58 to rank0
2848 17:16:25.871402 Final RX Vref Byte 0 = 57 to rank1
2849 17:16:25.874511 Final RX Vref Byte 1 = 58 to rank1==
2850 17:16:25.877675 Dram Type= 6, Freq= 0, CH_0, rank 0
2851 17:16:25.884140 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2852 17:16:25.884270 ==
2853 17:16:25.884371 DQS Delay:
2854 17:16:25.884466 DQS0 = 0, DQS1 = 0
2855 17:16:25.887628 DQM Delay:
2856 17:16:25.887742 DQM0 = 117, DQM1 = 105
2857 17:16:25.890874 DQ Delay:
2858 17:16:25.894150 DQ0 =118, DQ1 =116, DQ2 =114, DQ3 =112
2859 17:16:25.897483 DQ4 =120, DQ5 =112, DQ6 =126, DQ7 =120
2860 17:16:25.900629 DQ8 =94, DQ9 =90, DQ10 =106, DQ11 =100
2861 17:16:25.903938 DQ12 =114, DQ13 =110, DQ14 =118, DQ15 =114
2862 17:16:25.904027
2863 17:16:25.904095
2864 17:16:25.911186 [DQSOSCAuto] RK0, (LSB)MR18= 0xfef9, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 410 ps
2865 17:16:25.914383
2866 17:16:25.914472 CH0 RK0: MR19=303, MR18=FEF9
2867 17:16:25.920817 CH0_RK0: MR19=0x303, MR18=0xFEF9, DQSOSC=410, MR23=63, INC=39, DEC=26
2868 17:16:25.920930
2869 17:16:25.924144 ----->DramcWriteLeveling(PI) begin...
2870 17:16:25.924235 ==
2871 17:16:25.927362 Dram Type= 6, Freq= 0, CH_0, rank 1
2872 17:16:25.933946 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2873 17:16:25.934043 ==
2874 17:16:25.937205 Write leveling (Byte 0): 33 => 33
2875 17:16:25.937293 Write leveling (Byte 1): 26 => 26
2876 17:16:25.940452 DramcWriteLeveling(PI) end<-----
2877 17:16:25.940537
2878 17:16:25.943635 ==
2879 17:16:25.943721 Dram Type= 6, Freq= 0, CH_0, rank 1
2880 17:16:25.950497 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2881 17:16:25.950596 ==
2882 17:16:25.953808 [Gating] SW mode calibration
2883 17:16:25.960815 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
2884 17:16:25.963362 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
2885 17:16:25.970447 0 15 0 | B1->B0 | 2323 3434 | 1 1 | (0 0) (1 1)
2886 17:16:25.973737 0 15 4 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
2887 17:16:25.977016 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2888 17:16:25.983477 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2889 17:16:25.986590 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2890 17:16:25.990439 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
2891 17:16:25.996952 0 15 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
2892 17:16:26.000098 0 15 28 | B1->B0 | 3434 2727 | 1 0 | (1 0) (0 0)
2893 17:16:26.003489 1 0 0 | B1->B0 | 2d2d 2323 | 0 0 | (0 0) (0 0)
2894 17:16:26.009943 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2895 17:16:26.013157 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2896 17:16:26.016527 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2897 17:16:26.023526 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2898 17:16:26.026733 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
2899 17:16:26.029995 1 0 24 | B1->B0 | 2323 2b2a | 0 1 | (0 0) (0 0)
2900 17:16:26.036508 1 0 28 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
2901 17:16:26.039811 1 1 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
2902 17:16:26.042952 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2903 17:16:26.049507 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2904 17:16:26.052725 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2905 17:16:26.055976 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2906 17:16:26.062975 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2907 17:16:26.066180 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2908 17:16:26.069967 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
2909 17:16:26.075807 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
2910 17:16:26.079682 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2911 17:16:26.082766 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2912 17:16:26.089195 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2913 17:16:26.092372 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2914 17:16:26.095739 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2915 17:16:26.102206 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2916 17:16:26.105384 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2917 17:16:26.109122 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2918 17:16:26.115700 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2919 17:16:26.118942 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2920 17:16:26.122206 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2921 17:16:26.128704 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2922 17:16:26.131956 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
2923 17:16:26.135805 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
2924 17:16:26.142370 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2925 17:16:26.142473 Total UI for P1: 0, mck2ui 16
2926 17:16:26.148942 best dqsien dly found for B0: ( 1, 3, 24)
2927 17:16:26.152022 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
2928 17:16:26.155288 1 4 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
2929 17:16:26.158458 Total UI for P1: 0, mck2ui 16
2930 17:16:26.161915 best dqsien dly found for B1: ( 1, 3, 30)
2931 17:16:26.164962 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
2932 17:16:26.168230 best DQS1 dly(MCK, UI, PI) = (1, 3, 30)
2933 17:16:26.168318
2934 17:16:26.175086 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
2935 17:16:26.178252 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 30)
2936 17:16:26.178347 [Gating] SW calibration Done
2937 17:16:26.181417 ==
2938 17:16:26.184659 Dram Type= 6, Freq= 0, CH_0, rank 1
2939 17:16:26.187942 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2940 17:16:26.188041 ==
2941 17:16:26.188223 RX Vref Scan: 0
2942 17:16:26.188309
2943 17:16:26.191201 RX Vref 0 -> 0, step: 1
2944 17:16:26.191285
2945 17:16:26.194357 RX Delay -40 -> 252, step: 8
2946 17:16:26.197609 iDelay=200, Bit 0, Center 111 (40 ~ 183) 144
2947 17:16:26.200743 iDelay=200, Bit 1, Center 119 (48 ~ 191) 144
2948 17:16:26.207978 iDelay=200, Bit 2, Center 115 (48 ~ 183) 136
2949 17:16:26.211383 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
2950 17:16:26.214008 iDelay=200, Bit 4, Center 119 (48 ~ 191) 144
2951 17:16:26.217340 iDelay=200, Bit 5, Center 111 (40 ~ 183) 144
2952 17:16:26.220980 iDelay=200, Bit 6, Center 127 (56 ~ 199) 144
2953 17:16:26.227442 iDelay=200, Bit 7, Center 123 (48 ~ 199) 152
2954 17:16:26.230548 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
2955 17:16:26.233847 iDelay=200, Bit 9, Center 91 (24 ~ 159) 136
2956 17:16:26.237703 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
2957 17:16:26.240958 iDelay=200, Bit 11, Center 103 (32 ~ 175) 144
2958 17:16:26.247508 iDelay=200, Bit 12, Center 115 (48 ~ 183) 136
2959 17:16:26.250745 iDelay=200, Bit 13, Center 115 (48 ~ 183) 136
2960 17:16:26.254060 iDelay=200, Bit 14, Center 123 (56 ~ 191) 136
2961 17:16:26.257121 iDelay=200, Bit 15, Center 115 (48 ~ 183) 136
2962 17:16:26.257210 ==
2963 17:16:26.260483 Dram Type= 6, Freq= 0, CH_0, rank 1
2964 17:16:26.266864 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2965 17:16:26.267009 ==
2966 17:16:26.267077 DQS Delay:
2967 17:16:26.270066 DQS0 = 0, DQS1 = 0
2968 17:16:26.270141 DQM Delay:
2969 17:16:26.273349 DQM0 = 117, DQM1 = 109
2970 17:16:26.273437 DQ Delay:
2971 17:16:26.277150 DQ0 =111, DQ1 =119, DQ2 =115, DQ3 =111
2972 17:16:26.280382 DQ4 =119, DQ5 =111, DQ6 =127, DQ7 =123
2973 17:16:26.283679 DQ8 =99, DQ9 =91, DQ10 =111, DQ11 =103
2974 17:16:26.286890 DQ12 =115, DQ13 =115, DQ14 =123, DQ15 =115
2975 17:16:26.287017
2976 17:16:26.287084
2977 17:16:26.287145 ==
2978 17:16:26.290110 Dram Type= 6, Freq= 0, CH_0, rank 1
2979 17:16:26.296463 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2980 17:16:26.296579 ==
2981 17:16:26.296651
2982 17:16:26.296715
2983 17:16:26.296776 TX Vref Scan disable
2984 17:16:26.300410 == TX Byte 0 ==
2985 17:16:26.303027 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
2986 17:16:26.306909 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
2987 17:16:26.310241
2988 17:16:26.310349 == TX Byte 1 ==
2989 17:16:26.313497 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
2990 17:16:26.319889 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
2991 17:16:26.320025 ==
2992 17:16:26.323096 Dram Type= 6, Freq= 0, CH_0, rank 1
2993 17:16:26.326358 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
2994 17:16:26.326459 ==
2995 17:16:26.338613 TX Vref=22, minBit 8, minWin=25, winSum=417
2996 17:16:26.341677 TX Vref=24, minBit 13, minWin=25, winSum=421
2997 17:16:26.345052 TX Vref=26, minBit 1, minWin=26, winSum=426
2998 17:16:26.348319 TX Vref=28, minBit 12, minWin=26, winSum=430
2999 17:16:26.352079 TX Vref=30, minBit 10, minWin=26, winSum=428
3000 17:16:26.358479 TX Vref=32, minBit 4, minWin=26, winSum=430
3001 17:16:26.361745 [TxChooseVref] Worse bit 12, Min win 26, Win sum 430, Final Vref 28
3002 17:16:26.361843
3003 17:16:26.365037 Final TX Range 1 Vref 28
3004 17:16:26.365140
3005 17:16:26.365212 ==
3006 17:16:26.368136 Dram Type= 6, Freq= 0, CH_0, rank 1
3007 17:16:26.371439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3008 17:16:26.374655
3009 17:16:26.374769 ==
3010 17:16:26.374842
3011 17:16:26.374934
3012 17:16:26.374998 TX Vref Scan disable
3013 17:16:26.378445 == TX Byte 0 ==
3014 17:16:26.382337 Update DQ dly =852 (3 ,2, 20) DQ OEN =(2 ,7)
3015 17:16:26.388525 Update DQM dly =852 (3 ,2, 20) DQM OEN =(2 ,7)
3016 17:16:26.388682 == TX Byte 1 ==
3017 17:16:26.391846 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3018 17:16:26.398226 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3019 17:16:26.398344
3020 17:16:26.398416 [DATLAT]
3021 17:16:26.398485 Freq=1200, CH0 RK1
3022 17:16:26.398548
3023 17:16:26.402111 DATLAT Default: 0xd
3024 17:16:26.402206 0, 0xFFFF, sum = 0
3025 17:16:26.405404
3026 17:16:26.405490 1, 0xFFFF, sum = 0
3027 17:16:26.408648 2, 0xFFFF, sum = 0
3028 17:16:26.408781 3, 0xFFFF, sum = 0
3029 17:16:26.411393 4, 0xFFFF, sum = 0
3030 17:16:26.411495 5, 0xFFFF, sum = 0
3031 17:16:26.415369 6, 0xFFFF, sum = 0
3032 17:16:26.415465 7, 0xFFFF, sum = 0
3033 17:16:26.417941 8, 0xFFFF, sum = 0
3034 17:16:26.418019 9, 0xFFFF, sum = 0
3035 17:16:26.421860 10, 0xFFFF, sum = 0
3036 17:16:26.421941 11, 0xFFFF, sum = 0
3037 17:16:26.425231 12, 0x0, sum = 1
3038 17:16:26.425320 13, 0x0, sum = 2
3039 17:16:26.428366 14, 0x0, sum = 3
3040 17:16:26.428455 15, 0x0, sum = 4
3041 17:16:26.431108 best_step = 13
3042 17:16:26.431194
3043 17:16:26.431262 ==
3044 17:16:26.434828 Dram Type= 6, Freq= 0, CH_0, rank 1
3045 17:16:26.438034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3046 17:16:26.438130 ==
3047 17:16:26.441192 RX Vref Scan: 0
3048 17:16:26.441280
3049 17:16:26.441347 RX Vref 0 -> 0, step: 1
3050 17:16:26.441410
3051 17:16:26.444606 RX Delay -21 -> 252, step: 4
3052 17:16:26.451095 iDelay=195, Bit 0, Center 114 (47 ~ 182) 136
3053 17:16:26.454310 iDelay=195, Bit 1, Center 118 (51 ~ 186) 136
3054 17:16:26.458138 iDelay=195, Bit 2, Center 112 (47 ~ 178) 132
3055 17:16:26.461406 iDelay=195, Bit 3, Center 114 (47 ~ 182) 136
3056 17:16:26.464541 iDelay=195, Bit 4, Center 118 (51 ~ 186) 136
3057 17:16:26.471080 iDelay=195, Bit 5, Center 110 (43 ~ 178) 136
3058 17:16:26.474311 iDelay=195, Bit 6, Center 126 (59 ~ 194) 136
3059 17:16:26.477526 iDelay=195, Bit 7, Center 122 (55 ~ 190) 136
3060 17:16:26.481352 iDelay=195, Bit 8, Center 96 (31 ~ 162) 132
3061 17:16:26.484539 iDelay=195, Bit 9, Center 92 (27 ~ 158) 132
3062 17:16:26.487765 iDelay=195, Bit 10, Center 110 (43 ~ 178) 136
3063 17:16:26.494146 iDelay=195, Bit 11, Center 100 (31 ~ 170) 140
3064 17:16:26.497927 iDelay=195, Bit 12, Center 112 (47 ~ 178) 132
3065 17:16:26.501097 iDelay=195, Bit 13, Center 112 (47 ~ 178) 132
3066 17:16:26.504387 iDelay=195, Bit 14, Center 118 (55 ~ 182) 128
3067 17:16:26.510758 iDelay=195, Bit 15, Center 114 (51 ~ 178) 128
3068 17:16:26.510872 ==
3069 17:16:26.514094 Dram Type= 6, Freq= 0, CH_0, rank 1
3070 17:16:26.517391 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3071 17:16:26.517476 ==
3072 17:16:26.517543 DQS Delay:
3073 17:16:26.520590 DQS0 = 0, DQS1 = 0
3074 17:16:26.520682 DQM Delay:
3075 17:16:26.524469 DQM0 = 116, DQM1 = 106
3076 17:16:26.524553 DQ Delay:
3077 17:16:26.527668 DQ0 =114, DQ1 =118, DQ2 =112, DQ3 =114
3078 17:16:26.531017 DQ4 =118, DQ5 =110, DQ6 =126, DQ7 =122
3079 17:16:26.533695 DQ8 =96, DQ9 =92, DQ10 =110, DQ11 =100
3080 17:16:26.537001 DQ12 =112, DQ13 =112, DQ14 =118, DQ15 =114
3081 17:16:26.537100
3082 17:16:26.537168
3083 17:16:26.540937
3084 17:16:26.547250 [DQSOSCAuto] RK1, (LSB)MR18= 0xfdfb, (MSB)MR19= 0x303, tDQSOscB0 = 412 ps tDQSOscB1 = 411 ps
3085 17:16:26.550444 CH0 RK1: MR19=303, MR18=FDFB
3086 17:16:26.557032 CH0_RK1: MR19=0x303, MR18=0xFDFB, DQSOSC=411, MR23=63, INC=38, DEC=25
3087 17:16:26.557139 [RxdqsGatingPostProcess] freq 1200
3088 17:16:26.560858
3089 17:16:26.563538 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3090 17:16:26.567287 best DQS0 dly(2T, 0.5T) = (0, 11)
3091 17:16:26.570565 best DQS1 dly(2T, 0.5T) = (0, 12)
3092 17:16:26.573853 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3093 17:16:26.576991 best DQS1 P1 dly(2T, 0.5T) = (1, 0)
3094 17:16:26.580139 best DQS0 dly(2T, 0.5T) = (0, 11)
3095 17:16:26.583341 best DQS1 dly(2T, 0.5T) = (0, 11)
3096 17:16:26.587285 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3097 17:16:26.590436 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3098 17:16:26.593616 Pre-setting of DQS Precalculation
3099 17:16:26.596786 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3100 17:16:26.596882 ==
3101 17:16:26.600019 Dram Type= 6, Freq= 0, CH_1, rank 0
3102 17:16:26.606346 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3103 17:16:26.606472 ==
3104 17:16:26.609689 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3105 17:16:26.616718 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=29, u1VrefScanEnd=39
3106 17:16:26.625133 [CA 0] Center 38 (8~68) winsize 61
3107 17:16:26.628361 [CA 1] Center 37 (7~68) winsize 62
3108 17:16:26.631502 [CA 2] Center 35 (5~65) winsize 61
3109 17:16:26.634790 [CA 3] Center 34 (4~64) winsize 61
3110 17:16:26.638031 [CA 4] Center 34 (4~65) winsize 62
3111 17:16:26.641295 [CA 5] Center 34 (4~64) winsize 61
3112 17:16:26.641395
3113 17:16:26.644624 [CmdBusTrainingLP45] Vref(ca) range 1: 37
3114 17:16:26.644713
3115 17:16:26.648417 [CATrainingPosCal] consider 1 rank data
3116 17:16:26.651664 u2DelayCellTimex100 = 270/100 ps
3117 17:16:26.654959 CA0 delay=38 (8~68),Diff = 4 PI (19 cell)
3118 17:16:26.661503 CA1 delay=37 (7~68),Diff = 3 PI (14 cell)
3119 17:16:26.664715 CA2 delay=35 (5~65),Diff = 1 PI (4 cell)
3120 17:16:26.668141 CA3 delay=34 (4~64),Diff = 0 PI (0 cell)
3121 17:16:26.671341 CA4 delay=34 (4~65),Diff = 0 PI (0 cell)
3122 17:16:26.674449 CA5 delay=34 (4~64),Diff = 0 PI (0 cell)
3123 17:16:26.674542
3124 17:16:26.677760 CA PerBit enable=1, Macro0, CA PI delay=34
3125 17:16:26.677857
3126 17:16:26.681505 [CBTSetCACLKResult] CA Dly = 34
3127 17:16:26.681600 CS Dly: 5 (0~36)
3128 17:16:26.684598 ==
3129 17:16:26.687950 Dram Type= 6, Freq= 0, CH_1, rank 1
3130 17:16:26.691118 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3131 17:16:26.691223 ==
3132 17:16:26.694355 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3133 17:16:26.697603
3134 17:16:26.701346 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=27, u1VrefScanEnd=37
3135 17:16:26.710843 [CA 0] Center 37 (7~68) winsize 62
3136 17:16:26.714118 [CA 1] Center 37 (7~68) winsize 62
3137 17:16:26.717428 [CA 2] Center 35 (5~65) winsize 61
3138 17:16:26.720701 [CA 3] Center 34 (4~64) winsize 61
3139 17:16:26.723904 [CA 4] Center 34 (4~64) winsize 61
3140 17:16:26.727147 [CA 5] Center 33 (3~63) winsize 61
3141 17:16:26.727244
3142 17:16:26.730393 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3143 17:16:26.730494
3144 17:16:26.733628 [CATrainingPosCal] consider 2 rank data
3145 17:16:26.736981 u2DelayCellTimex100 = 270/100 ps
3146 17:16:26.740374 CA0 delay=38 (8~68),Diff = 5 PI (24 cell)
3147 17:16:26.747006 CA1 delay=37 (7~68),Diff = 4 PI (19 cell)
3148 17:16:26.750057 CA2 delay=35 (5~65),Diff = 2 PI (9 cell)
3149 17:16:26.754109 CA3 delay=34 (4~64),Diff = 1 PI (4 cell)
3150 17:16:26.756685 CA4 delay=34 (4~64),Diff = 1 PI (4 cell)
3151 17:16:26.759996 CA5 delay=33 (4~63),Diff = 0 PI (0 cell)
3152 17:16:26.760101
3153 17:16:26.763837 CA PerBit enable=1, Macro0, CA PI delay=33
3154 17:16:26.763945
3155 17:16:26.766923 [CBTSetCACLKResult] CA Dly = 33
3156 17:16:26.767015 CS Dly: 6 (0~39)
3157 17:16:26.770352
3158 17:16:26.770451
3159 17:16:26.773503 ----->DramcWriteLeveling(PI) begin...
3160 17:16:26.773594 ==
3161 17:16:26.776741 Dram Type= 6, Freq= 0, CH_1, rank 0
3162 17:16:26.779920 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3163 17:16:26.780023 ==
3164 17:16:26.783141 Write leveling (Byte 0): 24 => 24
3165 17:16:26.786986 Write leveling (Byte 1): 26 => 26
3166 17:16:26.790216 DramcWriteLeveling(PI) end<-----
3167 17:16:26.790321
3168 17:16:26.790393 ==
3169 17:16:26.793422 Dram Type= 6, Freq= 0, CH_1, rank 0
3170 17:16:26.796593 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3171 17:16:26.796677 ==
3172 17:16:26.799869 [Gating] SW mode calibration
3173 17:16:26.806255 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3174 17:16:26.813325 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3175 17:16:26.816654 0 15 0 | B1->B0 | 3131 3434 | 1 1 | (1 1) (1 1)
3176 17:16:26.819903 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3177 17:16:26.826363 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3178 17:16:26.829710 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3179 17:16:26.832809 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3180 17:16:26.839365 0 15 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3181 17:16:26.843219 0 15 24 | B1->B0 | 3434 3434 | 1 0 | (1 0) (0 0)
3182 17:16:26.846480 0 15 28 | B1->B0 | 2b2b 2828 | 0 0 | (0 0) (1 0)
3183 17:16:26.852937 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3184 17:16:26.856197 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3185 17:16:26.859408 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3186 17:16:26.866440 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3187 17:16:26.869502 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3188 17:16:26.872833 1 0 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3189 17:16:26.879384 1 0 24 | B1->B0 | 2424 3030 | 0 0 | (0 0) (0 0)
3190 17:16:26.882550 1 0 28 | B1->B0 | 4040 4646 | 0 0 | (1 1) (0 0)
3191 17:16:26.886277 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3192 17:16:26.892578 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3193 17:16:26.896331 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3194 17:16:26.899141 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3195 17:16:26.902981 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3196 17:16:26.906071
3197 17:16:26.909319 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3198 17:16:26.912438 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3199 17:16:26.915822 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
3200 17:16:26.918977
3201 17:16:26.922325 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3202 17:16:26.925613 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3203 17:16:26.929507 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3204 17:16:26.932605
3205 17:16:26.935911 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3206 17:16:26.939010 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3207 17:16:26.942358 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3208 17:16:26.945625
3209 17:16:26.948849 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3210 17:16:26.951985 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3211 17:16:26.955349 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3212 17:16:26.958576
3213 17:16:26.961957 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3214 17:16:26.965039 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3215 17:16:26.972189 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3216 17:16:26.975446 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3217 17:16:26.978531 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3218 17:16:26.981950 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3219 17:16:26.985103
3220 17:16:26.988264 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3221 17:16:26.991497 Total UI for P1: 0, mck2ui 16
3222 17:16:26.995278 best dqsien dly found for B0: ( 1, 3, 24)
3223 17:16:26.998425 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3224 17:16:27.001683 Total UI for P1: 0, mck2ui 16
3225 17:16:27.005047 best dqsien dly found for B1: ( 1, 3, 28)
3226 17:16:27.008268 best DQS0 dly(MCK, UI, PI) = (1, 3, 24)
3227 17:16:27.011477 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3228 17:16:27.011566
3229 17:16:27.014636 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 24)
3230 17:16:27.021156 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3231 17:16:27.021283 [Gating] SW calibration Done
3232 17:16:27.021378 ==
3233 17:16:27.025036 Dram Type= 6, Freq= 0, CH_1, rank 0
3234 17:16:27.031648 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3235 17:16:27.031749 ==
3236 17:16:27.031834 RX Vref Scan: 0
3237 17:16:27.031900
3238 17:16:27.034890 RX Vref 0 -> 0, step: 1
3239 17:16:27.034987
3240 17:16:27.038169 RX Delay -40 -> 252, step: 8
3241 17:16:27.041351 iDelay=200, Bit 0, Center 123 (48 ~ 199) 152
3242 17:16:27.044607 iDelay=200, Bit 1, Center 111 (40 ~ 183) 144
3243 17:16:27.047832 iDelay=200, Bit 2, Center 107 (40 ~ 175) 136
3244 17:16:27.054852 iDelay=200, Bit 3, Center 115 (40 ~ 191) 152
3245 17:16:27.057956 iDelay=200, Bit 4, Center 111 (40 ~ 183) 144
3246 17:16:27.061416 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3247 17:16:27.064596 iDelay=200, Bit 6, Center 123 (48 ~ 199) 152
3248 17:16:27.067797 iDelay=200, Bit 7, Center 111 (40 ~ 183) 144
3249 17:16:27.074328 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3250 17:16:27.077521 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3251 17:16:27.080828 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3252 17:16:27.084124 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3253 17:16:27.087212 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3254 17:16:27.090409
3255 17:16:27.093652 iDelay=200, Bit 13, Center 123 (56 ~ 191) 136
3256 17:16:27.097545 iDelay=200, Bit 14, Center 119 (48 ~ 191) 144
3257 17:16:27.100670 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3258 17:16:27.100764 ==
3259 17:16:27.104012 Dram Type= 6, Freq= 0, CH_1, rank 0
3260 17:16:27.110249 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3261 17:16:27.110360 ==
3262 17:16:27.110440 DQS Delay:
3263 17:16:27.110505 DQS0 = 0, DQS1 = 0
3264 17:16:27.113955 DQM Delay:
3265 17:16:27.114038 DQM0 = 116, DQM1 = 113
3266 17:16:27.117071 DQ Delay:
3267 17:16:27.120374 DQ0 =123, DQ1 =111, DQ2 =107, DQ3 =115
3268 17:16:27.123687 DQ4 =111, DQ5 =127, DQ6 =123, DQ7 =111
3269 17:16:27.126905 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3270 17:16:27.130003 DQ12 =123, DQ13 =123, DQ14 =119, DQ15 =119
3271 17:16:27.130091
3272 17:16:27.130164
3273 17:16:27.130234 ==
3274 17:16:27.133391 Dram Type= 6, Freq= 0, CH_1, rank 0
3275 17:16:27.137201 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3276 17:16:27.140492 ==
3277 17:16:27.140580
3278 17:16:27.140645
3279 17:16:27.140706 TX Vref Scan disable
3280 17:16:27.143046 == TX Byte 0 ==
3281 17:16:27.147043 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3282 17:16:27.150208 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3283 17:16:27.153615 == TX Byte 1 ==
3284 17:16:27.156840 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3285 17:16:27.159989 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3286 17:16:27.163340 ==
3287 17:16:27.163425 Dram Type= 6, Freq= 0, CH_1, rank 0
3288 17:16:27.169724 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3289 17:16:27.169826 ==
3290 17:16:27.180514 TX Vref=22, minBit 9, minWin=23, winSum=412
3291 17:16:27.183919 TX Vref=24, minBit 8, minWin=24, winSum=416
3292 17:16:27.187744 TX Vref=26, minBit 8, minWin=25, winSum=419
3293 17:16:27.190666 TX Vref=28, minBit 8, minWin=25, winSum=423
3294 17:16:27.193939 TX Vref=30, minBit 8, minWin=25, winSum=424
3295 17:16:27.200999 TX Vref=32, minBit 8, minWin=25, winSum=423
3296 17:16:27.204269 [TxChooseVref] Worse bit 8, Min win 25, Win sum 424, Final Vref 30
3297 17:16:27.204364
3298 17:16:27.207449 Final TX Range 1 Vref 30
3299 17:16:27.207533
3300 17:16:27.207600 ==
3301 17:16:27.210569 Dram Type= 6, Freq= 0, CH_1, rank 0
3302 17:16:27.213969 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3303 17:16:27.216923 ==
3304 17:16:27.217004
3305 17:16:27.217070
3306 17:16:27.217132 TX Vref Scan disable
3307 17:16:27.220696 == TX Byte 0 ==
3308 17:16:27.224066 Update DQ dly =841 (3 ,1, 41) DQ OEN =(2 ,6)
3309 17:16:27.230664 Update DQM dly =841 (3 ,1, 41) DQM OEN =(2 ,6)
3310 17:16:27.230747 == TX Byte 1 ==
3311 17:16:27.233402 Update DQ dly =843 (3 ,2, 11) DQ OEN =(2 ,7)
3312 17:16:27.240462 Update DQM dly =843 (3 ,2, 11) DQM OEN =(2 ,7)
3313 17:16:27.240550
3314 17:16:27.240617 [DATLAT]
3315 17:16:27.240680 Freq=1200, CH1 RK0
3316 17:16:27.240741
3317 17:16:27.243706 DATLAT Default: 0xd
3318 17:16:27.243787 0, 0xFFFF, sum = 0
3319 17:16:27.246979
3320 17:16:27.247064 1, 0xFFFF, sum = 0
3321 17:16:27.250069 2, 0xFFFF, sum = 0
3322 17:16:27.250148 3, 0xFFFF, sum = 0
3323 17:16:27.253310 4, 0xFFFF, sum = 0
3324 17:16:27.253391 5, 0xFFFF, sum = 0
3325 17:16:27.256658 6, 0xFFFF, sum = 0
3326 17:16:27.256743 7, 0xFFFF, sum = 0
3327 17:16:27.260475 8, 0xFFFF, sum = 0
3328 17:16:27.260561 9, 0xFFFF, sum = 0
3329 17:16:27.263555 10, 0xFFFF, sum = 0
3330 17:16:27.263640 11, 0xFFFF, sum = 0
3331 17:16:27.266372 12, 0x0, sum = 1
3332 17:16:27.266456 13, 0x0, sum = 2
3333 17:16:27.270119 14, 0x0, sum = 3
3334 17:16:27.270205 15, 0x0, sum = 4
3335 17:16:27.273337 best_step = 13
3336 17:16:27.273421
3337 17:16:27.273486 ==
3338 17:16:27.276590 Dram Type= 6, Freq= 0, CH_1, rank 0
3339 17:16:27.279731 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3340 17:16:27.279818 ==
3341 17:16:27.282902 RX Vref Scan: 1
3342 17:16:27.282986
3343 17:16:27.283052 Set Vref Range= 32 -> 127
3344 17:16:27.283113
3345 17:16:27.286250 RX Vref 32 -> 127, step: 1
3346 17:16:27.286333
3347 17:16:27.289352 RX Delay -13 -> 252, step: 4
3348 17:16:27.289441
3349 17:16:27.293048 Set Vref, RX VrefLevel [Byte0]: 32
3350 17:16:27.296219 [Byte1]: 32
3351 17:16:27.296305
3352 17:16:27.299483 Set Vref, RX VrefLevel [Byte0]: 33
3353 17:16:27.302743 [Byte1]: 33
3354 17:16:27.307233
3355 17:16:27.307404 Set Vref, RX VrefLevel [Byte0]: 34
3356 17:16:27.310357 [Byte1]: 34
3357 17:16:27.314936
3358 17:16:27.315074 Set Vref, RX VrefLevel [Byte0]: 35
3359 17:16:27.318120 [Byte1]: 35
3360 17:16:27.322757
3361 17:16:27.322924 Set Vref, RX VrefLevel [Byte0]: 36
3362 17:16:27.326029 [Byte1]: 36
3363 17:16:27.330652
3364 17:16:27.330792 Set Vref, RX VrefLevel [Byte0]: 37
3365 17:16:27.334004 [Byte1]: 37
3366 17:16:27.338565
3367 17:16:27.338656 Set Vref, RX VrefLevel [Byte0]: 38
3368 17:16:27.341733 [Byte1]: 38
3369 17:16:27.346392
3370 17:16:27.346559 Set Vref, RX VrefLevel [Byte0]: 39
3371 17:16:27.349737 [Byte1]: 39
3372 17:16:27.354282
3373 17:16:27.354419 Set Vref, RX VrefLevel [Byte0]: 40
3374 17:16:27.357179 [Byte1]: 40
3375 17:16:27.361984
3376 17:16:27.362139 Set Vref, RX VrefLevel [Byte0]: 41
3377 17:16:27.365183 [Byte1]: 41
3378 17:16:27.369765
3379 17:16:27.369854 Set Vref, RX VrefLevel [Byte0]: 42
3380 17:16:27.372996 [Byte1]: 42
3381 17:16:27.377610
3382 17:16:27.377684 Set Vref, RX VrefLevel [Byte0]: 43
3383 17:16:27.380831 [Byte1]: 43
3384 17:16:27.384010
3385 17:16:27.384086
3386 17:16:27.388001 Set Vref, RX VrefLevel [Byte0]: 44
3387 17:16:27.390672 [Byte1]: 44
3388 17:16:27.390749
3389 17:16:27.394040 Set Vref, RX VrefLevel [Byte0]: 45
3390 17:16:27.397406 [Byte1]: 45
3391 17:16:27.401201
3392 17:16:27.401276 Set Vref, RX VrefLevel [Byte0]: 46
3393 17:16:27.404545 [Byte1]: 46
3394 17:16:27.409831
3395 17:16:27.409911 Set Vref, RX VrefLevel [Byte0]: 47
3396 17:16:27.412485 [Byte1]: 47
3397 17:16:27.417642
3398 17:16:27.417734 Set Vref, RX VrefLevel [Byte0]: 48
3399 17:16:27.420296 [Byte1]: 48
3400 17:16:27.425466
3401 17:16:27.425541 Set Vref, RX VrefLevel [Byte0]: 49
3402 17:16:27.428732 [Byte1]: 49
3403 17:16:27.433412
3404 17:16:27.433487 Set Vref, RX VrefLevel [Byte0]: 50
3405 17:16:27.436106 [Byte1]: 50
3406 17:16:27.440679
3407 17:16:27.440754 Set Vref, RX VrefLevel [Byte0]: 51
3408 17:16:27.444546 [Byte1]: 51
3409 17:16:27.449015
3410 17:16:27.449091 Set Vref, RX VrefLevel [Byte0]: 52
3411 17:16:27.452434 [Byte1]: 52
3412 17:16:27.456477
3413 17:16:27.456554 Set Vref, RX VrefLevel [Byte0]: 53
3414 17:16:27.460445 [Byte1]: 53
3415 17:16:27.464489
3416 17:16:27.464571 Set Vref, RX VrefLevel [Byte0]: 54
3417 17:16:27.467795 [Byte1]: 54
3418 17:16:27.472500
3419 17:16:27.472582 Set Vref, RX VrefLevel [Byte0]: 55
3420 17:16:27.475686 [Byte1]: 55
3421 17:16:27.480300
3422 17:16:27.483409 Set Vref, RX VrefLevel [Byte0]: 56
3423 17:16:27.483505 [Byte1]: 56
3424 17:16:27.486666
3425 17:16:27.486748
3426 17:16:27.490078 Set Vref, RX VrefLevel [Byte0]: 57
3427 17:16:27.493284 [Byte1]: 57
3428 17:16:27.493368
3429 17:16:27.496520 Set Vref, RX VrefLevel [Byte0]: 58
3430 17:16:27.499635 [Byte1]: 58
3431 17:16:27.504241
3432 17:16:27.504323 Set Vref, RX VrefLevel [Byte0]: 59
3433 17:16:27.507502 [Byte1]: 59
3434 17:16:27.512048
3435 17:16:27.512130 Set Vref, RX VrefLevel [Byte0]: 60
3436 17:16:27.514750 [Byte1]: 60
3437 17:16:27.520035
3438 17:16:27.520119 Set Vref, RX VrefLevel [Byte0]: 61
3439 17:16:27.523288 [Byte1]: 61
3440 17:16:27.527244
3441 17:16:27.527326 Set Vref, RX VrefLevel [Byte0]: 62
3442 17:16:27.531161 [Byte1]: 62
3443 17:16:27.535690
3444 17:16:27.535772 Set Vref, RX VrefLevel [Byte0]: 63
3445 17:16:27.539073 [Byte1]: 63
3446 17:16:27.543630
3447 17:16:27.543738 Set Vref, RX VrefLevel [Byte0]: 64
3448 17:16:27.546821 [Byte1]: 64
3449 17:16:27.551427
3450 17:16:27.551509 Set Vref, RX VrefLevel [Byte0]: 65
3451 17:16:27.554800 [Byte1]: 65
3452 17:16:27.559430
3453 17:16:27.559513 Final RX Vref Byte 0 = 53 to rank0
3454 17:16:27.562029 Final RX Vref Byte 1 = 53 to rank0
3455 17:16:27.565425 Final RX Vref Byte 0 = 53 to rank1
3456 17:16:27.568765 Final RX Vref Byte 1 = 53 to rank1==
3457 17:16:27.572158 Dram Type= 6, Freq= 0, CH_1, rank 0
3458 17:16:27.578611 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3459 17:16:27.578701 ==
3460 17:16:27.578766 DQS Delay:
3461 17:16:27.581900 DQS0 = 0, DQS1 = 0
3462 17:16:27.581982 DQM Delay:
3463 17:16:27.585107 DQM0 = 114, DQM1 = 113
3464 17:16:27.585189 DQ Delay:
3465 17:16:27.588315 DQ0 =120, DQ1 =110, DQ2 =106, DQ3 =114
3466 17:16:27.591683 DQ4 =110, DQ5 =122, DQ6 =126, DQ7 =110
3467 17:16:27.594959 DQ8 =100, DQ9 =104, DQ10 =114, DQ11 =106
3468 17:16:27.598201 DQ12 =122, DQ13 =120, DQ14 =120, DQ15 =120
3469 17:16:27.598285
3470 17:16:27.598352
3471 17:16:27.608496 [DQSOSCAuto] RK0, (LSB)MR18= 0xf0fd, (MSB)MR19= 0x303, tDQSOscB0 = 411 ps tDQSOscB1 = 416 ps
3472 17:16:27.608581 CH1 RK0: MR19=303, MR18=F0FD
3473 17:16:27.611192
3474 17:16:27.615024 CH1_RK0: MR19=0x303, MR18=0xF0FD, DQSOSC=411, MR23=63, INC=38, DEC=25
3475 17:16:27.615099
3476 17:16:27.618349 ----->DramcWriteLeveling(PI) begin...
3477 17:16:27.621029 ==
3478 17:16:27.624796 Dram Type= 6, Freq= 0, CH_1, rank 1
3479 17:16:27.627991 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3480 17:16:27.628072 ==
3481 17:16:27.631142 Write leveling (Byte 0): 25 => 25
3482 17:16:27.634493 Write leveling (Byte 1): 27 => 27
3483 17:16:27.637771 DramcWriteLeveling(PI) end<-----
3484 17:16:27.637843
3485 17:16:27.637906 ==
3486 17:16:27.641060 Dram Type= 6, Freq= 0, CH_1, rank 1
3487 17:16:27.644322 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3488 17:16:27.644400 ==
3489 17:16:27.647471 [Gating] SW mode calibration
3490 17:16:27.654118 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 26 , u4TDQSCK_UI_min 3, 1:4ExtraMCK 0
3491 17:16:27.660605 RX_Path_delay_UI(47) -3 - DQSINCTL_UI(32) = u1StartUI(15)
3492 17:16:27.663994 0 15 0 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
3493 17:16:27.667305 0 15 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3494 17:16:27.674040 0 15 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3495 17:16:27.677299 0 15 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3496 17:16:27.680583 0 15 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
3497 17:16:27.687040 0 15 20 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 1)
3498 17:16:27.690311 0 15 24 | B1->B0 | 3434 2424 | 1 0 | (1 1) (0 0)
3499 17:16:27.693556 0 15 28 | B1->B0 | 2e2e 2323 | 1 0 | (1 0) (0 0)
3500 17:16:27.700108 1 0 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3501 17:16:27.703857 1 0 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3502 17:16:27.707197 1 0 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3503 17:16:27.713967 1 0 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3504 17:16:27.717210 1 0 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
3505 17:16:27.720465 1 0 20 | B1->B0 | 2323 2e2e | 0 0 | (0 0) (0 0)
3506 17:16:27.726893 1 0 24 | B1->B0 | 2323 4545 | 0 0 | (0 0) (0 0)
3507 17:16:27.730148 1 0 28 | B1->B0 | 3b3b 4646 | 0 0 | (1 1) (0 0)
3508 17:16:27.733572 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3509 17:16:27.740271 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3510 17:16:27.743650 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3511 17:16:27.746817 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3512 17:16:27.753318 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3513 17:16:27.756621 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3514 17:16:27.759941 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
3515 17:16:27.766268 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
3516 17:16:27.769556 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3517 17:16:27.772738 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3518 17:16:27.779408 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3519 17:16:27.782643 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3520 17:16:27.785828 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3521 17:16:27.792364 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3522 17:16:27.795652 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3523 17:16:27.799000 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3524 17:16:27.805986 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3525 17:16:27.808689 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3526 17:16:27.812111 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3527 17:16:27.818685 1 3 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3528 17:16:27.821895 1 3 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
3529 17:16:27.825151 1 3 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3530 17:16:27.832126 1 3 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
3531 17:16:27.835494 1 3 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
3532 17:16:27.838175 Total UI for P1: 0, mck2ui 16
3533 17:16:27.841515 best dqsien dly found for B0: ( 1, 3, 22)
3534 17:16:27.844834 1 4 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
3535 17:16:27.848037 Total UI for P1: 0, mck2ui 16
3536 17:16:27.851329 best dqsien dly found for B1: ( 1, 3, 28)
3537 17:16:27.854569 best DQS0 dly(MCK, UI, PI) = (1, 3, 22)
3538 17:16:27.861088 best DQS1 dly(MCK, UI, PI) = (1, 3, 28)
3539 17:16:27.861172
3540 17:16:27.865050 best DQS0 P1 dly(MCK, UI, PI) = (1, 7, 22)
3541 17:16:27.867643 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 28)
3542 17:16:27.871030 [Gating] SW calibration Done
3543 17:16:27.871113 ==
3544 17:16:27.874445 Dram Type= 6, Freq= 0, CH_1, rank 1
3545 17:16:27.877723 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3546 17:16:27.877820 ==
3547 17:16:27.881056 RX Vref Scan: 0
3548 17:16:27.881138
3549 17:16:27.881204 RX Vref 0 -> 0, step: 1
3550 17:16:27.881265
3551 17:16:27.884402 RX Delay -40 -> 252, step: 8
3552 17:16:27.887517 iDelay=200, Bit 0, Center 119 (48 ~ 191) 144
3553 17:16:27.893930 iDelay=200, Bit 1, Center 115 (40 ~ 191) 152
3554 17:16:27.897147 iDelay=200, Bit 2, Center 103 (32 ~ 175) 144
3555 17:16:27.900380 iDelay=200, Bit 3, Center 111 (40 ~ 183) 144
3556 17:16:27.903617 iDelay=200, Bit 4, Center 115 (40 ~ 191) 152
3557 17:16:27.907437 iDelay=200, Bit 5, Center 127 (56 ~ 199) 144
3558 17:16:27.913935 iDelay=200, Bit 6, Center 119 (48 ~ 191) 144
3559 17:16:27.917232 iDelay=200, Bit 7, Center 115 (40 ~ 191) 152
3560 17:16:27.920524 iDelay=200, Bit 8, Center 99 (32 ~ 167) 136
3561 17:16:27.923906 iDelay=200, Bit 9, Center 103 (32 ~ 175) 144
3562 17:16:27.927039 iDelay=200, Bit 10, Center 111 (40 ~ 183) 144
3563 17:16:27.933420 iDelay=200, Bit 11, Center 107 (40 ~ 175) 136
3564 17:16:27.936596 iDelay=200, Bit 12, Center 123 (56 ~ 191) 136
3565 17:16:27.939991 iDelay=200, Bit 13, Center 119 (48 ~ 191) 144
3566 17:16:27.943317 iDelay=200, Bit 14, Center 115 (48 ~ 183) 136
3567 17:16:27.949865 iDelay=200, Bit 15, Center 119 (48 ~ 191) 144
3568 17:16:27.949953 ==
3569 17:16:27.953116 Dram Type= 6, Freq= 0, CH_1, rank 1
3570 17:16:27.956495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3571 17:16:27.956576 ==
3572 17:16:27.956644 DQS Delay:
3573 17:16:27.959686 DQS0 = 0, DQS1 = 0
3574 17:16:27.959761 DQM Delay:
3575 17:16:27.963020 DQM0 = 115, DQM1 = 112
3576 17:16:27.963100 DQ Delay:
3577 17:16:27.966345 DQ0 =119, DQ1 =115, DQ2 =103, DQ3 =111
3578 17:16:27.969624 DQ4 =115, DQ5 =127, DQ6 =119, DQ7 =115
3579 17:16:27.972882 DQ8 =99, DQ9 =103, DQ10 =111, DQ11 =107
3580 17:16:27.979500 DQ12 =123, DQ13 =119, DQ14 =115, DQ15 =119
3581 17:16:27.979582
3582 17:16:27.979647
3583 17:16:27.979712 ==
3584 17:16:27.982952 Dram Type= 6, Freq= 0, CH_1, rank 1
3585 17:16:27.985518 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3586 17:16:27.985594 ==
3587 17:16:27.985690
3588 17:16:27.985751
3589 17:16:27.989440 TX Vref Scan disable
3590 17:16:27.989514 == TX Byte 0 ==
3591 17:16:27.995518 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3592 17:16:27.998800 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3593 17:16:27.998887 == TX Byte 1 ==
3594 17:16:28.005437 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3595 17:16:28.008632 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3596 17:16:28.008713 ==
3597 17:16:28.011945 Dram Type= 6, Freq= 0, CH_1, rank 1
3598 17:16:28.015053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3599 17:16:28.015129 ==
3600 17:16:28.028211 TX Vref=22, minBit 8, minWin=24, winSum=417
3601 17:16:28.031447 TX Vref=24, minBit 9, minWin=24, winSum=422
3602 17:16:28.034543 TX Vref=26, minBit 9, minWin=24, winSum=423
3603 17:16:28.038031 TX Vref=28, minBit 9, minWin=25, winSum=424
3604 17:16:28.041423 TX Vref=30, minBit 9, minWin=25, winSum=429
3605 17:16:28.048142 TX Vref=32, minBit 9, minWin=25, winSum=426
3606 17:16:28.051531 [TxChooseVref] Worse bit 9, Min win 25, Win sum 429, Final Vref 30
3607 17:16:28.051614
3608 17:16:28.054816 Final TX Range 1 Vref 30
3609 17:16:28.054922
3610 17:16:28.054987 ==
3611 17:16:28.058204 Dram Type= 6, Freq= 0, CH_1, rank 1
3612 17:16:28.060798 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3613 17:16:28.064028
3614 17:16:28.064108 ==
3615 17:16:28.064173
3616 17:16:28.064236
3617 17:16:28.064296 TX Vref Scan disable
3618 17:16:28.068104 == TX Byte 0 ==
3619 17:16:28.071513 Update DQ dly =842 (3 ,2, 10) DQ OEN =(2 ,7)
3620 17:16:28.078083 Update DQM dly =842 (3 ,2, 10) DQM OEN =(2 ,7)
3621 17:16:28.078164 == TX Byte 1 ==
3622 17:16:28.081279 Update DQ dly =844 (3 ,2, 12) DQ OEN =(2 ,7)
3623 17:16:28.088087 Update DQM dly =844 (3 ,2, 12) DQM OEN =(2 ,7)
3624 17:16:28.088191
3625 17:16:28.088257 [DATLAT]
3626 17:16:28.088329 Freq=1200, CH1 RK1
3627 17:16:28.088416
3628 17:16:28.090609 DATLAT Default: 0xd
3629 17:16:28.093905 0, 0xFFFF, sum = 0
3630 17:16:28.093992 1, 0xFFFF, sum = 0
3631 17:16:28.097288 2, 0xFFFF, sum = 0
3632 17:16:28.097362 3, 0xFFFF, sum = 0
3633 17:16:28.100485 4, 0xFFFF, sum = 0
3634 17:16:28.100563 5, 0xFFFF, sum = 0
3635 17:16:28.103762 6, 0xFFFF, sum = 0
3636 17:16:28.103840 7, 0xFFFF, sum = 0
3637 17:16:28.107107 8, 0xFFFF, sum = 0
3638 17:16:28.107182 9, 0xFFFF, sum = 0
3639 17:16:28.110387 10, 0xFFFF, sum = 0
3640 17:16:28.110466 11, 0xFFFF, sum = 0
3641 17:16:28.113626 12, 0x0, sum = 1
3642 17:16:28.113698 13, 0x0, sum = 2
3643 17:16:28.116949 14, 0x0, sum = 3
3644 17:16:28.117027 15, 0x0, sum = 4
3645 17:16:28.120157 best_step = 13
3646 17:16:28.120245
3647 17:16:28.120308 ==
3648 17:16:28.123493 Dram Type= 6, Freq= 0, CH_1, rank 1
3649 17:16:28.126746 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3650 17:16:28.126826 ==
3651 17:16:28.130087 RX Vref Scan: 0
3652 17:16:28.130175
3653 17:16:28.130244 RX Vref 0 -> 0, step: 1
3654 17:16:28.130306
3655 17:16:28.133299 RX Delay -13 -> 252, step: 4
3656 17:16:28.140523 iDelay=191, Bit 0, Center 116 (47 ~ 186) 140
3657 17:16:28.143776 iDelay=191, Bit 1, Center 112 (43 ~ 182) 140
3658 17:16:28.146502 iDelay=191, Bit 2, Center 106 (39 ~ 174) 136
3659 17:16:28.150473 iDelay=191, Bit 3, Center 112 (47 ~ 178) 132
3660 17:16:28.156441 iDelay=191, Bit 4, Center 116 (47 ~ 186) 140
3661 17:16:28.159710 iDelay=191, Bit 5, Center 122 (55 ~ 190) 136
3662 17:16:28.163018 iDelay=191, Bit 6, Center 122 (55 ~ 190) 136
3663 17:16:28.166183 iDelay=191, Bit 7, Center 112 (43 ~ 182) 140
3664 17:16:28.169466 iDelay=191, Bit 8, Center 100 (39 ~ 162) 124
3665 17:16:28.176059 iDelay=191, Bit 9, Center 102 (39 ~ 166) 128
3666 17:16:28.179509 iDelay=191, Bit 10, Center 114 (51 ~ 178) 128
3667 17:16:28.182714 iDelay=191, Bit 11, Center 106 (43 ~ 170) 128
3668 17:16:28.185978 iDelay=191, Bit 12, Center 122 (59 ~ 186) 128
3669 17:16:28.192510 iDelay=191, Bit 13, Center 118 (55 ~ 182) 128
3670 17:16:28.195764 iDelay=191, Bit 14, Center 118 (55 ~ 182) 128
3671 17:16:28.198977 iDelay=191, Bit 15, Center 122 (59 ~ 186) 128
3672 17:16:28.199060 ==
3673 17:16:28.202187 Dram Type= 6, Freq= 0, CH_1, rank 1
3674 17:16:28.205600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3675 17:16:28.205681 ==
3676 17:16:28.208799 DQS Delay:
3677 17:16:28.208876 DQS0 = 0, DQS1 = 0
3678 17:16:28.212011 DQM Delay:
3679 17:16:28.212089 DQM0 = 114, DQM1 = 112
3680 17:16:28.212152 DQ Delay:
3681 17:16:28.215934
3682 17:16:28.218573 DQ0 =116, DQ1 =112, DQ2 =106, DQ3 =112
3683 17:16:28.221803 DQ4 =116, DQ5 =122, DQ6 =122, DQ7 =112
3684 17:16:28.225778 DQ8 =100, DQ9 =102, DQ10 =114, DQ11 =106
3685 17:16:28.229038 DQ12 =122, DQ13 =118, DQ14 =118, DQ15 =122
3686 17:16:28.229115
3687 17:16:28.229178
3688 17:16:28.235497 [DQSOSCAuto] RK1, (LSB)MR18= 0xf507, (MSB)MR19= 0x304, tDQSOscB0 = 407 ps tDQSOscB1 = 414 ps
3689 17:16:28.238696 CH1 RK1: MR19=304, MR18=F507
3690 17:16:28.245490 CH1_RK1: MR19=0x304, MR18=0xF507, DQSOSC=407, MR23=63, INC=39, DEC=26
3691 17:16:28.248681 [RxdqsGatingPostProcess] freq 1200
3692 17:16:28.254690 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
3693 17:16:28.258027 best DQS0 dly(2T, 0.5T) = (0, 11)
3694 17:16:28.261291 best DQS1 dly(2T, 0.5T) = (0, 11)
3695 17:16:28.264613 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3696 17:16:28.267870 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3697 17:16:28.267952 best DQS0 dly(2T, 0.5T) = (0, 11)
3698 17:16:28.271163 best DQS1 dly(2T, 0.5T) = (0, 11)
3699 17:16:28.275199 best DQS0 P1 dly(2T, 0.5T) = (0, 15)
3700 17:16:28.277828 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
3701 17:16:28.281032 Pre-setting of DQS Precalculation
3702 17:16:28.287619 [DualRankRxdatlatCal] RK0: 13, RK1: 13, Final_Datlat 13
3703 17:16:28.294737 sync_frequency_calibration_params sync calibration params of frequency 1200 to shu:2
3704 17:16:28.301431 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
3705 17:16:28.301527
3706 17:16:28.301595
3707 17:16:28.304599 [Calibration Summary] 2400 Mbps
3708 17:16:28.307899 CH 0, Rank 0
3709 17:16:28.307975 SW Impedance : PASS
3710 17:16:28.311211 DUTY Scan : NO K
3711 17:16:28.311287 ZQ Calibration : PASS
3712 17:16:28.314401
3713 17:16:28.314479 Jitter Meter : NO K
3714 17:16:28.317641 CBT Training : PASS
3715 17:16:28.317718 Write leveling : PASS
3716 17:16:28.320770 RX DQS gating : PASS
3717 17:16:28.324143 RX DQ/DQS(RDDQC) : PASS
3718 17:16:28.324221 TX DQ/DQS : PASS
3719 17:16:28.327568 RX DATLAT : PASS
3720 17:16:28.330328 RX DQ/DQS(Engine): PASS
3721 17:16:28.330407 TX OE : NO K
3722 17:16:28.333587 All Pass.
3723 17:16:28.333664
3724 17:16:28.333727 CH 0, Rank 1
3725 17:16:28.337473 SW Impedance : PASS
3726 17:16:28.337549 DUTY Scan : NO K
3727 17:16:28.340646 ZQ Calibration : PASS
3728 17:16:28.344117 Jitter Meter : NO K
3729 17:16:28.344197 CBT Training : PASS
3730 17:16:28.346762 Write leveling : PASS
3731 17:16:28.350147 RX DQS gating : PASS
3732 17:16:28.350221 RX DQ/DQS(RDDQC) : PASS
3733 17:16:28.353376 TX DQ/DQS : PASS
3734 17:16:28.356710 RX DATLAT : PASS
3735 17:16:28.356811 RX DQ/DQS(Engine): PASS
3736 17:16:28.359968 TX OE : NO K
3737 17:16:28.360043 All Pass.
3738 17:16:28.360110
3739 17:16:28.363239 CH 1, Rank 0
3740 17:16:28.363313 SW Impedance : PASS
3741 17:16:28.366511 DUTY Scan : NO K
3742 17:16:28.369886 ZQ Calibration : PASS
3743 17:16:28.369962 Jitter Meter : NO K
3744 17:16:28.373085 CBT Training : PASS
3745 17:16:28.376473 Write leveling : PASS
3746 17:16:28.376548 RX DQS gating : PASS
3747 17:16:28.379796 RX DQ/DQS(RDDQC) : PASS
3748 17:16:28.383118 TX DQ/DQS : PASS
3749 17:16:28.383198 RX DATLAT : PASS
3750 17:16:28.386404 RX DQ/DQS(Engine): PASS
3751 17:16:28.389720 TX OE : NO K
3752 17:16:28.389798 All Pass.
3753 17:16:28.389864
3754 17:16:28.389925 CH 1, Rank 1
3755 17:16:28.393099 SW Impedance : PASS
3756 17:16:28.396349 DUTY Scan : NO K
3757 17:16:28.396431 ZQ Calibration : PASS
3758 17:16:28.399613 Jitter Meter : NO K
3759 17:16:28.402860 CBT Training : PASS
3760 17:16:28.402966 Write leveling : PASS
3761 17:16:28.406300 RX DQS gating : PASS
3762 17:16:28.409599 RX DQ/DQS(RDDQC) : PASS
3763 17:16:28.409687 TX DQ/DQS : PASS
3764 17:16:28.412794 RX DATLAT : PASS
3765 17:16:28.412869 RX DQ/DQS(Engine): PASS
3766 17:16:28.415933
3767 17:16:28.416009 TX OE : NO K
3768 17:16:28.416072 All Pass.
3769 17:16:28.416131
3770 17:16:28.419264
3771 17:16:28.419342 DramC Write-DBI off
3772 17:16:28.422609 PER_BANK_REFRESH: Hybrid Mode
3773 17:16:28.422738 TX_TRACKING: ON
3774 17:16:28.432373 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 72, TRFC_05T 1, TXREFCNT 87, TRFCpb 30, TRFCpb_05T 1
3775 17:16:28.435675 [FAST_K] Save calibration result to emmc
3776 17:16:28.439024 dramc_set_vcore_voltage set vcore to 650000
3777 17:16:28.442296 Read voltage for 600, 5
3778 17:16:28.442380 Vio18 = 0
3779 17:16:28.445529 Vcore = 650000
3780 17:16:28.445612 Vdram = 0
3781 17:16:28.445677 Vddq = 0
3782 17:16:28.448676 Vmddr = 0
3783 17:16:28.452146 [FAST_K] DramcSave_Time_For_Cal_Init SHU4, femmc_Ready=0
3784 17:16:28.458763 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
3785 17:16:28.458854 MEM_TYPE=3, freq_sel=19
3786 17:16:28.462070 sv_algorithm_assistance_LP4_1600
3787 17:16:28.468710 ============ PULL DRAM RESETB DOWN ============
3788 17:16:28.471345 ========== PULL DRAM RESETB DOWN end =========
3789 17:16:28.474632 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3790 17:16:28.478551 ===================================
3791 17:16:28.481675 LPDDR4 DRAM CONFIGURATION
3792 17:16:28.484395 ===================================
3793 17:16:28.487723 EX_ROW_EN[0] = 0x0
3794 17:16:28.487807 EX_ROW_EN[1] = 0x0
3795 17:16:28.491103 LP4Y_EN = 0x0
3796 17:16:28.491235 WORK_FSP = 0x0
3797 17:16:28.494361 WL = 0x2
3798 17:16:28.494445 RL = 0x2
3799 17:16:28.497625 BL = 0x2
3800 17:16:28.497710 RPST = 0x0
3801 17:16:28.500986 RD_PRE = 0x0
3802 17:16:28.501070 WR_PRE = 0x1
3803 17:16:28.504259 WR_PST = 0x0
3804 17:16:28.504342 DBI_WR = 0x0
3805 17:16:28.507581 DBI_RD = 0x0
3806 17:16:28.507675 OTF = 0x1
3807 17:16:28.510848
3808 17:16:28.510969 ===================================
3809 17:16:28.514152
3810 17:16:28.514227 ===================================
3811 17:16:28.517416
3812 17:16:28.517492 ANA top config
3813 17:16:28.520605 ===================================
3814 17:16:28.523877 DLL_ASYNC_EN = 0
3815 17:16:28.523967 ALL_SLAVE_EN = 1
3816 17:16:28.527093
3817 17:16:28.527169 NEW_RANK_MODE = 1
3818 17:16:28.530511 DLL_IDLE_MODE = 1
3819 17:16:28.533613 LP45_APHY_COMB_EN = 1
3820 17:16:28.536995 TX_ODT_DIS = 1
3821 17:16:28.537075 NEW_8X_MODE = 1
3822 17:16:28.540233 ===================================
3823 17:16:28.543514 ===================================
3824 17:16:28.547403 data_rate = 1200
3825 17:16:28.550044 CKR = 1
3826 17:16:28.553439 DQ_P2S_RATIO = 8
3827 17:16:28.556724 ===================================
3828 17:16:28.560060 CA_P2S_RATIO = 8
3829 17:16:28.563424 DQ_CA_OPEN = 0
3830 17:16:28.566736 DQ_SEMI_OPEN = 0
3831 17:16:28.566812 CA_SEMI_OPEN = 0
3832 17:16:28.570127 CA_FULL_RATE = 0
3833 17:16:28.573520 DQ_CKDIV4_EN = 1
3834 17:16:28.576960 CA_CKDIV4_EN = 1
3835 17:16:28.580076 CA_PREDIV_EN = 0
3836 17:16:28.583459 PH8_DLY = 0
3837 17:16:28.583541 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
3838 17:16:28.586675 DQ_AAMCK_DIV = 4
3839 17:16:28.589991 CA_AAMCK_DIV = 4
3840 17:16:28.592710 CA_ADMCK_DIV = 4
3841 17:16:28.596217 DQ_TRACK_CA_EN = 0
3842 17:16:28.599512 CA_PICK = 600
3843 17:16:28.602636 CA_MCKIO = 600
3844 17:16:28.602717 MCKIO_SEMI = 0
3845 17:16:28.606493 PLL_FREQ = 2288
3846 17:16:28.609346 DQ_UI_PI_RATIO = 32
3847 17:16:28.612553 CA_UI_PI_RATIO = 0
3848 17:16:28.615864 ===================================
3849 17:16:28.619221 ===================================
3850 17:16:28.622456 memory_type:LPDDR4
3851 17:16:28.622540 GP_NUM : 10
3852 17:16:28.625729 SRAM_EN : 1
3853 17:16:28.629063 MD32_EN : 0
3854 17:16:28.632498 ===================================
3855 17:16:28.632593 [ANA_INIT] >>>>>>>>>>>>>>
3856 17:16:28.635731 <<<<<< [CONFIGURE PHASE]: ANA_TX
3857 17:16:28.639118 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
3858 17:16:28.642223 ===================================
3859 17:16:28.645486 data_rate = 1200,PCW = 0X5800
3860 17:16:28.648608 ===================================
3861 17:16:28.651972 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
3862 17:16:28.658662 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3863 17:16:28.665441 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
3864 17:16:28.668128 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
3865 17:16:28.671961 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
3866 17:16:28.675223 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
3867 17:16:28.678518 [ANA_INIT] flow start
3868 17:16:28.678604 [ANA_INIT] PLL >>>>>>>>
3869 17:16:28.681772 [ANA_INIT] PLL <<<<<<<<
3870 17:16:28.685077 [ANA_INIT] MIDPI >>>>>>>>
3871 17:16:28.685179 [ANA_INIT] MIDPI <<<<<<<<
3872 17:16:28.688437
3873 17:16:28.688539 [ANA_INIT] DLL >>>>>>>>
3874 17:16:28.691136 [ANA_INIT] flow end
3875 17:16:28.694562 ============ LP4 DIFF to SE enter ============
3876 17:16:28.697862 ============ LP4 DIFF to SE exit ============
3877 17:16:28.701211 [ANA_INIT] <<<<<<<<<<<<<
3878 17:16:28.704321 [Flow] Enable top DCM control >>>>>
3879 17:16:28.707587 [Flow] Enable top DCM control <<<<<
3880 17:16:28.710958 Enable DLL master slave shuffle
3881 17:16:28.717567 ==============================================================
3882 17:16:28.717655 Gating Mode config
3883 17:16:28.724052 ==============================================================
3884 17:16:28.724141 Config description:
3885 17:16:28.733756 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
3886 17:16:28.740443 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
3887 17:16:28.747167 SELPH_MODE 0: By rank 1: By Phase
3888 17:16:28.750517 ==============================================================
3889 17:16:28.753779 GAT_TRACK_EN = 1
3890 17:16:28.757071 RX_GATING_MODE = 2
3891 17:16:28.760382 RX_GATING_TRACK_MODE = 2
3892 17:16:28.763181 SELPH_MODE = 1
3893 17:16:28.766525 PICG_EARLY_EN = 1
3894 17:16:28.769823 VALID_LAT_VALUE = 1
3895 17:16:28.776539 ==============================================================
3896 17:16:28.779902 Enter into Gating configuration >>>>
3897 17:16:28.783185 Exit from Gating configuration <<<<
3898 17:16:28.786390 Enter into DVFS_PRE_config >>>>>
3899 17:16:28.796456 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
3900 17:16:28.799806 Exit from DVFS_PRE_config <<<<<
3901 17:16:28.802464 Enter into PICG configuration >>>>
3902 17:16:28.806436 Exit from PICG configuration <<<<
3903 17:16:28.809140 [RX_INPUT] configuration >>>>>
3904 17:16:28.812345 [RX_INPUT] configuration <<<<<
3905 17:16:28.815781 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
3906 17:16:28.822416 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
3907 17:16:28.828854 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
3908 17:16:28.835624 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
3909 17:16:28.842392 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
3910 17:16:28.845584 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
3911 17:16:28.852006 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
3912 17:16:28.855223 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
3913 17:16:28.858615 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
3914 17:16:28.862006 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
3915 17:16:28.868562 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
3916 17:16:28.871835 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3917 17:16:28.875155 ===================================
3918 17:16:28.878429 LPDDR4 DRAM CONFIGURATION
3919 17:16:28.881814 ===================================
3920 17:16:28.881896 EX_ROW_EN[0] = 0x0
3921 17:16:28.884482 EX_ROW_EN[1] = 0x0
3922 17:16:28.884574 LP4Y_EN = 0x0
3923 17:16:28.887711 WORK_FSP = 0x0
3924 17:16:28.891061 WL = 0x2
3925 17:16:28.891152 RL = 0x2
3926 17:16:28.894477 BL = 0x2
3927 17:16:28.894567 RPST = 0x0
3928 17:16:28.897726 RD_PRE = 0x0
3929 17:16:28.897810 WR_PRE = 0x1
3930 17:16:28.901006 WR_PST = 0x0
3931 17:16:28.901089 DBI_WR = 0x0
3932 17:16:28.904257 DBI_RD = 0x0
3933 17:16:28.904353 OTF = 0x1
3934 17:16:28.907366 ===================================
3935 17:16:28.910735 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
3936 17:16:28.917326 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
3937 17:16:28.920544 [ModeRegister RLWL Config] data_rate:1200-MR2_RLWL:2
3938 17:16:28.923799 ===================================
3939 17:16:28.927026 LPDDR4 DRAM CONFIGURATION
3940 17:16:28.930749 ===================================
3941 17:16:28.930837 EX_ROW_EN[0] = 0x10
3942 17:16:28.934005 EX_ROW_EN[1] = 0x0
3943 17:16:28.937390 LP4Y_EN = 0x0
3944 17:16:28.937477 WORK_FSP = 0x0
3945 17:16:28.940637 WL = 0x2
3946 17:16:28.940723 RL = 0x2
3947 17:16:28.944008 BL = 0x2
3948 17:16:28.944095 RPST = 0x0
3949 17:16:28.947021 RD_PRE = 0x0
3950 17:16:28.947124 WR_PRE = 0x1
3951 17:16:28.950360 WR_PST = 0x0
3952 17:16:28.950445 DBI_WR = 0x0
3953 17:16:28.953654 DBI_RD = 0x0
3954 17:16:28.953739 OTF = 0x1
3955 17:16:28.956922 ===================================
3956 17:16:28.963646 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
3957 17:16:28.968331 nWR fixed to 30
3958 17:16:28.971044 [ModeRegInit_LP4] CH0 RK0
3959 17:16:28.971129 [ModeRegInit_LP4] CH0 RK1
3960 17:16:28.974940 [ModeRegInit_LP4] CH1 RK0
3961 17:16:28.977573 [ModeRegInit_LP4] CH1 RK1
3962 17:16:28.977658 match AC timing 17
3963 17:16:28.984425 dramType 5, freq 600, readDBI 0, DivMode 1, cbtMode 1
3964 17:16:28.987597 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
3965 17:16:28.991013 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
3966 17:16:28.997714 [TX_path_calculate] data rate=1200, WL=8, DQS_TotalUI=17
3967 17:16:29.000412 [TX_path_calculate] DQS = (2,1) DQS_OE = (1,6)
3968 17:16:29.000501 ==
3969 17:16:29.004404 Dram Type= 6, Freq= 0, CH_0, rank 0
3970 17:16:29.007506 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3971 17:16:29.010726 ==
3972 17:16:29.013901 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
3973 17:16:29.020480 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
3974 17:16:29.023647 [CA 0] Center 36 (6~67) winsize 62
3975 17:16:29.026894 [CA 1] Center 36 (5~67) winsize 63
3976 17:16:29.030155 [CA 2] Center 34 (4~65) winsize 62
3977 17:16:29.033419 [CA 3] Center 34 (4~65) winsize 62
3978 17:16:29.036751 [CA 4] Center 33 (3~64) winsize 62
3979 17:16:29.040030 [CA 5] Center 33 (3~64) winsize 62
3980 17:16:29.040110
3981 17:16:29.043348 [CmdBusTrainingLP45] Vref(ca) range 1: 35
3982 17:16:29.043429
3983 17:16:29.046698 [CATrainingPosCal] consider 1 rank data
3984 17:16:29.050081 u2DelayCellTimex100 = 270/100 ps
3985 17:16:29.053224 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
3986 17:16:29.059780 CA1 delay=36 (5~67),Diff = 3 PI (28 cell)
3987 17:16:29.063244 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
3988 17:16:29.066484 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
3989 17:16:29.069834 CA4 delay=33 (3~64),Diff = 0 PI (0 cell)
3990 17:16:29.072546 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
3991 17:16:29.072628
3992 17:16:29.075866 CA PerBit enable=1, Macro0, CA PI delay=33
3993 17:16:29.075942
3994 17:16:29.079730 [CBTSetCACLKResult] CA Dly = 33
3995 17:16:29.082487 CS Dly: 5 (0~36)
3996 17:16:29.082560 ==
3997 17:16:29.085718 Dram Type= 6, Freq= 0, CH_0, rank 1
3998 17:16:29.089053 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
3999 17:16:29.089136 ==
4000 17:16:29.095595 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4001 17:16:29.099050 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4002 17:16:29.103584 [CA 0] Center 36 (6~67) winsize 62
4003 17:16:29.106671 [CA 1] Center 36 (6~67) winsize 62
4004 17:16:29.110019 [CA 2] Center 34 (4~65) winsize 62
4005 17:16:29.113244 [CA 3] Center 34 (4~65) winsize 62
4006 17:16:29.116442 [CA 4] Center 34 (4~64) winsize 61
4007 17:16:29.119786 [CA 5] Center 33 (3~64) winsize 62
4008 17:16:29.119901
4009 17:16:29.123034 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4010 17:16:29.123111
4011 17:16:29.126203 [CATrainingPosCal] consider 2 rank data
4012 17:16:29.129571 u2DelayCellTimex100 = 270/100 ps
4013 17:16:29.132737 CA0 delay=36 (6~67),Diff = 3 PI (28 cell)
4014 17:16:29.139765 CA1 delay=36 (6~67),Diff = 3 PI (28 cell)
4015 17:16:29.143049 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4016 17:16:29.146328 CA3 delay=34 (4~65),Diff = 1 PI (9 cell)
4017 17:16:29.149631 CA4 delay=34 (4~64),Diff = 1 PI (9 cell)
4018 17:16:29.152934 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4019 17:16:29.153017
4020 17:16:29.155964 CA PerBit enable=1, Macro0, CA PI delay=33
4021 17:16:29.156071
4022 17:16:29.159143 [CBTSetCACLKResult] CA Dly = 33
4023 17:16:29.162428 CS Dly: 5 (0~37)
4024 17:16:29.162514
4025 17:16:29.165670 ----->DramcWriteLeveling(PI) begin...
4026 17:16:29.165761 ==
4027 17:16:29.169064 Dram Type= 6, Freq= 0, CH_0, rank 0
4028 17:16:29.172494 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4029 17:16:29.172583 ==
4030 17:16:29.175666 Write leveling (Byte 0): 33 => 33
4031 17:16:29.178856 Write leveling (Byte 1): 28 => 28
4032 17:16:29.182246 DramcWriteLeveling(PI) end<-----
4033 17:16:29.182372
4034 17:16:29.182444 ==
4035 17:16:29.185623 Dram Type= 6, Freq= 0, CH_0, rank 0
4036 17:16:29.188944 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4037 17:16:29.189028 ==
4038 17:16:29.192286 [Gating] SW mode calibration
4039 17:16:29.198721 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4040 17:16:29.205342 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4041 17:16:29.208623 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4042 17:16:29.214649 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4043 17:16:29.217907 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4044 17:16:29.221228 0 9 12 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
4045 17:16:29.228436 0 9 16 | B1->B0 | 2f2f 2626 | 1 1 | (1 1) (1 0)
4046 17:16:29.231604 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4047 17:16:29.234901 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4048 17:16:29.240907 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4049 17:16:29.244764 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4050 17:16:29.247354 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4051 17:16:29.254032 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4052 17:16:29.257228 0 10 12 | B1->B0 | 2525 2f2f | 1 0 | (0 0) (0 0)
4053 17:16:29.260426 0 10 16 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
4054 17:16:29.267070 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4055 17:16:29.270381 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4056 17:16:29.273757 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4057 17:16:29.280292 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4058 17:16:29.283518 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4059 17:16:29.287002 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4060 17:16:29.293504 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
4061 17:16:29.296845 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4062 17:16:29.299966 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4063 17:16:29.306639 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4064 17:16:29.309392 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4065 17:16:29.312652 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4066 17:16:29.316472
4067 17:16:29.319762 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4068 17:16:29.323094 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4069 17:16:29.329058 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4070 17:16:29.332288 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4071 17:16:29.335630 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4072 17:16:29.342652 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4073 17:16:29.345490 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4074 17:16:29.348710 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4075 17:16:29.355416 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4076 17:16:29.358554 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4077 17:16:29.361933 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4078 17:16:29.368531 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
4079 17:16:29.371794 0 13 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4080 17:16:29.375244 Total UI for P1: 0, mck2ui 16
4081 17:16:29.378695 best dqsien dly found for B0: ( 0, 13, 14)
4082 17:16:29.381923 Total UI for P1: 0, mck2ui 16
4083 17:16:29.384553 best dqsien dly found for B1: ( 0, 13, 18)
4084 17:16:29.387865 best DQS0 dly(MCK, UI, PI) = (0, 13, 14)
4085 17:16:29.391251 best DQS1 dly(MCK, UI, PI) = (0, 13, 18)
4086 17:16:29.391367
4087 17:16:29.394403 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 14)
4088 17:16:29.397747 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 18)
4089 17:16:29.401125
4090 17:16:29.401206 [Gating] SW calibration Done
4091 17:16:29.401272 ==
4092 17:16:29.404247 Dram Type= 6, Freq= 0, CH_0, rank 0
4093 17:16:29.410834 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4094 17:16:29.410945 ==
4095 17:16:29.411018 RX Vref Scan: 0
4096 17:16:29.411087
4097 17:16:29.414758 RX Vref 0 -> 0, step: 1
4098 17:16:29.414853
4099 17:16:29.417302 RX Delay -230 -> 252, step: 16
4100 17:16:29.420639 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4101 17:16:29.424421 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4102 17:16:29.431111 iDelay=218, Bit 2, Center 41 (-118 ~ 201) 320
4103 17:16:29.433778 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4104 17:16:29.437065 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4105 17:16:29.440951 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4106 17:16:29.443684 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4107 17:16:29.450311 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4108 17:16:29.453564 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4109 17:16:29.456909 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4110 17:16:29.460115 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4111 17:16:29.466700 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4112 17:16:29.470200 iDelay=218, Bit 12, Center 41 (-118 ~ 201) 320
4113 17:16:29.473409 iDelay=218, Bit 13, Center 41 (-118 ~ 201) 320
4114 17:16:29.476737 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4115 17:16:29.483524 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4116 17:16:29.483612 ==
4117 17:16:29.486677 Dram Type= 6, Freq= 0, CH_0, rank 0
4118 17:16:29.489869 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4119 17:16:29.489951 ==
4120 17:16:29.490020 DQS Delay:
4121 17:16:29.493114
4122 17:16:29.493220 DQS0 = 0, DQS1 = 0
4123 17:16:29.493311 DQM Delay:
4124 17:16:29.496387 DQM0 = 42, DQM1 = 34
4125 17:16:29.496467 DQ Delay:
4126 17:16:29.499544 DQ0 =41, DQ1 =41, DQ2 =41, DQ3 =41
4127 17:16:29.502896 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4128 17:16:29.506328 DQ8 =25, DQ9 =17, DQ10 =33, DQ11 =33
4129 17:16:29.509721 DQ12 =41, DQ13 =41, DQ14 =41, DQ15 =41
4130 17:16:29.509802
4131 17:16:29.509871
4132 17:16:29.509941 ==
4133 17:16:29.512937 Dram Type= 6, Freq= 0, CH_0, rank 0
4134 17:16:29.519616 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4135 17:16:29.519700 ==
4136 17:16:29.519767
4137 17:16:29.519829
4138 17:16:29.519890 TX Vref Scan disable
4139 17:16:29.523485 == TX Byte 0 ==
4140 17:16:29.526208 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4141 17:16:29.529469 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4142 17:16:29.533376
4143 17:16:29.533458 == TX Byte 1 ==
4144 17:16:29.536047 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4145 17:16:29.542486 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4146 17:16:29.542576 ==
4147 17:16:29.546394 Dram Type= 6, Freq= 0, CH_0, rank 0
4148 17:16:29.549137 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4149 17:16:29.549217 ==
4150 17:16:29.549297
4151 17:16:29.549372
4152 17:16:29.552999 TX Vref Scan disable
4153 17:16:29.555696 == TX Byte 0 ==
4154 17:16:29.559009 Update DQ dly =578 (2 ,1, 34) DQ OEN =(1 ,6)
4155 17:16:29.562336 Update DQM dly =578 (2 ,1, 34) DQM OEN =(1 ,6)
4156 17:16:29.565582 == TX Byte 1 ==
4157 17:16:29.568872 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4158 17:16:29.572198 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4159 17:16:29.572288
4160 17:16:29.575425 [DATLAT]
4161 17:16:29.575506 Freq=600, CH0 RK0
4162 17:16:29.575573
4163 17:16:29.578765 DATLAT Default: 0x9
4164 17:16:29.578843 0, 0xFFFF, sum = 0
4165 17:16:29.582076 1, 0xFFFF, sum = 0
4166 17:16:29.582154 2, 0xFFFF, sum = 0
4167 17:16:29.585459 3, 0xFFFF, sum = 0
4168 17:16:29.585539 4, 0xFFFF, sum = 0
4169 17:16:29.588780 5, 0xFFFF, sum = 0
4170 17:16:29.588860 6, 0xFFFF, sum = 0
4171 17:16:29.592107 7, 0xFFFF, sum = 0
4172 17:16:29.592195 8, 0x0, sum = 1
4173 17:16:29.595382 9, 0x0, sum = 2
4174 17:16:29.595469 10, 0x0, sum = 3
4175 17:16:29.598778 11, 0x0, sum = 4
4176 17:16:29.598858 best_step = 9
4177 17:16:29.598931
4178 17:16:29.598994 ==
4179 17:16:29.601457 Dram Type= 6, Freq= 0, CH_0, rank 0
4180 17:16:29.608133 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4181 17:16:29.608227 ==
4182 17:16:29.608299 RX Vref Scan: 1
4183 17:16:29.608365
4184 17:16:29.611853 RX Vref 0 -> 0, step: 1
4185 17:16:29.611929
4186 17:16:29.614732 RX Delay -195 -> 252, step: 8
4187 17:16:29.614805
4188 17:16:29.618097 Set Vref, RX VrefLevel [Byte0]: 57
4189 17:16:29.621446 [Byte1]: 58
4190 17:16:29.621529
4191 17:16:29.624636 Final RX Vref Byte 0 = 57 to rank0
4192 17:16:29.628048 Final RX Vref Byte 1 = 58 to rank0
4193 17:16:29.631362 Final RX Vref Byte 0 = 57 to rank1
4194 17:16:29.634619 Final RX Vref Byte 1 = 58 to rank1==
4195 17:16:29.637860 Dram Type= 6, Freq= 0, CH_0, rank 0
4196 17:16:29.641151 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4197 17:16:29.641227 ==
4198 17:16:29.644232 DQS Delay:
4199 17:16:29.644304 DQS0 = 0, DQS1 = 0
4200 17:16:29.647467 DQM Delay:
4201 17:16:29.647549 DQM0 = 42, DQM1 = 33
4202 17:16:29.647651 DQ Delay:
4203 17:16:29.651327 DQ0 =44, DQ1 =44, DQ2 =36, DQ3 =40
4204 17:16:29.654503 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =48
4205 17:16:29.657734 DQ8 =24, DQ9 =16, DQ10 =32, DQ11 =28
4206 17:16:29.661161 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4207 17:16:29.661252
4208 17:16:29.661324
4209 17:16:29.670801 [DQSOSCAuto] RK0, (LSB)MR18= 0x4d44, (MSB)MR19= 0x808, tDQSOscB0 = 396 ps tDQSOscB1 = 395 ps
4210 17:16:29.674187 CH0 RK0: MR19=808, MR18=4D44
4211 17:16:29.680342 CH0_RK0: MR19=0x808, MR18=0x4D44, DQSOSC=395, MR23=63, INC=168, DEC=112
4212 17:16:29.680456
4213 17:16:29.683697 ----->DramcWriteLeveling(PI) begin...
4214 17:16:29.683810 ==
4215 17:16:29.687017 Dram Type= 6, Freq= 0, CH_0, rank 1
4216 17:16:29.690256 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4217 17:16:29.690363 ==
4218 17:16:29.693423 Write leveling (Byte 0): 34 => 34
4219 17:16:29.696804 Write leveling (Byte 1): 30 => 30
4220 17:16:29.700017 DramcWriteLeveling(PI) end<-----
4221 17:16:29.700131
4222 17:16:29.700225 ==
4223 17:16:29.703443 Dram Type= 6, Freq= 0, CH_0, rank 1
4224 17:16:29.706889 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4225 17:16:29.707012 ==
4226 17:16:29.710167 [Gating] SW mode calibration
4227 17:16:29.716316 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4228 17:16:29.723386 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4229 17:16:29.726086 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4230 17:16:29.732847 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4231 17:16:29.736053 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4232 17:16:29.739277 0 9 12 | B1->B0 | 3333 3333 | 1 1 | (1 1) (1 0)
4233 17:16:29.746201 0 9 16 | B1->B0 | 2e2e 2626 | 0 0 | (0 0) (0 0)
4234 17:16:29.749467 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4235 17:16:29.752734 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4236 17:16:29.758828 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4237 17:16:29.762096 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4238 17:16:29.765338 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4239 17:16:29.772325 0 10 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4240 17:16:29.775743 0 10 12 | B1->B0 | 2525 3838 | 0 0 | (0 0) (0 0)
4241 17:16:29.778956 0 10 16 | B1->B0 | 3e3e 4646 | 0 0 | (0 0) (0 0)
4242 17:16:29.785406 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4243 17:16:29.788798 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4244 17:16:29.792074 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4245 17:16:29.798698 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4246 17:16:29.801411 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4247 17:16:29.804756 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4248 17:16:29.811969 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4249 17:16:29.814641 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4250 17:16:29.818063 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4251 17:16:29.824588 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4252 17:16:29.827860 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4253 17:16:29.831139 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4254 17:16:29.837852 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4255 17:16:29.841142 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4256 17:16:29.844404 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4257 17:16:29.850985 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4258 17:16:29.854113 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4259 17:16:29.857565 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4260 17:16:29.864156 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4261 17:16:29.867409 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4262 17:16:29.870602 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4263 17:16:29.877377 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4264 17:16:29.880655 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4265 17:16:29.883361 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4266 17:16:29.886570
4267 17:16:29.886645 Total UI for P1: 0, mck2ui 16
4268 17:16:29.889904 best dqsien dly found for B0: ( 0, 13, 12)
4269 17:16:29.893921 Total UI for P1: 0, mck2ui 16
4270 17:16:29.897077 best dqsien dly found for B1: ( 0, 13, 12)
4271 17:16:29.903220 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4272 17:16:29.906384 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4273 17:16:29.906473
4274 17:16:29.910275 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4275 17:16:29.913606 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4276 17:16:29.916340 [Gating] SW calibration Done
4277 17:16:29.916425 ==
4278 17:16:29.919686 Dram Type= 6, Freq= 0, CH_0, rank 1
4279 17:16:29.923039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4280 17:16:29.923123 ==
4281 17:16:29.926382 RX Vref Scan: 0
4282 17:16:29.926467
4283 17:16:29.926533 RX Vref 0 -> 0, step: 1
4284 17:16:29.926595
4285 17:16:29.929276 RX Delay -230 -> 252, step: 16
4286 17:16:29.936569 iDelay=218, Bit 0, Center 41 (-118 ~ 201) 320
4287 17:16:29.939711 iDelay=218, Bit 1, Center 41 (-118 ~ 201) 320
4288 17:16:29.943019 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4289 17:16:29.946351 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4290 17:16:29.952245 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4291 17:16:29.956128 iDelay=218, Bit 5, Center 33 (-134 ~ 201) 336
4292 17:16:29.959563 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4293 17:16:29.962636 iDelay=218, Bit 7, Center 49 (-118 ~ 217) 336
4294 17:16:29.965937 iDelay=218, Bit 8, Center 17 (-150 ~ 185) 336
4295 17:16:29.972464 iDelay=218, Bit 9, Center 17 (-150 ~ 185) 336
4296 17:16:29.975703 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4297 17:16:29.978877 iDelay=218, Bit 11, Center 25 (-134 ~ 185) 320
4298 17:16:29.982236 iDelay=218, Bit 12, Center 33 (-134 ~ 201) 336
4299 17:16:29.988853 iDelay=218, Bit 13, Center 33 (-134 ~ 201) 336
4300 17:16:29.992291 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4301 17:16:29.995474 iDelay=218, Bit 15, Center 33 (-134 ~ 201) 336
4302 17:16:29.995573 ==
4303 17:16:29.998727 Dram Type= 6, Freq= 0, CH_0, rank 1
4304 17:16:30.004783 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4305 17:16:30.004930 ==
4306 17:16:30.005003 DQS Delay:
4307 17:16:30.008170 DQS0 = 0, DQS1 = 0
4308 17:16:30.008315 DQM Delay:
4309 17:16:30.008427 DQM0 = 40, DQM1 = 30
4310 17:16:30.011570 DQ Delay:
4311 17:16:30.014872 DQ0 =41, DQ1 =41, DQ2 =33, DQ3 =33
4312 17:16:30.018247 DQ4 =41, DQ5 =33, DQ6 =49, DQ7 =49
4313 17:16:30.021541 DQ8 =17, DQ9 =17, DQ10 =33, DQ11 =25
4314 17:16:30.024722 DQ12 =33, DQ13 =33, DQ14 =49, DQ15 =33
4315 17:16:30.024828
4316 17:16:30.024905
4317 17:16:30.024972 ==
4318 17:16:30.028184 Dram Type= 6, Freq= 0, CH_0, rank 1
4319 17:16:30.031536 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4320 17:16:30.031618 ==
4321 17:16:30.031686
4322 17:16:30.031747
4323 17:16:30.034697 TX Vref Scan disable
4324 17:16:30.038037 == TX Byte 0 ==
4325 17:16:30.041406 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4326 17:16:30.044078 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4327 17:16:30.047549 == TX Byte 1 ==
4328 17:16:30.050834 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4329 17:16:30.054052 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4330 17:16:30.054147 ==
4331 17:16:30.057443 Dram Type= 6, Freq= 0, CH_0, rank 1
4332 17:16:30.064064 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4333 17:16:30.064158 ==
4334 17:16:30.064227
4335 17:16:30.064301
4336 17:16:30.064364 TX Vref Scan disable
4337 17:16:30.068725 == TX Byte 0 ==
4338 17:16:30.072027 Update DQ dly =580 (2 ,1, 36) DQ OEN =(1 ,6)
4339 17:16:30.078555 Update DQM dly =580 (2 ,1, 36) DQM OEN =(1 ,6)
4340 17:16:30.078643 == TX Byte 1 ==
4341 17:16:30.081822 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4342 17:16:30.087955 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4343 17:16:30.088041
4344 17:16:30.088109 [DATLAT]
4345 17:16:30.088173 Freq=600, CH0 RK1
4346 17:16:30.088234
4347 17:16:30.091350 DATLAT Default: 0x9
4348 17:16:30.094614 0, 0xFFFF, sum = 0
4349 17:16:30.094704 1, 0xFFFF, sum = 0
4350 17:16:30.098016 2, 0xFFFF, sum = 0
4351 17:16:30.098109 3, 0xFFFF, sum = 0
4352 17:16:30.101450 4, 0xFFFF, sum = 0
4353 17:16:30.101540 5, 0xFFFF, sum = 0
4354 17:16:30.104799 6, 0xFFFF, sum = 0
4355 17:16:30.104892 7, 0xFFFF, sum = 0
4356 17:16:30.108086 8, 0x0, sum = 1
4357 17:16:30.108167 9, 0x0, sum = 2
4358 17:16:30.111483 10, 0x0, sum = 3
4359 17:16:30.111587 11, 0x0, sum = 4
4360 17:16:30.111656 best_step = 9
4361 17:16:30.111735
4362 17:16:30.114735 ==
4363 17:16:30.118044 Dram Type= 6, Freq= 0, CH_0, rank 1
4364 17:16:30.120757 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4365 17:16:30.120839 ==
4366 17:16:30.120904 RX Vref Scan: 0
4367 17:16:30.120966
4368 17:16:30.124096 RX Vref 0 -> 0, step: 1
4369 17:16:30.124173
4370 17:16:30.127553 RX Delay -195 -> 252, step: 8
4371 17:16:30.134320 iDelay=205, Bit 0, Center 40 (-107 ~ 188) 296
4372 17:16:30.137624 iDelay=205, Bit 1, Center 44 (-107 ~ 196) 304
4373 17:16:30.141121 iDelay=205, Bit 2, Center 36 (-115 ~ 188) 304
4374 17:16:30.144347 iDelay=205, Bit 3, Center 44 (-107 ~ 196) 304
4375 17:16:30.150331 iDelay=205, Bit 4, Center 44 (-107 ~ 196) 304
4376 17:16:30.153653 iDelay=205, Bit 5, Center 32 (-115 ~ 180) 296
4377 17:16:30.156972 iDelay=205, Bit 6, Center 52 (-99 ~ 204) 304
4378 17:16:30.160291 iDelay=205, Bit 7, Center 44 (-107 ~ 196) 304
4379 17:16:30.163697 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4380 17:16:30.170405 iDelay=205, Bit 9, Center 16 (-139 ~ 172) 312
4381 17:16:30.173642 iDelay=205, Bit 10, Center 36 (-123 ~ 196) 320
4382 17:16:30.176937 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4383 17:16:30.180199 iDelay=205, Bit 12, Center 40 (-115 ~ 196) 312
4384 17:16:30.186336 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4385 17:16:30.189715 iDelay=205, Bit 14, Center 44 (-107 ~ 196) 304
4386 17:16:30.193001 iDelay=205, Bit 15, Center 40 (-115 ~ 196) 312
4387 17:16:30.193086 ==
4388 17:16:30.196246 Dram Type= 6, Freq= 0, CH_0, rank 1
4389 17:16:30.203039 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4390 17:16:30.203124 ==
4391 17:16:30.203195 DQS Delay:
4392 17:16:30.206431 DQS0 = 0, DQS1 = 0
4393 17:16:30.206507 DQM Delay:
4394 17:16:30.206580 DQM0 = 42, DQM1 = 33
4395 17:16:30.209746 DQ Delay:
4396 17:16:30.213027 DQ0 =40, DQ1 =44, DQ2 =36, DQ3 =44
4397 17:16:30.216428 DQ4 =44, DQ5 =32, DQ6 =52, DQ7 =44
4398 17:16:30.219108 DQ8 =24, DQ9 =16, DQ10 =36, DQ11 =28
4399 17:16:30.222509 DQ12 =40, DQ13 =40, DQ14 =44, DQ15 =40
4400 17:16:30.222589
4401 17:16:30.222656
4402 17:16:30.229214 [DQSOSCAuto] RK1, (LSB)MR18= 0x403c, (MSB)MR19= 0x808, tDQSOscB0 = 398 ps tDQSOscB1 = 397 ps
4403 17:16:30.232606 CH0 RK1: MR19=808, MR18=403C
4404 17:16:30.239347 CH0_RK1: MR19=0x808, MR18=0x403C, DQSOSC=397, MR23=63, INC=166, DEC=110
4405 17:16:30.242097 [RxdqsGatingPostProcess] freq 600
4406 17:16:30.248656 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4407 17:16:30.248739 Pre-setting of DQS Precalculation
4408 17:16:30.252160
4409 17:16:30.255459 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4410 17:16:30.255540 ==
4411 17:16:30.258686 Dram Type= 6, Freq= 0, CH_1, rank 0
4412 17:16:30.262149 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4413 17:16:30.262229 ==
4414 17:16:30.268264 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4415 17:16:30.274799 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
4416 17:16:30.278603 [CA 0] Center 36 (6~66) winsize 61
4417 17:16:30.281867 [CA 1] Center 35 (5~66) winsize 62
4418 17:16:30.285269 [CA 2] Center 34 (4~65) winsize 62
4419 17:16:30.288025 [CA 3] Center 34 (3~65) winsize 63
4420 17:16:30.291383 [CA 4] Center 34 (4~65) winsize 62
4421 17:16:30.294865 [CA 5] Center 33 (3~64) winsize 62
4422 17:16:30.294963
4423 17:16:30.298280 [CmdBusTrainingLP45] Vref(ca) range 1: 37
4424 17:16:30.298384
4425 17:16:30.301630 [CATrainingPosCal] consider 1 rank data
4426 17:16:30.304888 u2DelayCellTimex100 = 270/100 ps
4427 17:16:30.307628 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4428 17:16:30.310954 CA1 delay=35 (5~66),Diff = 2 PI (19 cell)
4429 17:16:30.314374 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4430 17:16:30.317604 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4431 17:16:30.320950
4432 17:16:30.324376 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4433 17:16:30.327837 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4434 17:16:30.327916
4435 17:16:30.331216 CA PerBit enable=1, Macro0, CA PI delay=33
4436 17:16:30.331294
4437 17:16:30.333897 [CBTSetCACLKResult] CA Dly = 33
4438 17:16:30.333986 CS Dly: 4 (0~35)
4439 17:16:30.334050 ==
4440 17:16:30.337215 Dram Type= 6, Freq= 0, CH_1, rank 1
4441 17:16:30.344034 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4442 17:16:30.344118 ==
4443 17:16:30.347458 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
4444 17:16:30.354102 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
4445 17:16:30.357334 [CA 0] Center 35 (5~66) winsize 62
4446 17:16:30.361207 [CA 1] Center 36 (6~66) winsize 61
4447 17:16:30.363938 [CA 2] Center 34 (4~65) winsize 62
4448 17:16:30.367247 [CA 3] Center 34 (3~65) winsize 63
4449 17:16:30.370456 [CA 4] Center 34 (4~65) winsize 62
4450 17:16:30.373761 [CA 5] Center 33 (3~64) winsize 62
4451 17:16:30.373840
4452 17:16:30.377059 [CmdBusTrainingLP45] Vref(ca) range 1: 35
4453 17:16:30.377141
4454 17:16:30.380328 [CATrainingPosCal] consider 2 rank data
4455 17:16:30.383665 u2DelayCellTimex100 = 270/100 ps
4456 17:16:30.387103 CA0 delay=36 (6~66),Diff = 3 PI (28 cell)
4457 17:16:30.390470
4458 17:16:30.393158 CA1 delay=36 (6~66),Diff = 3 PI (28 cell)
4459 17:16:30.396509 CA2 delay=34 (4~65),Diff = 1 PI (9 cell)
4460 17:16:30.399878 CA3 delay=34 (3~65),Diff = 1 PI (9 cell)
4461 17:16:30.403228 CA4 delay=34 (4~65),Diff = 1 PI (9 cell)
4462 17:16:30.406458 CA5 delay=33 (3~64),Diff = 0 PI (0 cell)
4463 17:16:30.406549
4464 17:16:30.409769 CA PerBit enable=1, Macro0, CA PI delay=33
4465 17:16:30.409856
4466 17:16:30.413140 [CBTSetCACLKResult] CA Dly = 33
4467 17:16:30.416409 CS Dly: 5 (0~37)
4468 17:16:30.416496
4469 17:16:30.419573 ----->DramcWriteLeveling(PI) begin...
4470 17:16:30.419659 ==
4471 17:16:30.422852 Dram Type= 6, Freq= 0, CH_1, rank 0
4472 17:16:30.426390 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4473 17:16:30.426477 ==
4474 17:16:30.429582 Write leveling (Byte 0): 28 => 28
4475 17:16:30.433081 Write leveling (Byte 1): 32 => 32
4476 17:16:30.436304 DramcWriteLeveling(PI) end<-----
4477 17:16:30.436383
4478 17:16:30.436450 ==
4479 17:16:30.439528 Dram Type= 6, Freq= 0, CH_1, rank 0
4480 17:16:30.442943 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4481 17:16:30.443023 ==
4482 17:16:30.446361 [Gating] SW mode calibration
4483 17:16:30.453070 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4484 17:16:30.459076 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4485 17:16:30.462350 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4486 17:16:30.468936 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4487 17:16:30.472363 0 9 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
4488 17:16:30.475723 0 9 12 | B1->B0 | 2f2f 2f2f | 1 0 | (1 1) (0 0)
4489 17:16:30.482752 0 9 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4490 17:16:30.485239 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4491 17:16:30.488502 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4492 17:16:30.495281 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4493 17:16:30.498715 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4494 17:16:30.502231 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4495 17:16:30.508840 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4496 17:16:30.511449 0 10 12 | B1->B0 | 3232 3433 | 0 1 | (0 0) (0 0)
4497 17:16:30.514963 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4498 17:16:30.521657 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4499 17:16:30.524871 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4500 17:16:30.528249 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4501 17:16:30.535016 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4502 17:16:30.537623 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4503 17:16:30.541609 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4504 17:16:30.547622 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
4505 17:16:30.551040 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4506 17:16:30.554383 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4507 17:16:30.560981 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4508 17:16:30.564182 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4509 17:16:30.567428 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4510 17:16:30.574189 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4511 17:16:30.577488 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4512 17:16:30.580849 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4513 17:16:30.587325 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4514 17:16:30.590071 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4515 17:16:30.593480 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4516 17:16:30.600329 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4517 17:16:30.603631 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4518 17:16:30.606986 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4519 17:16:30.613604 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4520 17:16:30.616864 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
4521 17:16:30.620220 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4522 17:16:30.622919 Total UI for P1: 0, mck2ui 16
4523 17:16:30.626430 best dqsien dly found for B0: ( 0, 13, 12)
4524 17:16:30.629805 Total UI for P1: 0, mck2ui 16
4525 17:16:30.633232 best dqsien dly found for B1: ( 0, 13, 12)
4526 17:16:30.636038 best DQS0 dly(MCK, UI, PI) = (0, 13, 12)
4527 17:16:30.639310
4528 17:16:30.642619 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4529 17:16:30.642756
4530 17:16:30.646050 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 12)
4531 17:16:30.649478 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4532 17:16:30.652919 [Gating] SW calibration Done
4533 17:16:30.653002 ==
4534 17:16:30.655669 Dram Type= 6, Freq= 0, CH_1, rank 0
4535 17:16:30.659068 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4536 17:16:30.659151 ==
4537 17:16:30.662390 RX Vref Scan: 0
4538 17:16:30.662488
4539 17:16:30.662570 RX Vref 0 -> 0, step: 1
4540 17:16:30.662637
4541 17:16:30.665564 RX Delay -230 -> 252, step: 16
4542 17:16:30.672354 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4543 17:16:30.675624 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4544 17:16:30.678946 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4545 17:16:30.682515 iDelay=218, Bit 3, Center 41 (-118 ~ 201) 320
4546 17:16:30.685762 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4547 17:16:30.692408 iDelay=218, Bit 5, Center 57 (-102 ~ 217) 320
4548 17:16:30.695755 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4549 17:16:30.698478 iDelay=218, Bit 7, Center 41 (-118 ~ 201) 320
4550 17:16:30.701986 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4551 17:16:30.708751 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4552 17:16:30.712082 iDelay=218, Bit 10, Center 33 (-134 ~ 201) 336
4553 17:16:30.715388 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4554 17:16:30.718047 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4555 17:16:30.724650 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4556 17:16:30.727950 iDelay=218, Bit 14, Center 49 (-118 ~ 217) 336
4557 17:16:30.731247 iDelay=218, Bit 15, Center 41 (-118 ~ 201) 320
4558 17:16:30.731334 ==
4559 17:16:30.734596 Dram Type= 6, Freq= 0, CH_1, rank 0
4560 17:16:30.741352 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4561 17:16:30.741437 ==
4562 17:16:30.741505 DQS Delay:
4563 17:16:30.741566 DQS0 = 0, DQS1 = 0
4564 17:16:30.744699
4565 17:16:30.744784 DQM Delay:
4566 17:16:30.744850 DQM0 = 43, DQM1 = 38
4567 17:16:30.748090 DQ Delay:
4568 17:16:30.751465 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =41
4569 17:16:30.754190 DQ4 =41, DQ5 =57, DQ6 =49, DQ7 =41
4570 17:16:30.757952 DQ8 =25, DQ9 =25, DQ10 =33, DQ11 =33
4571 17:16:30.761286 DQ12 =49, DQ13 =49, DQ14 =49, DQ15 =41
4572 17:16:30.761371
4573 17:16:30.761438
4574 17:16:30.761501 ==
4575 17:16:30.764622 Dram Type= 6, Freq= 0, CH_1, rank 0
4576 17:16:30.767837 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4577 17:16:30.767942 ==
4578 17:16:30.768037
4579 17:16:30.768106
4580 17:16:30.770576 TX Vref Scan disable
4581 17:16:30.773937 == TX Byte 0 ==
4582 17:16:30.777244 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4583 17:16:30.780565 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4584 17:16:30.783944 == TX Byte 1 ==
4585 17:16:30.787410 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4586 17:16:30.790675 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4587 17:16:30.790757 ==
4588 17:16:30.794002 Dram Type= 6, Freq= 0, CH_1, rank 0
4589 17:16:30.800105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4590 17:16:30.800193 ==
4591 17:16:30.800278
4592 17:16:30.800359
4593 17:16:30.800439 TX Vref Scan disable
4594 17:16:30.804652 == TX Byte 0 ==
4595 17:16:30.808089 Update DQ dly =573 (2 ,1, 29) DQ OEN =(1 ,6)
4596 17:16:30.814086 Update DQM dly =573 (2 ,1, 29) DQM OEN =(1 ,6)
4597 17:16:30.814173 == TX Byte 1 ==
4598 17:16:30.817558 Update DQ dly =577 (2 ,1, 33) DQ OEN =(1 ,6)
4599 17:16:30.824236 Update DQM dly =577 (2 ,1, 33) DQM OEN =(1 ,6)
4600 17:16:30.824323
4601 17:16:30.824391 [DATLAT]
4602 17:16:30.824454 Freq=600, CH1 RK0
4603 17:16:30.824515
4604 17:16:30.827462 DATLAT Default: 0x9
4605 17:16:30.830615 0, 0xFFFF, sum = 0
4606 17:16:30.830702 1, 0xFFFF, sum = 0
4607 17:16:30.834179 2, 0xFFFF, sum = 0
4608 17:16:30.834266 3, 0xFFFF, sum = 0
4609 17:16:30.837392 4, 0xFFFF, sum = 0
4610 17:16:30.837479 5, 0xFFFF, sum = 0
4611 17:16:30.840812 6, 0xFFFF, sum = 0
4612 17:16:30.840899 7, 0xFFFF, sum = 0
4613 17:16:30.844133 8, 0x0, sum = 1
4614 17:16:30.844220 9, 0x0, sum = 2
4615 17:16:30.847416 10, 0x0, sum = 3
4616 17:16:30.847503 11, 0x0, sum = 4
4617 17:16:30.847571 best_step = 9
4618 17:16:30.847633
4619 17:16:30.850584 ==
4620 17:16:30.854170 Dram Type= 6, Freq= 0, CH_1, rank 0
4621 17:16:30.856822 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4622 17:16:30.856913 ==
4623 17:16:30.856980 RX Vref Scan: 1
4624 17:16:30.857042
4625 17:16:30.860180 RX Vref 0 -> 0, step: 1
4626 17:16:30.860266
4627 17:16:30.863524 RX Delay -179 -> 252, step: 8
4628 17:16:30.863609
4629 17:16:30.866874 Set Vref, RX VrefLevel [Byte0]: 53
4630 17:16:30.870247 [Byte1]: 53
4631 17:16:30.870333
4632 17:16:30.873483 Final RX Vref Byte 0 = 53 to rank0
4633 17:16:30.876912 Final RX Vref Byte 1 = 53 to rank0
4634 17:16:30.880199 Final RX Vref Byte 0 = 53 to rank1
4635 17:16:30.883580 Final RX Vref Byte 1 = 53 to rank1==
4636 17:16:30.886317 Dram Type= 6, Freq= 0, CH_1, rank 0
4637 17:16:30.893455 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4638 17:16:30.893541 ==
4639 17:16:30.893609 DQS Delay:
4640 17:16:30.893671 DQS0 = 0, DQS1 = 0
4641 17:16:30.896631
4642 17:16:30.896717 DQM Delay:
4643 17:16:30.896784 DQM0 = 41, DQM1 = 34
4644 17:16:30.900100 DQ Delay:
4645 17:16:30.902772 DQ0 =48, DQ1 =40, DQ2 =28, DQ3 =40
4646 17:16:30.906296 DQ4 =36, DQ5 =52, DQ6 =52, DQ7 =36
4647 17:16:30.909721 DQ8 =20, DQ9 =24, DQ10 =36, DQ11 =28
4648 17:16:30.913060 DQ12 =44, DQ13 =44, DQ14 =40, DQ15 =40
4649 17:16:30.913146
4650 17:16:30.913214
4651 17:16:30.919120 [DQSOSCAuto] RK0, (LSB)MR18= 0x2842, (MSB)MR19= 0x808, tDQSOscB0 = 397 ps tDQSOscB1 = 402 ps
4652 17:16:30.922517 CH1 RK0: MR19=808, MR18=2842
4653 17:16:30.929087 CH1_RK0: MR19=0x808, MR18=0x2842, DQSOSC=397, MR23=63, INC=166, DEC=110
4654 17:16:30.929174
4655 17:16:30.932489 ----->DramcWriteLeveling(PI) begin...
4656 17:16:30.932577 ==
4657 17:16:30.935735 Dram Type= 6, Freq= 0, CH_1, rank 1
4658 17:16:30.939160 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4659 17:16:30.939247 ==
4660 17:16:30.942546 Write leveling (Byte 0): 26 => 26
4661 17:16:30.945160 Write leveling (Byte 1): 30 => 30
4662 17:16:30.948490 DramcWriteLeveling(PI) end<-----
4663 17:16:30.948576
4664 17:16:30.948643 ==
4665 17:16:30.952476 Dram Type= 6, Freq= 0, CH_1, rank 1
4666 17:16:30.958415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4667 17:16:30.958502 ==
4668 17:16:30.958575 [Gating] SW mode calibration
4669 17:16:30.968259 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 0
4670 17:16:30.971499 RX_Path_delay_UI(25) -3 - DQSINCTL_UI(16) = u1StartUI(9)
4671 17:16:30.978332 0 9 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4672 17:16:30.981721 0 9 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
4673 17:16:30.985053 0 9 8 | B1->B0 | 3434 3434 | 1 0 | (1 1) (0 0)
4674 17:16:30.991504 0 9 12 | B1->B0 | 3030 2626 | 0 0 | (0 1) (1 1)
4675 17:16:30.994698 0 9 16 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
4676 17:16:30.997823 0 9 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4677 17:16:31.004731 0 9 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4678 17:16:31.007576 0 9 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4679 17:16:31.011056 0 10 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4680 17:16:31.017759 0 10 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
4681 17:16:31.021132 0 10 8 | B1->B0 | 2323 2424 | 0 0 | (0 0) (0 0)
4682 17:16:31.024422 0 10 12 | B1->B0 | 3131 3b3b | 0 0 | (0 0) (0 0)
4683 17:16:31.030827 0 10 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4684 17:16:31.033668 0 10 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4685 17:16:31.037149 0 10 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4686 17:16:31.043810 0 10 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4687 17:16:31.047211 0 11 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4688 17:16:31.050476 0 11 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4689 17:16:31.056910 0 11 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4690 17:16:31.060416 0 11 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
4691 17:16:31.063701 0 11 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4692 17:16:31.069719 0 11 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4693 17:16:31.073160 0 11 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4694 17:16:31.076367 0 11 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4695 17:16:31.083028 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4696 17:16:31.086329 0 12 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4697 17:16:31.089729 0 12 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4698 17:16:31.096304 0 12 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4699 17:16:31.099516 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4700 17:16:31.102909 0 12 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4701 17:16:31.109347 0 12 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4702 17:16:31.112671 0 12 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4703 17:16:31.116127 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4704 17:16:31.123044 0 13 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4705 17:16:31.126328 0 13 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
4706 17:16:31.129604 0 13 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
4707 17:16:31.132193 Total UI for P1: 0, mck2ui 16
4708 17:16:31.135471 best dqsien dly found for B0: ( 0, 13, 10)
4709 17:16:31.142232 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
4710 17:16:31.145708 Total UI for P1: 0, mck2ui 16
4711 17:16:31.149079 best dqsien dly found for B1: ( 0, 13, 12)
4712 17:16:31.151765 best DQS0 dly(MCK, UI, PI) = (0, 13, 10)
4713 17:16:31.155622 best DQS1 dly(MCK, UI, PI) = (0, 13, 12)
4714 17:16:31.155716
4715 17:16:31.158954 best DQS0 P1 dly(MCK, UI, PI) = (1, 1, 10)
4716 17:16:31.161652 best DQS1 P1 dly(MCK, UI, PI) = (1, 1, 12)
4717 17:16:31.165088 [Gating] SW calibration Done
4718 17:16:31.165188 ==
4719 17:16:31.168349 Dram Type= 6, Freq= 0, CH_1, rank 1
4720 17:16:31.171644 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4721 17:16:31.174951 ==
4722 17:16:31.175042 RX Vref Scan: 0
4723 17:16:31.175128
4724 17:16:31.178245 RX Vref 0 -> 0, step: 1
4725 17:16:31.178341
4726 17:16:31.181421 RX Delay -230 -> 252, step: 16
4727 17:16:31.184885 iDelay=218, Bit 0, Center 49 (-118 ~ 217) 336
4728 17:16:31.188002 iDelay=218, Bit 1, Center 33 (-134 ~ 201) 336
4729 17:16:31.191364 iDelay=218, Bit 2, Center 33 (-134 ~ 201) 336
4730 17:16:31.198072 iDelay=218, Bit 3, Center 33 (-134 ~ 201) 336
4731 17:16:31.201265 iDelay=218, Bit 4, Center 41 (-118 ~ 201) 320
4732 17:16:31.204047 iDelay=218, Bit 5, Center 49 (-118 ~ 217) 336
4733 17:16:31.207393 iDelay=218, Bit 6, Center 49 (-118 ~ 217) 336
4734 17:16:31.214187 iDelay=218, Bit 7, Center 33 (-134 ~ 201) 336
4735 17:16:31.217473 iDelay=218, Bit 8, Center 25 (-134 ~ 185) 320
4736 17:16:31.220809 iDelay=218, Bit 9, Center 25 (-134 ~ 185) 320
4737 17:16:31.223745 iDelay=218, Bit 10, Center 41 (-118 ~ 201) 320
4738 17:16:31.230385 iDelay=218, Bit 11, Center 33 (-134 ~ 201) 336
4739 17:16:31.233690 iDelay=218, Bit 12, Center 49 (-118 ~ 217) 336
4740 17:16:31.237055 iDelay=218, Bit 13, Center 49 (-118 ~ 217) 336
4741 17:16:31.240374 iDelay=218, Bit 14, Center 41 (-118 ~ 201) 320
4742 17:16:31.247180 iDelay=218, Bit 15, Center 49 (-118 ~ 217) 336
4743 17:16:31.247283 ==
4744 17:16:31.249857 Dram Type= 6, Freq= 0, CH_1, rank 1
4745 17:16:31.253320 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4746 17:16:31.253418 ==
4747 17:16:31.253508 DQS Delay:
4748 17:16:31.256561 DQS0 = 0, DQS1 = 0
4749 17:16:31.256650 DQM Delay:
4750 17:16:31.259929 DQM0 = 40, DQM1 = 39
4751 17:16:31.260024 DQ Delay:
4752 17:16:31.263294 DQ0 =49, DQ1 =33, DQ2 =33, DQ3 =33
4753 17:16:31.266658 DQ4 =41, DQ5 =49, DQ6 =49, DQ7 =33
4754 17:16:31.269964 DQ8 =25, DQ9 =25, DQ10 =41, DQ11 =33
4755 17:16:31.272744 DQ12 =49, DQ13 =49, DQ14 =41, DQ15 =49
4756 17:16:31.272831
4757 17:16:31.272899
4758 17:16:31.272963 ==
4759 17:16:31.276006 Dram Type= 6, Freq= 0, CH_1, rank 1
4760 17:16:31.279398 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4761 17:16:31.282769
4762 17:16:31.282852 ==
4763 17:16:31.282947
4764 17:16:31.283012
4765 17:16:31.283073 TX Vref Scan disable
4766 17:16:31.285953 == TX Byte 0 ==
4767 17:16:31.289456 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4768 17:16:31.296087 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4769 17:16:31.296175 == TX Byte 1 ==
4770 17:16:31.299431 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4771 17:16:31.306118 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4772 17:16:31.306205 ==
4773 17:16:31.309706 Dram Type= 6, Freq= 0, CH_1, rank 1
4774 17:16:31.312360 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4775 17:16:31.312452 ==
4776 17:16:31.312521
4777 17:16:31.312585
4778 17:16:31.315769 TX Vref Scan disable
4779 17:16:31.319154 == TX Byte 0 ==
4780 17:16:31.322487 Update DQ dly =571 (2 ,1, 27) DQ OEN =(1 ,6)
4781 17:16:31.325810 Update DQM dly =571 (2 ,1, 27) DQM OEN =(1 ,6)
4782 17:16:31.329225 == TX Byte 1 ==
4783 17:16:31.332512 Update DQ dly =575 (2 ,1, 31) DQ OEN =(1 ,6)
4784 17:16:31.335791 Update DQM dly =575 (2 ,1, 31) DQM OEN =(1 ,6)
4785 17:16:31.335876
4786 17:16:31.339208 [DATLAT]
4787 17:16:31.339315 Freq=600, CH1 RK1
4788 17:16:31.339390
4789 17:16:31.341903 DATLAT Default: 0x9
4790 17:16:31.341997 0, 0xFFFF, sum = 0
4791 17:16:31.345883 1, 0xFFFF, sum = 0
4792 17:16:31.345965 2, 0xFFFF, sum = 0
4793 17:16:31.348394 3, 0xFFFF, sum = 0
4794 17:16:31.348475 4, 0xFFFF, sum = 0
4795 17:16:31.351942 5, 0xFFFF, sum = 0
4796 17:16:31.352024 6, 0xFFFF, sum = 0
4797 17:16:31.355262 7, 0xFFFF, sum = 0
4798 17:16:31.355343 8, 0x0, sum = 1
4799 17:16:31.358452 9, 0x0, sum = 2
4800 17:16:31.358533 10, 0x0, sum = 3
4801 17:16:31.361792 11, 0x0, sum = 4
4802 17:16:31.361885 best_step = 9
4803 17:16:31.361963
4804 17:16:31.362028 ==
4805 17:16:31.365191 Dram Type= 6, Freq= 0, CH_1, rank 1
4806 17:16:31.368488 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4807 17:16:31.371784 ==
4808 17:16:31.371874 RX Vref Scan: 0
4809 17:16:31.371944
4810 17:16:31.375257 RX Vref 0 -> 0, step: 1
4811 17:16:31.375344
4812 17:16:31.378314 RX Delay -179 -> 252, step: 8
4813 17:16:31.381587 iDelay=205, Bit 0, Center 40 (-115 ~ 196) 312
4814 17:16:31.384929 iDelay=205, Bit 1, Center 36 (-123 ~ 196) 320
4815 17:16:31.388308
4816 17:16:31.391527 iDelay=205, Bit 2, Center 28 (-131 ~ 188) 320
4817 17:16:31.394900 iDelay=205, Bit 3, Center 36 (-123 ~ 196) 320
4818 17:16:31.398245 iDelay=205, Bit 4, Center 36 (-123 ~ 196) 320
4819 17:16:31.401558 iDelay=205, Bit 5, Center 48 (-107 ~ 204) 312
4820 17:16:31.407878 iDelay=205, Bit 6, Center 44 (-115 ~ 204) 320
4821 17:16:31.411379 iDelay=205, Bit 7, Center 32 (-123 ~ 188) 312
4822 17:16:31.414105 iDelay=205, Bit 8, Center 24 (-131 ~ 180) 312
4823 17:16:31.417550 iDelay=205, Bit 9, Center 24 (-131 ~ 180) 312
4824 17:16:31.424371 iDelay=205, Bit 10, Center 40 (-115 ~ 196) 312
4825 17:16:31.427066 iDelay=205, Bit 11, Center 28 (-123 ~ 180) 304
4826 17:16:31.431026 iDelay=205, Bit 12, Center 44 (-107 ~ 196) 304
4827 17:16:31.434362 iDelay=205, Bit 13, Center 40 (-115 ~ 196) 312
4828 17:16:31.440971 iDelay=205, Bit 14, Center 40 (-115 ~ 196) 312
4829 17:16:31.444184 iDelay=205, Bit 15, Center 44 (-115 ~ 204) 320
4830 17:16:31.444282 ==
4831 17:16:31.446927 Dram Type= 6, Freq= 0, CH_1, rank 1
4832 17:16:31.450415 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
4833 17:16:31.450494 ==
4834 17:16:31.453693 DQS Delay:
4835 17:16:31.453769 DQS0 = 0, DQS1 = 0
4836 17:16:31.457142 DQM Delay:
4837 17:16:31.457225 DQM0 = 37, DQM1 = 35
4838 17:16:31.457289 DQ Delay:
4839 17:16:31.460388 DQ0 =40, DQ1 =36, DQ2 =28, DQ3 =36
4840 17:16:31.463667 DQ4 =36, DQ5 =48, DQ6 =44, DQ7 =32
4841 17:16:31.467184 DQ8 =24, DQ9 =24, DQ10 =40, DQ11 =28
4842 17:16:31.470050 DQ12 =44, DQ13 =40, DQ14 =40, DQ15 =44
4843 17:16:31.470134
4844 17:16:31.470199
4845 17:16:31.480038 [DQSOSCAuto] RK1, (LSB)MR18= 0x365b, (MSB)MR19= 0x808, tDQSOscB0 = 392 ps tDQSOscB1 = 399 ps
4846 17:16:31.483425 CH1 RK1: MR19=808, MR18=365B
4847 17:16:31.490014 CH1_RK1: MR19=0x808, MR18=0x365B, DQSOSC=392, MR23=63, INC=170, DEC=113
4848 17:16:31.493378 [RxdqsGatingPostProcess] freq 600
4849 17:16:31.496058 ChangeDQSINCTL 0, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 1
4850 17:16:31.499437 Pre-setting of DQS Precalculation
4851 17:16:31.506091 [DualRankRxdatlatCal] RK0: 9, RK1: 9, Final_Datlat 9
4852 17:16:31.512890 sync_frequency_calibration_params sync calibration params of frequency 600 to shu:5
4853 17:16:31.519649 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
4854 17:16:31.519749
4855 17:16:31.519843
4856 17:16:31.523030 [Calibration Summary] 1200 Mbps
4857 17:16:31.523115 CH 0, Rank 0
4858 17:16:31.525722 SW Impedance : PASS
4859 17:16:31.528991 DUTY Scan : NO K
4860 17:16:31.529077 ZQ Calibration : PASS
4861 17:16:31.532436 Jitter Meter : NO K
4862 17:16:31.535880 CBT Training : PASS
4863 17:16:31.535962 Write leveling : PASS
4864 17:16:31.539283 RX DQS gating : PASS
4865 17:16:31.542655 RX DQ/DQS(RDDQC) : PASS
4866 17:16:31.542741 TX DQ/DQS : PASS
4867 17:16:31.545974 RX DATLAT : PASS
4868 17:16:31.549194 RX DQ/DQS(Engine): PASS
4869 17:16:31.549298 TX OE : NO K
4870 17:16:31.549368 All Pass.
4871 17:16:31.551887
4872 17:16:31.551966 CH 0, Rank 1
4873 17:16:31.555251 SW Impedance : PASS
4874 17:16:31.555337 DUTY Scan : NO K
4875 17:16:31.559217 ZQ Calibration : PASS
4876 17:16:31.559303 Jitter Meter : NO K
4877 17:16:31.561763
4878 17:16:31.561849 CBT Training : PASS
4879 17:16:31.565238 Write leveling : PASS
4880 17:16:31.565324 RX DQS gating : PASS
4881 17:16:31.568480 RX DQ/DQS(RDDQC) : PASS
4882 17:16:31.571845 TX DQ/DQS : PASS
4883 17:16:31.571932 RX DATLAT : PASS
4884 17:16:31.575011 RX DQ/DQS(Engine): PASS
4885 17:16:31.578394 TX OE : NO K
4886 17:16:31.578481 All Pass.
4887 17:16:31.578549
4888 17:16:31.578612 CH 1, Rank 0
4889 17:16:31.581743 SW Impedance : PASS
4890 17:16:31.585100 DUTY Scan : NO K
4891 17:16:31.585186 ZQ Calibration : PASS
4892 17:16:31.588471 Jitter Meter : NO K
4893 17:16:31.591859 CBT Training : PASS
4894 17:16:31.591945 Write leveling : PASS
4895 17:16:31.595273 RX DQS gating : PASS
4896 17:16:31.598572 RX DQ/DQS(RDDQC) : PASS
4897 17:16:31.598659 TX DQ/DQS : PASS
4898 17:16:31.601297 RX DATLAT : PASS
4899 17:16:31.604665 RX DQ/DQS(Engine): PASS
4900 17:16:31.604751 TX OE : NO K
4901 17:16:31.608011 All Pass.
4902 17:16:31.608092
4903 17:16:31.608158 CH 1, Rank 1
4904 17:16:31.611154 SW Impedance : PASS
4905 17:16:31.611248 DUTY Scan : NO K
4906 17:16:31.614526 ZQ Calibration : PASS
4907 17:16:31.617979 Jitter Meter : NO K
4908 17:16:31.618067 CBT Training : PASS
4909 17:16:31.621455 Write leveling : PASS
4910 17:16:31.624102 RX DQS gating : PASS
4911 17:16:31.624185 RX DQ/DQS(RDDQC) : PASS
4912 17:16:31.627395 TX DQ/DQS : PASS
4913 17:16:31.630717 RX DATLAT : PASS
4914 17:16:31.630797 RX DQ/DQS(Engine): PASS
4915 17:16:31.634076 TX OE : NO K
4916 17:16:31.634158 All Pass.
4917 17:16:31.634232
4918 17:16:31.637448 DramC Write-DBI off
4919 17:16:31.640871 PER_BANK_REFRESH: Hybrid Mode
4920 17:16:31.640963 TX_TRACKING: ON
4921 17:16:31.650848 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 30, TRFC_05T 1, TXREFCNT 44, TRFCpb 9, TRFCpb_05T 1
4922 17:16:31.654362 [FAST_K] Save calibration result to emmc
4923 17:16:31.657121 dramc_set_vcore_voltage set vcore to 662500
4924 17:16:31.660469 Read voltage for 933, 3
4925 17:16:31.660552 Vio18 = 0
4926 17:16:31.660618 Vcore = 662500
4927 17:16:31.663870 Vdram = 0
4928 17:16:31.663948 Vddq = 0
4929 17:16:31.664013 Vmddr = 0
4930 17:16:31.670470 [FAST_K] DramcSave_Time_For_Cal_Init SHU3, femmc_Ready=0
4931 17:16:31.673866 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
4932 17:16:31.676970 MEM_TYPE=3, freq_sel=17
4933 17:16:31.680441 sv_algorithm_assistance_LP4_1600
4934 17:16:31.683755 ============ PULL DRAM RESETB DOWN ============
4935 17:16:31.690336 ========== PULL DRAM RESETB DOWN end =========
4936 17:16:31.693592 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
4937 17:16:31.696924 ===================================
4938 17:16:31.699734 LPDDR4 DRAM CONFIGURATION
4939 17:16:31.703150 ===================================
4940 17:16:31.703240 EX_ROW_EN[0] = 0x0
4941 17:16:31.706584 EX_ROW_EN[1] = 0x0
4942 17:16:31.706663 LP4Y_EN = 0x0
4943 17:16:31.709943 WORK_FSP = 0x0
4944 17:16:31.710027 WL = 0x3
4945 17:16:31.713210 RL = 0x3
4946 17:16:31.713303 BL = 0x2
4947 17:16:31.716612
4948 17:16:31.716694 RPST = 0x0
4949 17:16:31.719435 RD_PRE = 0x0
4950 17:16:31.719527 WR_PRE = 0x1
4951 17:16:31.722730 WR_PST = 0x0
4952 17:16:31.722809 DBI_WR = 0x0
4953 17:16:31.726240 DBI_RD = 0x0
4954 17:16:31.726316 OTF = 0x1
4955 17:16:31.729729 ===================================
4956 17:16:31.732967 ===================================
4957 17:16:31.735795 ANA top config
4958 17:16:31.739103 ===================================
4959 17:16:31.739190 DLL_ASYNC_EN = 0
4960 17:16:31.742456 ALL_SLAVE_EN = 1
4961 17:16:31.745804 NEW_RANK_MODE = 1
4962 17:16:31.749138 DLL_IDLE_MODE = 1
4963 17:16:31.752433 LP45_APHY_COMB_EN = 1
4964 17:16:31.752513 TX_ODT_DIS = 1
4965 17:16:31.755897 NEW_8X_MODE = 1
4966 17:16:31.758562 ===================================
4967 17:16:31.761983 ===================================
4968 17:16:31.765429 data_rate = 1866
4969 17:16:31.768523 CKR = 1
4970 17:16:31.771908 DQ_P2S_RATIO = 8
4971 17:16:31.775383 ===================================
4972 17:16:31.778733 CA_P2S_RATIO = 8
4973 17:16:31.778823 DQ_CA_OPEN = 0
4974 17:16:31.782044 DQ_SEMI_OPEN = 0
4975 17:16:31.785401 CA_SEMI_OPEN = 0
4976 17:16:31.788033 CA_FULL_RATE = 0
4977 17:16:31.791395 DQ_CKDIV4_EN = 1
4978 17:16:31.794701 CA_CKDIV4_EN = 1
4979 17:16:31.794818 CA_PREDIV_EN = 0
4980 17:16:31.797954 PH8_DLY = 0
4981 17:16:31.801416 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
4982 17:16:31.804855 DQ_AAMCK_DIV = 4
4983 17:16:31.808107 CA_AAMCK_DIV = 4
4984 17:16:31.811383 CA_ADMCK_DIV = 4
4985 17:16:31.811512 DQ_TRACK_CA_EN = 0
4986 17:16:31.814683
4987 17:16:31.814764 CA_PICK = 933
4988 17:16:31.818006 CA_MCKIO = 933
4989 17:16:31.821486 MCKIO_SEMI = 0
4990 17:16:31.824401 PLL_FREQ = 3732
4991 17:16:31.827789 DQ_UI_PI_RATIO = 32
4992 17:16:31.831093 CA_UI_PI_RATIO = 0
4993 17:16:31.834446 ===================================
4994 17:16:31.837921 ===================================
4995 17:16:31.838052 memory_type:LPDDR4
4996 17:16:31.841162
4997 17:16:31.841260 GP_NUM : 10
4998 17:16:31.843855 SRAM_EN : 1
4999 17:16:31.843942 MD32_EN : 0
5000 17:16:31.847901 ===================================
5001 17:16:31.850431 [ANA_INIT] >>>>>>>>>>>>>>
5002 17:16:31.853728 <<<<<< [CONFIGURE PHASE]: ANA_TX
5003 17:16:31.857085 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
5004 17:16:31.860463 ===================================
5005 17:16:31.863865 data_rate = 1866,PCW = 0X8f00
5006 17:16:31.867160 ===================================
5007 17:16:31.870510 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
5008 17:16:31.877138 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5009 17:16:31.880492 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
5010 17:16:31.886516 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
5011 17:16:31.890319 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
5012 17:16:31.893767 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
5013 17:16:31.893853 [ANA_INIT] flow start
5014 17:16:31.896361 [ANA_INIT] PLL >>>>>>>>
5015 17:16:31.900363 [ANA_INIT] PLL <<<<<<<<
5016 17:16:31.900449 [ANA_INIT] MIDPI >>>>>>>>
5017 17:16:31.903045 [ANA_INIT] MIDPI <<<<<<<<
5018 17:16:31.906388 [ANA_INIT] DLL >>>>>>>>
5019 17:16:31.906474 [ANA_INIT] flow end
5020 17:16:31.912984 ============ LP4 DIFF to SE enter ============
5021 17:16:31.916193 ============ LP4 DIFF to SE exit ============
5022 17:16:31.919549 [ANA_INIT] <<<<<<<<<<<<<
5023 17:16:31.922875 [Flow] Enable top DCM control >>>>>
5024 17:16:31.926210 [Flow] Enable top DCM control <<<<<
5025 17:16:31.929682 Enable DLL master slave shuffle
5026 17:16:31.932996 ==============================================================
5027 17:16:31.936492 Gating Mode config
5028 17:16:31.942491 ==============================================================
5029 17:16:31.942574 Config description:
5030 17:16:31.952540 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
5031 17:16:31.959332 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
5032 17:16:31.961915 SELPH_MODE 0: By rank 1: By Phase
5033 17:16:31.968766 ==============================================================
5034 17:16:31.972149 GAT_TRACK_EN = 1
5035 17:16:31.975482 RX_GATING_MODE = 2
5036 17:16:31.978687 RX_GATING_TRACK_MODE = 2
5037 17:16:31.982041 SELPH_MODE = 1
5038 17:16:31.985352 PICG_EARLY_EN = 1
5039 17:16:31.988702 VALID_LAT_VALUE = 1
5040 17:16:31.992059 ==============================================================
5041 17:16:31.995157 Enter into Gating configuration >>>>
5042 17:16:31.998585 Exit from Gating configuration <<<<
5043 17:16:32.001926 Enter into DVFS_PRE_config >>>>>
5044 17:16:32.014542 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
5045 17:16:32.018892 Exit from DVFS_PRE_config <<<<<
5046 17:16:32.021630 Enter into PICG configuration >>>>
5047 17:16:32.025044 Exit from PICG configuration <<<<
5048 17:16:32.025124 [RX_INPUT] configuration >>>>>
5049 17:16:32.027705 [RX_INPUT] configuration <<<<<
5050 17:16:32.034512 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
5051 17:16:32.037984 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
5052 17:16:32.041389
5053 17:16:32.044686 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
5054 17:16:32.050712 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
5055 17:16:32.057567 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
5056 17:16:32.064394 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
5057 17:16:32.067079 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
5058 17:16:32.070428 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
5059 17:16:32.076908 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
5060 17:16:32.080363 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
5061 17:16:32.083606 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
5062 17:16:32.090471 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5063 17:16:32.093705 ===================================
5064 17:16:32.093804 LPDDR4 DRAM CONFIGURATION
5065 17:16:32.097071 ===================================
5066 17:16:32.100272 EX_ROW_EN[0] = 0x0
5067 17:16:32.103592 EX_ROW_EN[1] = 0x0
5068 17:16:32.103670 LP4Y_EN = 0x0
5069 17:16:32.106785 WORK_FSP = 0x0
5070 17:16:32.106871 WL = 0x3
5071 17:16:32.110318 RL = 0x3
5072 17:16:32.110402 BL = 0x2
5073 17:16:32.113041 RPST = 0x0
5074 17:16:32.113126 RD_PRE = 0x0
5075 17:16:32.116254 WR_PRE = 0x1
5076 17:16:32.116339 WR_PST = 0x0
5077 17:16:32.119585 DBI_WR = 0x0
5078 17:16:32.119728 DBI_RD = 0x0
5079 17:16:32.122838 OTF = 0x1
5080 17:16:32.126291 ===================================
5081 17:16:32.129777 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
5082 17:16:32.132543 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
5083 17:16:32.139349 [ModeRegister RLWL Config] data_rate:1866-MR2_RLWL:3
5084 17:16:32.142607 ===================================
5085 17:16:32.142722 LPDDR4 DRAM CONFIGURATION
5086 17:16:32.146133 ===================================
5087 17:16:32.149383 EX_ROW_EN[0] = 0x10
5088 17:16:32.152095 EX_ROW_EN[1] = 0x0
5089 17:16:32.152181 LP4Y_EN = 0x0
5090 17:16:32.155524 WORK_FSP = 0x0
5091 17:16:32.155609 WL = 0x3
5092 17:16:32.158723 RL = 0x3
5093 17:16:32.158809 BL = 0x2
5094 17:16:32.162358 RPST = 0x0
5095 17:16:32.162443 RD_PRE = 0x0
5096 17:16:32.165653 WR_PRE = 0x1
5097 17:16:32.165739 WR_PST = 0x0
5098 17:16:32.169020 DBI_WR = 0x0
5099 17:16:32.171659 DBI_RD = 0x0
5100 17:16:32.171745 OTF = 0x1
5101 17:16:32.175566 ===================================
5102 17:16:32.181631 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
5103 17:16:32.185650 nWR fixed to 30
5104 17:16:32.188880 [ModeRegInit_LP4] CH0 RK0
5105 17:16:32.188966 [ModeRegInit_LP4] CH0 RK1
5106 17:16:32.191565 [ModeRegInit_LP4] CH1 RK0
5107 17:16:32.194856 [ModeRegInit_LP4] CH1 RK1
5108 17:16:32.194954 match AC timing 9
5109 17:16:32.201357 dramType 5, freq 933, readDBI 0, DivMode 1, cbtMode 1
5110 17:16:32.204688 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
5111 17:16:32.208060 [WriteLatency GET] Version:0-MR_RL_field_value:3-WL:10
5112 17:16:32.214721 [TX_path_calculate] data rate=1866, WL=10, DQS_TotalUI=21
5113 17:16:32.217627 [TX_path_calculate] DQS = (2,5) DQS_OE = (2,2)
5114 17:16:32.217744 ==
5115 17:16:32.221512 Dram Type= 6, Freq= 0, CH_0, rank 0
5116 17:16:32.224332 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5117 17:16:32.227834
5118 17:16:32.227951 ==
5119 17:16:32.231271 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5120 17:16:32.237370 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5121 17:16:32.240597 [CA 0] Center 37 (7~68) winsize 62
5122 17:16:32.243856 [CA 1] Center 37 (7~68) winsize 62
5123 17:16:32.247325 [CA 2] Center 34 (4~64) winsize 61
5124 17:16:32.250634 [CA 3] Center 33 (3~64) winsize 62
5125 17:16:32.254113 [CA 4] Center 32 (2~63) winsize 62
5126 17:16:32.257437 [CA 5] Center 32 (2~63) winsize 62
5127 17:16:32.257548
5128 17:16:32.260636 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5129 17:16:32.260794
5130 17:16:32.263530 [CATrainingPosCal] consider 1 rank data
5131 17:16:32.267016 u2DelayCellTimex100 = 270/100 ps
5132 17:16:32.270481 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5133 17:16:32.277037 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5134 17:16:32.280283 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5135 17:16:32.283722 CA3 delay=33 (3~64),Diff = 1 PI (6 cell)
5136 17:16:32.287115 CA4 delay=32 (2~63),Diff = 0 PI (0 cell)
5137 17:16:32.289950 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5138 17:16:32.290047
5139 17:16:32.293385 CA PerBit enable=1, Macro0, CA PI delay=32
5140 17:16:32.293467
5141 17:16:32.296828 [CBTSetCACLKResult] CA Dly = 32
5142 17:16:32.300069 CS Dly: 6 (0~37)
5143 17:16:32.300185 ==
5144 17:16:32.303314 Dram Type= 6, Freq= 0, CH_0, rank 1
5145 17:16:32.306642 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5146 17:16:32.306728 ==
5147 17:16:32.313508 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5148 17:16:32.316214 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5149 17:16:32.320883 [CA 0] Center 37 (7~68) winsize 62
5150 17:16:32.324281 [CA 1] Center 37 (7~68) winsize 62
5151 17:16:32.326757 [CA 2] Center 34 (4~65) winsize 62
5152 17:16:32.330274 [CA 3] Center 34 (4~65) winsize 62
5153 17:16:32.333658 [CA 4] Center 33 (3~64) winsize 62
5154 17:16:32.337199 [CA 5] Center 32 (2~63) winsize 62
5155 17:16:32.337289
5156 17:16:32.340100 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5157 17:16:32.340185
5158 17:16:32.343898 [CATrainingPosCal] consider 2 rank data
5159 17:16:32.346824 u2DelayCellTimex100 = 270/100 ps
5160 17:16:32.350184 CA0 delay=37 (7~68),Diff = 5 PI (31 cell)
5161 17:16:32.356868 CA1 delay=37 (7~68),Diff = 5 PI (31 cell)
5162 17:16:32.360268 CA2 delay=34 (4~64),Diff = 2 PI (12 cell)
5163 17:16:32.363527 CA3 delay=34 (4~64),Diff = 2 PI (12 cell)
5164 17:16:32.366894 CA4 delay=33 (3~63),Diff = 1 PI (6 cell)
5165 17:16:32.370403 CA5 delay=32 (2~63),Diff = 0 PI (0 cell)
5166 17:16:32.370489
5167 17:16:32.373023 CA PerBit enable=1, Macro0, CA PI delay=32
5168 17:16:32.373126
5169 17:16:32.376304 [CBTSetCACLKResult] CA Dly = 32
5170 17:16:32.379548 CS Dly: 7 (0~39)
5171 17:16:32.379655
5172 17:16:32.382900 ----->DramcWriteLeveling(PI) begin...
5173 17:16:32.383000 ==
5174 17:16:32.386249 Dram Type= 6, Freq= 0, CH_0, rank 0
5175 17:16:32.389421 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5176 17:16:32.389507 ==
5177 17:16:32.392944 Write leveling (Byte 0): 33 => 33
5178 17:16:32.396411 Write leveling (Byte 1): 28 => 28
5179 17:16:32.399534 DramcWriteLeveling(PI) end<-----
5180 17:16:32.399626
5181 17:16:32.399695 ==
5182 17:16:32.402737 Dram Type= 6, Freq= 0, CH_0, rank 0
5183 17:16:32.406243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5184 17:16:32.406329 ==
5185 17:16:32.409593 [Gating] SW mode calibration
5186 17:16:32.415681 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5187 17:16:32.422266 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5188 17:16:32.425496 0 14 0 | B1->B0 | 2525 3434 | 1 1 | (0 0) (1 1)
5189 17:16:32.432068 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5190 17:16:32.435473 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5191 17:16:32.438784 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5192 17:16:32.445457 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5193 17:16:32.448753 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5194 17:16:32.452141 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5195 17:16:32.458174 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (0 1)
5196 17:16:32.461390 0 15 0 | B1->B0 | 2f2f 2323 | 1 0 | (1 1) (0 0)
5197 17:16:32.464831 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5198 17:16:32.471476 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5199 17:16:32.474833 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5200 17:16:32.478034 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5201 17:16:32.484721 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5202 17:16:32.488206 0 15 24 | B1->B0 | 2323 2727 | 0 0 | (0 0) (0 0)
5203 17:16:32.490811 0 15 28 | B1->B0 | 2323 3b3b | 0 0 | (0 0) (0 0)
5204 17:16:32.497517 1 0 0 | B1->B0 | 3737 4646 | 0 0 | (0 0) (0 0)
5205 17:16:32.500883 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5206 17:16:32.504204 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5207 17:16:32.510839 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5208 17:16:32.514120 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5209 17:16:32.517541 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5210 17:16:32.520160
5211 17:16:32.524036 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5212 17:16:32.527295 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5213 17:16:32.533269 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5214 17:16:32.536848 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5215 17:16:32.540358 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5216 17:16:32.546451 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5217 17:16:32.549854 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5218 17:16:32.553186 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5219 17:16:32.559861 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5220 17:16:32.563185 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5221 17:16:32.566602 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5222 17:16:32.573249 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5223 17:16:32.576008 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5224 17:16:32.579290 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5225 17:16:32.585948 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5226 17:16:32.589272 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5227 17:16:32.592656 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5228 17:16:32.599137 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5229 17:16:32.602498 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5230 17:16:32.605769 Total UI for P1: 0, mck2ui 16
5231 17:16:32.608992 best dqsien dly found for B0: ( 1, 2, 26)
5232 17:16:32.612267 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5233 17:16:32.618857 1 3 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5234 17:16:32.618975 Total UI for P1: 0, mck2ui 16
5235 17:16:32.625543 best dqsien dly found for B1: ( 1, 3, 2)
5236 17:16:32.628735 best DQS0 dly(MCK, UI, PI) = (1, 2, 26)
5237 17:16:32.632197 best DQS1 dly(MCK, UI, PI) = (1, 3, 2)
5238 17:16:32.632284
5239 17:16:32.635551 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 26)
5240 17:16:32.638852 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 2)
5241 17:16:32.641582 [Gating] SW calibration Done
5242 17:16:32.641670 ==
5243 17:16:32.644984 Dram Type= 6, Freq= 0, CH_0, rank 0
5244 17:16:32.648495 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5245 17:16:32.648587 ==
5246 17:16:32.651700 RX Vref Scan: 0
5247 17:16:32.651783
5248 17:16:32.651849 RX Vref 0 -> 0, step: 1
5249 17:16:32.651921
5250 17:16:32.655231
5251 17:16:32.655307 RX Delay -80 -> 252, step: 8
5252 17:16:32.661801 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5253 17:16:32.665172 iDelay=208, Bit 1, Center 99 (0 ~ 199) 200
5254 17:16:32.667876 iDelay=208, Bit 2, Center 95 (0 ~ 191) 192
5255 17:16:32.671190 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5256 17:16:32.674470 iDelay=208, Bit 4, Center 103 (8 ~ 199) 192
5257 17:16:32.677656 iDelay=208, Bit 5, Center 87 (-8 ~ 183) 192
5258 17:16:32.684292 iDelay=208, Bit 6, Center 111 (16 ~ 207) 192
5259 17:16:32.687603 iDelay=208, Bit 7, Center 107 (8 ~ 207) 200
5260 17:16:32.690828 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5261 17:16:32.694242 iDelay=208, Bit 9, Center 75 (-16 ~ 167) 184
5262 17:16:32.697670 iDelay=208, Bit 10, Center 91 (0 ~ 183) 184
5263 17:16:32.704302 iDelay=208, Bit 11, Center 83 (-8 ~ 175) 184
5264 17:16:32.707583 iDelay=208, Bit 12, Center 95 (0 ~ 191) 192
5265 17:16:32.710875 iDelay=208, Bit 13, Center 95 (0 ~ 191) 192
5266 17:16:32.714274 iDelay=208, Bit 14, Center 99 (8 ~ 191) 184
5267 17:16:32.717597 iDelay=208, Bit 15, Center 95 (0 ~ 191) 192
5268 17:16:32.717684 ==
5269 17:16:32.720191 Dram Type= 6, Freq= 0, CH_0, rank 0
5270 17:16:32.726738 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5271 17:16:32.726827 ==
5272 17:16:32.726963 DQS Delay:
5273 17:16:32.729903 DQS0 = 0, DQS1 = 0
5274 17:16:32.730044 DQM Delay:
5275 17:16:32.730139 DQM0 = 100, DQM1 = 89
5276 17:16:32.733852
5277 17:16:32.733952 DQ Delay:
5278 17:16:32.736546 DQ0 =103, DQ1 =99, DQ2 =95, DQ3 =95
5279 17:16:32.740000 DQ4 =103, DQ5 =87, DQ6 =111, DQ7 =107
5280 17:16:32.743421 DQ8 =83, DQ9 =75, DQ10 =91, DQ11 =83
5281 17:16:32.746832 DQ12 =95, DQ13 =95, DQ14 =99, DQ15 =95
5282 17:16:32.746943
5283 17:16:32.747018
5284 17:16:32.747079 ==
5285 17:16:32.750265 Dram Type= 6, Freq= 0, CH_0, rank 0
5286 17:16:32.753509 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5287 17:16:32.753587 ==
5288 17:16:32.753652
5289 17:16:32.753731
5290 17:16:32.756978 TX Vref Scan disable
5291 17:16:32.759532 == TX Byte 0 ==
5292 17:16:32.762834 Update DQ dly =718 (2 ,6, 14) DQ OEN =(2 ,3)
5293 17:16:32.766129 Update DQM dly =718 (2 ,6, 14) DQM OEN =(2 ,3)
5294 17:16:32.769363 == TX Byte 1 ==
5295 17:16:32.772619 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5296 17:16:32.776013 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5297 17:16:32.776104 ==
5298 17:16:32.779372 Dram Type= 6, Freq= 0, CH_0, rank 0
5299 17:16:32.786062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5300 17:16:32.786191 ==
5301 17:16:32.786272
5302 17:16:32.786379
5303 17:16:32.786449 TX Vref Scan disable
5304 17:16:32.789336
5305 17:16:32.789422 == TX Byte 0 ==
5306 17:16:32.795935 Update DQ dly =717 (2 ,6, 13) DQ OEN =(2 ,3)
5307 17:16:32.799322 Update DQM dly =717 (2 ,6, 13) DQM OEN =(2 ,3)
5308 17:16:32.799414 == TX Byte 1 ==
5309 17:16:32.805427 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5310 17:16:32.808820 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5311 17:16:32.808904
5312 17:16:32.808970 [DATLAT]
5313 17:16:32.812056 Freq=933, CH0 RK0
5314 17:16:32.812139
5315 17:16:32.812204 DATLAT Default: 0xd
5316 17:16:32.815420 0, 0xFFFF, sum = 0
5317 17:16:32.815506 1, 0xFFFF, sum = 0
5318 17:16:32.818702 2, 0xFFFF, sum = 0
5319 17:16:32.818805 3, 0xFFFF, sum = 0
5320 17:16:32.822051
5321 17:16:32.822139 4, 0xFFFF, sum = 0
5322 17:16:32.825385 5, 0xFFFF, sum = 0
5323 17:16:32.825476 6, 0xFFFF, sum = 0
5324 17:16:32.828635 7, 0xFFFF, sum = 0
5325 17:16:32.828721 8, 0xFFFF, sum = 0
5326 17:16:32.832032 9, 0xFFFF, sum = 0
5327 17:16:32.832118 10, 0x0, sum = 1
5328 17:16:32.835406 11, 0x0, sum = 2
5329 17:16:32.835506 12, 0x0, sum = 3
5330 17:16:32.838630 13, 0x0, sum = 4
5331 17:16:32.838713 best_step = 11
5332 17:16:32.838786
5333 17:16:32.838861 ==
5334 17:16:32.841486 Dram Type= 6, Freq= 0, CH_0, rank 0
5335 17:16:32.844793 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5336 17:16:32.844877 ==
5337 17:16:32.848224 RX Vref Scan: 1
5338 17:16:32.848318
5339 17:16:32.851606 RX Vref 0 -> 0, step: 1
5340 17:16:32.851694
5341 17:16:32.851765 RX Delay -61 -> 252, step: 4
5342 17:16:32.851826
5343 17:16:32.854862
5344 17:16:32.854954 Set Vref, RX VrefLevel [Byte0]: 57
5345 17:16:32.858222 [Byte1]: 58
5346 17:16:32.862818
5347 17:16:32.862911 Final RX Vref Byte 0 = 57 to rank0
5348 17:16:32.866199 Final RX Vref Byte 1 = 58 to rank0
5349 17:16:32.869812 Final RX Vref Byte 0 = 57 to rank1
5350 17:16:32.873129 Final RX Vref Byte 1 = 58 to rank1==
5351 17:16:32.875947 Dram Type= 6, Freq= 0, CH_0, rank 0
5352 17:16:32.882772 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5353 17:16:32.882859 ==
5354 17:16:32.882935 DQS Delay:
5355 17:16:32.886257 DQS0 = 0, DQS1 = 0
5356 17:16:32.886342 DQM Delay:
5357 17:16:32.886409 DQM0 = 98, DQM1 = 88
5358 17:16:32.889427 DQ Delay:
5359 17:16:32.892140 DQ0 =100, DQ1 =98, DQ2 =92, DQ3 =94
5360 17:16:32.896116 DQ4 =102, DQ5 =90, DQ6 =108, DQ7 =104
5361 17:16:32.899438 DQ8 =78, DQ9 =74, DQ10 =88, DQ11 =84
5362 17:16:32.902576 DQ12 =96, DQ13 =92, DQ14 =96, DQ15 =96
5363 17:16:32.902667
5364 17:16:32.902735
5365 17:16:32.908707 [DQSOSCAuto] RK0, (LSB)MR18= 0x1b15, (MSB)MR19= 0x505, tDQSOscB0 = 415 ps tDQSOscB1 = 413 ps
5366 17:16:32.912066 CH0 RK0: MR19=505, MR18=1B15
5367 17:16:32.918684 CH0_RK0: MR19=0x505, MR18=0x1B15, DQSOSC=413, MR23=63, INC=63, DEC=42
5368 17:16:32.918774
5369 17:16:32.921906 ----->DramcWriteLeveling(PI) begin...
5370 17:16:32.921987 ==
5371 17:16:32.925356 Dram Type= 6, Freq= 0, CH_0, rank 1
5372 17:16:32.928684 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5373 17:16:32.931959 ==
5374 17:16:32.932043 Write leveling (Byte 0): 31 => 31
5375 17:16:32.935255
5376 17:16:32.935340 Write leveling (Byte 1): 27 => 27
5377 17:16:32.938522 DramcWriteLeveling(PI) end<-----
5378 17:16:32.938606
5379 17:16:32.938671 ==
5380 17:16:32.941846 Dram Type= 6, Freq= 0, CH_0, rank 1
5381 17:16:32.947863 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5382 17:16:32.947953 ==
5383 17:16:32.951278 [Gating] SW mode calibration
5384 17:16:32.957972 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5385 17:16:32.961453 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5386 17:16:32.968142 0 14 0 | B1->B0 | 2c2b 3434 | 1 1 | (0 0) (1 1)
5387 17:16:32.970876 0 14 4 | B1->B0 | 3434 3434 | 0 1 | (0 0) (1 1)
5388 17:16:32.974212 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5389 17:16:32.980887 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5390 17:16:32.984222 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5391 17:16:32.987687 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5392 17:16:32.994468 0 14 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5393 17:16:32.997072 0 14 28 | B1->B0 | 3434 2f2f | 1 0 | (1 1) (1 1)
5394 17:16:33.000532 0 15 0 | B1->B0 | 2e2e 2323 | 0 0 | (0 0) (0 0)
5395 17:16:33.007261 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5396 17:16:33.010494 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5397 17:16:33.013764 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5398 17:16:33.020502 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5399 17:16:33.023835 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5400 17:16:33.027196 0 15 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5401 17:16:33.033912 0 15 28 | B1->B0 | 2626 3939 | 0 0 | (0 0) (0 0)
5402 17:16:33.037150 1 0 0 | B1->B0 | 3a3a 4646 | 0 0 | (0 0) (0 0)
5403 17:16:33.039932 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5404 17:16:33.046649 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5405 17:16:33.050083 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5406 17:16:33.053553 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5407 17:16:33.059680 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5408 17:16:33.063030 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5409 17:16:33.066467 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5410 17:16:33.073025 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5411 17:16:33.076354 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5412 17:16:33.079639 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5413 17:16:33.086373 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5414 17:16:33.089112 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5415 17:16:33.092464 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5416 17:16:33.095794
5417 17:16:33.099066 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5418 17:16:33.102427 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5419 17:16:33.109069 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5420 17:16:33.112397 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5421 17:16:33.115617 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5422 17:16:33.122345 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5423 17:16:33.125762 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5424 17:16:33.128259 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5425 17:16:33.135009 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5426 17:16:33.138361 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5427 17:16:33.141787 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5428 17:16:33.145111 Total UI for P1: 0, mck2ui 16
5429 17:16:33.148400 best dqsien dly found for B0: ( 1, 2, 28)
5430 17:16:33.154627 1 3 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5431 17:16:33.154713 Total UI for P1: 0, mck2ui 16
5432 17:16:33.161397 best dqsien dly found for B1: ( 1, 3, 0)
5433 17:16:33.164799 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5434 17:16:33.168269 best DQS1 dly(MCK, UI, PI) = (1, 3, 0)
5435 17:16:33.168354
5436 17:16:33.170894 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5437 17:16:33.174866 best DQS1 P1 dly(MCK, UI, PI) = (1, 7, 0)
5438 17:16:33.177485 [Gating] SW calibration Done
5439 17:16:33.177570 ==
5440 17:16:33.180842 Dram Type= 6, Freq= 0, CH_0, rank 1
5441 17:16:33.184265 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5442 17:16:33.184351 ==
5443 17:16:33.187593 RX Vref Scan: 0
5444 17:16:33.187677
5445 17:16:33.187744 RX Vref 0 -> 0, step: 1
5446 17:16:33.187806
5447 17:16:33.190872 RX Delay -80 -> 252, step: 8
5448 17:16:33.194265 iDelay=200, Bit 0, Center 99 (8 ~ 191) 184
5449 17:16:33.197479
5450 17:16:33.200869 iDelay=200, Bit 1, Center 103 (8 ~ 199) 192
5451 17:16:33.204217 iDelay=200, Bit 2, Center 95 (0 ~ 191) 192
5452 17:16:33.206890 iDelay=200, Bit 3, Center 95 (0 ~ 191) 192
5453 17:16:33.210768 iDelay=200, Bit 4, Center 103 (8 ~ 199) 192
5454 17:16:33.213450 iDelay=200, Bit 5, Center 87 (-8 ~ 183) 192
5455 17:16:33.220551 iDelay=200, Bit 6, Center 103 (8 ~ 199) 192
5456 17:16:33.223367 iDelay=200, Bit 7, Center 103 (8 ~ 199) 192
5457 17:16:33.226580 iDelay=200, Bit 8, Center 83 (-8 ~ 175) 184
5458 17:16:33.230015 iDelay=200, Bit 9, Center 79 (-8 ~ 167) 176
5459 17:16:33.233367 iDelay=200, Bit 10, Center 91 (0 ~ 183) 184
5460 17:16:33.236699 iDelay=200, Bit 11, Center 87 (0 ~ 175) 176
5461 17:16:33.243342 iDelay=200, Bit 12, Center 95 (0 ~ 191) 192
5462 17:16:33.246638 iDelay=200, Bit 13, Center 95 (0 ~ 191) 192
5463 17:16:33.250017 iDelay=200, Bit 14, Center 95 (0 ~ 191) 192
5464 17:16:33.253440 iDelay=200, Bit 15, Center 91 (0 ~ 183) 184
5465 17:16:33.253547 ==
5466 17:16:33.256168 Dram Type= 6, Freq= 0, CH_0, rank 1
5467 17:16:33.262926 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5468 17:16:33.263043 ==
5469 17:16:33.263148 DQS Delay:
5470 17:16:33.263214 DQS0 = 0, DQS1 = 0
5471 17:16:33.266317
5472 17:16:33.266427 DQM Delay:
5473 17:16:33.266508 DQM0 = 98, DQM1 = 89
5474 17:16:33.269593 DQ Delay:
5475 17:16:33.272905 DQ0 =99, DQ1 =103, DQ2 =95, DQ3 =95
5476 17:16:33.276220 DQ4 =103, DQ5 =87, DQ6 =103, DQ7 =103
5477 17:16:33.279564 DQ8 =83, DQ9 =79, DQ10 =91, DQ11 =87
5478 17:16:33.282839 DQ12 =95, DQ13 =95, DQ14 =95, DQ15 =91
5479 17:16:33.282971
5480 17:16:33.283058
5481 17:16:33.283169 ==
5482 17:16:33.285598 Dram Type= 6, Freq= 0, CH_0, rank 1
5483 17:16:33.289013 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5484 17:16:33.289094 ==
5485 17:16:33.289162
5486 17:16:33.289224
5487 17:16:33.292497 TX Vref Scan disable
5488 17:16:33.295990 == TX Byte 0 ==
5489 17:16:33.299158 Update DQ dly =716 (2 ,6, 12) DQ OEN =(2 ,3)
5490 17:16:33.302429 Update DQM dly =716 (2 ,6, 12) DQM OEN =(2 ,3)
5491 17:16:33.305621 == TX Byte 1 ==
5492 17:16:33.308995 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5493 17:16:33.312258 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5494 17:16:33.312343 ==
5495 17:16:33.315575 Dram Type= 6, Freq= 0, CH_0, rank 1
5496 17:16:33.322090 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5497 17:16:33.322188 ==
5498 17:16:33.322256
5499 17:16:33.322320
5500 17:16:33.322394 TX Vref Scan disable
5501 17:16:33.326083 == TX Byte 0 ==
5502 17:16:33.329298 Update DQ dly =715 (2 ,6, 11) DQ OEN =(2 ,3)
5503 17:16:33.336088 Update DQM dly =715 (2 ,6, 11) DQM OEN =(2 ,3)
5504 17:16:33.336191 == TX Byte 1 ==
5505 17:16:33.339518 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5506 17:16:33.345911 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5507 17:16:33.346017
5508 17:16:33.346087 [DATLAT]
5509 17:16:33.346157 Freq=933, CH0 RK1
5510 17:16:33.346238
5511 17:16:33.349149 DATLAT Default: 0xb
5512 17:16:33.351964 0, 0xFFFF, sum = 0
5513 17:16:33.352048 1, 0xFFFF, sum = 0
5514 17:16:33.355360 2, 0xFFFF, sum = 0
5515 17:16:33.355457 3, 0xFFFF, sum = 0
5516 17:16:33.358718 4, 0xFFFF, sum = 0
5517 17:16:33.358802 5, 0xFFFF, sum = 0
5518 17:16:33.362154 6, 0xFFFF, sum = 0
5519 17:16:33.362237 7, 0xFFFF, sum = 0
5520 17:16:33.365393 8, 0xFFFF, sum = 0
5521 17:16:33.365479 9, 0xFFFF, sum = 0
5522 17:16:33.368931 10, 0x0, sum = 1
5523 17:16:33.369019 11, 0x0, sum = 2
5524 17:16:33.372251 12, 0x0, sum = 3
5525 17:16:33.372339 13, 0x0, sum = 4
5526 17:16:33.375471 best_step = 11
5527 17:16:33.375554
5528 17:16:33.375623 ==
5529 17:16:33.378785 Dram Type= 6, Freq= 0, CH_0, rank 1
5530 17:16:33.382029 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5531 17:16:33.382121 ==
5532 17:16:33.382189 RX Vref Scan: 0
5533 17:16:33.385303
5534 17:16:33.385381
5535 17:16:33.385447 RX Vref 0 -> 0, step: 1
5536 17:16:33.385520
5537 17:16:33.388012 RX Delay -53 -> 252, step: 4
5538 17:16:33.394747 iDelay=199, Bit 0, Center 96 (7 ~ 186) 180
5539 17:16:33.398136 iDelay=199, Bit 1, Center 98 (7 ~ 190) 184
5540 17:16:33.401423 iDelay=199, Bit 2, Center 92 (3 ~ 182) 180
5541 17:16:33.404702 iDelay=199, Bit 3, Center 96 (7 ~ 186) 180
5542 17:16:33.408040 iDelay=199, Bit 4, Center 100 (11 ~ 190) 180
5543 17:16:33.411333 iDelay=199, Bit 5, Center 86 (-5 ~ 178) 184
5544 17:16:33.414688
5545 17:16:33.418042 iDelay=199, Bit 6, Center 108 (19 ~ 198) 180
5546 17:16:33.421323 iDelay=199, Bit 7, Center 104 (15 ~ 194) 180
5547 17:16:33.424609 iDelay=199, Bit 8, Center 82 (-5 ~ 170) 176
5548 17:16:33.428000 iDelay=199, Bit 9, Center 76 (-9 ~ 162) 172
5549 17:16:33.431497 iDelay=199, Bit 10, Center 88 (-1 ~ 178) 180
5550 17:16:33.437459 iDelay=199, Bit 11, Center 82 (-5 ~ 170) 176
5551 17:16:33.440913 iDelay=199, Bit 12, Center 94 (7 ~ 182) 176
5552 17:16:33.444113 iDelay=199, Bit 13, Center 92 (3 ~ 182) 180
5553 17:16:33.447251 iDelay=199, Bit 14, Center 100 (11 ~ 190) 180
5554 17:16:33.451268 iDelay=199, Bit 15, Center 96 (7 ~ 186) 180
5555 17:16:33.451353 ==
5556 17:16:33.453897
5557 17:16:33.453975 Dram Type= 6, Freq= 0, CH_0, rank 1
5558 17:16:33.460647 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5559 17:16:33.460737 ==
5560 17:16:33.460811 DQS Delay:
5561 17:16:33.464175 DQS0 = 0, DQS1 = 0
5562 17:16:33.464267 DQM Delay:
5563 17:16:33.467456 DQM0 = 97, DQM1 = 88
5564 17:16:33.467572 DQ Delay:
5565 17:16:33.470828 DQ0 =96, DQ1 =98, DQ2 =92, DQ3 =96
5566 17:16:33.473621 DQ4 =100, DQ5 =86, DQ6 =108, DQ7 =104
5567 17:16:33.476918 DQ8 =82, DQ9 =76, DQ10 =88, DQ11 =82
5568 17:16:33.480299 DQ12 =94, DQ13 =92, DQ14 =100, DQ15 =96
5569 17:16:33.480391
5570 17:16:33.480463
5571 17:16:33.486961 [DQSOSCAuto] RK1, (LSB)MR18= 0x110e, (MSB)MR19= 0x505, tDQSOscB0 = 417 ps tDQSOscB1 = 416 ps
5572 17:16:33.490306
5573 17:16:33.490395 CH0 RK1: MR19=505, MR18=110E
5574 17:16:33.497027 CH0_RK1: MR19=0x505, MR18=0x110E, DQSOSC=416, MR23=63, INC=62, DEC=41
5575 17:16:33.499641 [RxdqsGatingPostProcess] freq 933
5576 17:16:33.506343 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
5577 17:16:33.509640 best DQS0 dly(2T, 0.5T) = (0, 10)
5578 17:16:33.512935 best DQS1 dly(2T, 0.5T) = (0, 11)
5579 17:16:33.516402 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5580 17:16:33.519813 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5581 17:16:33.523133 best DQS0 dly(2T, 0.5T) = (0, 10)
5582 17:16:33.523216 best DQS1 dly(2T, 0.5T) = (0, 11)
5583 17:16:33.526513 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
5584 17:16:33.529173 best DQS1 P1 dly(2T, 0.5T) = (0, 15)
5585 17:16:33.533183 Pre-setting of DQS Precalculation
5586 17:16:33.539151 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
5587 17:16:33.539244 ==
5588 17:16:33.542434 Dram Type= 6, Freq= 0, CH_1, rank 0
5589 17:16:33.545712 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5590 17:16:33.545808 ==
5591 17:16:33.552099 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5592 17:16:33.558930 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
5593 17:16:33.562481 [CA 0] Center 36 (6~67) winsize 62
5594 17:16:33.565809 [CA 1] Center 36 (6~67) winsize 62
5595 17:16:33.568509 [CA 2] Center 34 (4~65) winsize 62
5596 17:16:33.571896 [CA 3] Center 34 (4~64) winsize 61
5597 17:16:33.575067 [CA 4] Center 34 (4~65) winsize 62
5598 17:16:33.578518 [CA 5] Center 33 (3~63) winsize 61
5599 17:16:33.578603
5600 17:16:33.581776 [CmdBusTrainingLP45] Vref(ca) range 1: 37
5601 17:16:33.581871
5602 17:16:33.585197 [CATrainingPosCal] consider 1 rank data
5603 17:16:33.588496 u2DelayCellTimex100 = 270/100 ps
5604 17:16:33.591745 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5605 17:16:33.595050 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5606 17:16:33.598484 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5607 17:16:33.601804 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5608 17:16:33.608292 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5609 17:16:33.611697 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5610 17:16:33.611784
5611 17:16:33.615051 CA PerBit enable=1, Macro0, CA PI delay=33
5612 17:16:33.615137
5613 17:16:33.617620 [CBTSetCACLKResult] CA Dly = 33
5614 17:16:33.617707 CS Dly: 5 (0~36)
5615 17:16:33.617774 ==
5616 17:16:33.621206 Dram Type= 6, Freq= 0, CH_1, rank 1
5617 17:16:33.627859 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5618 17:16:33.627946 ==
5619 17:16:33.631206 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
5620 17:16:33.637949 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
5621 17:16:33.641311 [CA 0] Center 36 (6~67) winsize 62
5622 17:16:33.644040 [CA 1] Center 36 (6~67) winsize 62
5623 17:16:33.647295 [CA 2] Center 34 (4~65) winsize 62
5624 17:16:33.650658 [CA 3] Center 33 (3~64) winsize 62
5625 17:16:33.653921 [CA 4] Center 34 (4~65) winsize 62
5626 17:16:33.657281 [CA 5] Center 33 (3~64) winsize 62
5627 17:16:33.657360
5628 17:16:33.660758 [CmdBusTrainingLP45] Vref(ca) range 1: 35
5629 17:16:33.660842
5630 17:16:33.663965 [CATrainingPosCal] consider 2 rank data
5631 17:16:33.667427 u2DelayCellTimex100 = 270/100 ps
5632 17:16:33.670797 CA0 delay=36 (6~67),Diff = 3 PI (18 cell)
5633 17:16:33.674066
5634 17:16:33.676789 CA1 delay=36 (6~67),Diff = 3 PI (18 cell)
5635 17:16:33.680101 CA2 delay=34 (4~65),Diff = 1 PI (6 cell)
5636 17:16:33.683389 CA3 delay=34 (4~64),Diff = 1 PI (6 cell)
5637 17:16:33.686555 CA4 delay=34 (4~65),Diff = 1 PI (6 cell)
5638 17:16:33.690059 CA5 delay=33 (3~63),Diff = 0 PI (0 cell)
5639 17:16:33.690146
5640 17:16:33.693320 CA PerBit enable=1, Macro0, CA PI delay=33
5641 17:16:33.693407
5642 17:16:33.696631 [CBTSetCACLKResult] CA Dly = 33
5643 17:16:33.699979 CS Dly: 6 (0~38)
5644 17:16:33.700077
5645 17:16:33.703288 ----->DramcWriteLeveling(PI) begin...
5646 17:16:33.703382 ==
5647 17:16:33.706579 Dram Type= 6, Freq= 0, CH_1, rank 0
5648 17:16:33.710006 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5649 17:16:33.710093 ==
5650 17:16:33.713348 Write leveling (Byte 0): 29 => 29
5651 17:16:33.716095 Write leveling (Byte 1): 30 => 30
5652 17:16:33.719327 DramcWriteLeveling(PI) end<-----
5653 17:16:33.719413
5654 17:16:33.719481 ==
5655 17:16:33.722704 Dram Type= 6, Freq= 0, CH_1, rank 0
5656 17:16:33.726051 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5657 17:16:33.726141 ==
5658 17:16:33.729293 [Gating] SW mode calibration
5659 17:16:33.736205 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5660 17:16:33.742321 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5661 17:16:33.745617 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5662 17:16:33.752594 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5663 17:16:33.755353 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5664 17:16:33.758709 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5665 17:16:33.765462 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5666 17:16:33.768923 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5667 17:16:33.772279 0 14 24 | B1->B0 | 3434 3434 | 0 0 | (0 0) (0 0)
5668 17:16:33.778453 0 14 28 | B1->B0 | 2d2d 2323 | 0 0 | (1 0) (0 0)
5669 17:16:33.781731 0 15 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5670 17:16:33.785001 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5671 17:16:33.791620 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5672 17:16:33.795034 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5673 17:16:33.798248 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5674 17:16:33.804462 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5675 17:16:33.808315 0 15 24 | B1->B0 | 2525 2525 | 0 0 | (0 0) (0 0)
5676 17:16:33.811047 0 15 28 | B1->B0 | 3636 3f3f | 0 0 | (0 0) (0 0)
5677 17:16:33.817704 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5678 17:16:33.821014 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5679 17:16:33.824429 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5680 17:16:33.830887 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5681 17:16:33.834295 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5682 17:16:33.837674 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5683 17:16:33.844455 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5684 17:16:33.847072 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (0 1)
5685 17:16:33.850425 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5686 17:16:33.853665
5687 17:16:33.856913 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5688 17:16:33.860374 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5689 17:16:33.867238 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5690 17:16:33.870076 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5691 17:16:33.873505 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5692 17:16:33.880183 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5693 17:16:33.883625 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5694 17:16:33.886392 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5695 17:16:33.893502 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5696 17:16:33.896470 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5697 17:16:33.899799 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5698 17:16:33.906592 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5699 17:16:33.909844 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5700 17:16:33.913303 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5701 17:16:33.919427 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
5702 17:16:33.922713 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5703 17:16:33.926053 Total UI for P1: 0, mck2ui 16
5704 17:16:33.929465 best dqsien dly found for B0: ( 1, 2, 28)
5705 17:16:33.932870 Total UI for P1: 0, mck2ui 16
5706 17:16:33.936378 best dqsien dly found for B1: ( 1, 2, 28)
5707 17:16:33.939137 best DQS0 dly(MCK, UI, PI) = (1, 2, 28)
5708 17:16:33.942560 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5709 17:16:33.942653
5710 17:16:33.946057 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 28)
5711 17:16:33.949051 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5712 17:16:33.952461 [Gating] SW calibration Done
5713 17:16:33.952544 ==
5714 17:16:33.955371 Dram Type= 6, Freq= 0, CH_1, rank 0
5715 17:16:33.958652 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5716 17:16:33.962206
5717 17:16:33.962296 ==
5718 17:16:33.962367 RX Vref Scan: 0
5719 17:16:33.962443
5720 17:16:33.965138 RX Vref 0 -> 0, step: 1
5721 17:16:33.965224
5722 17:16:33.968654 RX Delay -80 -> 252, step: 8
5723 17:16:33.971657 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5724 17:16:33.975109 iDelay=208, Bit 1, Center 95 (0 ~ 191) 192
5725 17:16:33.978640 iDelay=208, Bit 2, Center 91 (0 ~ 183) 184
5726 17:16:33.981592 iDelay=208, Bit 3, Center 99 (0 ~ 199) 200
5727 17:16:33.985076 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5728 17:16:33.992004 iDelay=208, Bit 5, Center 107 (16 ~ 199) 184
5729 17:16:33.994831 iDelay=208, Bit 6, Center 107 (8 ~ 207) 200
5730 17:16:33.998224 iDelay=208, Bit 7, Center 99 (8 ~ 191) 184
5731 17:16:34.001741 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5732 17:16:34.005190 iDelay=208, Bit 9, Center 87 (-8 ~ 183) 192
5733 17:16:34.011720 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5734 17:16:34.015059 iDelay=208, Bit 11, Center 91 (0 ~ 183) 184
5735 17:16:34.018402 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5736 17:16:34.021288 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5737 17:16:34.024598 iDelay=208, Bit 14, Center 103 (8 ~ 199) 192
5738 17:16:34.031441 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5739 17:16:34.031535 ==
5740 17:16:34.034684 Dram Type= 6, Freq= 0, CH_1, rank 0
5741 17:16:34.037475 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5742 17:16:34.037558 ==
5743 17:16:34.037630 DQS Delay:
5744 17:16:34.041032 DQS0 = 0, DQS1 = 0
5745 17:16:34.041115 DQM Delay:
5746 17:16:34.044483 DQM0 = 99, DQM1 = 96
5747 17:16:34.044562 DQ Delay:
5748 17:16:34.047831 DQ0 =103, DQ1 =95, DQ2 =91, DQ3 =99
5749 17:16:34.050562 DQ4 =95, DQ5 =107, DQ6 =107, DQ7 =99
5750 17:16:34.053953 DQ8 =83, DQ9 =87, DQ10 =95, DQ11 =91
5751 17:16:34.057452 DQ12 =103, DQ13 =103, DQ14 =103, DQ15 =103
5752 17:16:34.057534
5753 17:16:34.057602
5754 17:16:34.057668 ==
5755 17:16:34.060590 Dram Type= 6, Freq= 0, CH_1, rank 0
5756 17:16:34.067490 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5757 17:16:34.067584 ==
5758 17:16:34.067657
5759 17:16:34.067720
5760 17:16:34.067782 TX Vref Scan disable
5761 17:16:34.070868 == TX Byte 0 ==
5762 17:16:34.074320 Update DQ dly =712 (2 ,5, 40) DQ OEN =(2 ,2)
5763 17:16:34.080359 Update DQM dly =712 (2 ,5, 40) DQM OEN =(2 ,2)
5764 17:16:34.080444 == TX Byte 1 ==
5765 17:16:34.083647 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5766 17:16:34.090437 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5767 17:16:34.090524 ==
5768 17:16:34.093837 Dram Type= 6, Freq= 0, CH_1, rank 0
5769 17:16:34.097092 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5770 17:16:34.097186 ==
5771 17:16:34.097283
5772 17:16:34.097372
5773 17:16:34.100515 TX Vref Scan disable
5774 17:16:34.103312 == TX Byte 0 ==
5775 17:16:34.106828 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5776 17:16:34.110252 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5777 17:16:34.113639 == TX Byte 1 ==
5778 17:16:34.116791 Update DQ dly =713 (2 ,5, 41) DQ OEN =(2 ,2)
5779 17:16:34.120346 Update DQM dly =713 (2 ,5, 41) DQM OEN =(2 ,2)
5780 17:16:34.120432
5781 17:16:34.120500 [DATLAT]
5782 17:16:34.123538 Freq=933, CH1 RK0
5783 17:16:34.123624
5784 17:16:34.126280 DATLAT Default: 0xd
5785 17:16:34.126361 0, 0xFFFF, sum = 0
5786 17:16:34.129602 1, 0xFFFF, sum = 0
5787 17:16:34.129696 2, 0xFFFF, sum = 0
5788 17:16:34.133060 3, 0xFFFF, sum = 0
5789 17:16:34.133151 4, 0xFFFF, sum = 0
5790 17:16:34.136294 5, 0xFFFF, sum = 0
5791 17:16:34.136379 6, 0xFFFF, sum = 0
5792 17:16:34.139510 7, 0xFFFF, sum = 0
5793 17:16:34.139603 8, 0xFFFF, sum = 0
5794 17:16:34.142885 9, 0xFFFF, sum = 0
5795 17:16:34.142976 10, 0x0, sum = 1
5796 17:16:34.146259 11, 0x0, sum = 2
5797 17:16:34.146344 12, 0x0, sum = 3
5798 17:16:34.149546 13, 0x0, sum = 4
5799 17:16:34.149629 best_step = 11
5800 17:16:34.149705
5801 17:16:34.149771 ==
5802 17:16:34.152861 Dram Type= 6, Freq= 0, CH_1, rank 0
5803 17:16:34.156131 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5804 17:16:34.159447
5805 17:16:34.159529 ==
5806 17:16:34.159603 RX Vref Scan: 1
5807 17:16:34.159671
5808 17:16:34.162637 RX Vref 0 -> 0, step: 1
5809 17:16:34.162724
5810 17:16:34.165996 RX Delay -53 -> 252, step: 4
5811 17:16:34.166080
5812 17:16:34.169425 Set Vref, RX VrefLevel [Byte0]: 53
5813 17:16:34.172200 [Byte1]: 53
5814 17:16:34.172283
5815 17:16:34.175638 Final RX Vref Byte 0 = 53 to rank0
5816 17:16:34.178975 Final RX Vref Byte 1 = 53 to rank0
5817 17:16:34.182377 Final RX Vref Byte 0 = 53 to rank1
5818 17:16:34.185233 Final RX Vref Byte 1 = 53 to rank1==
5819 17:16:34.188827 Dram Type= 6, Freq= 0, CH_1, rank 0
5820 17:16:34.192221 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5821 17:16:34.192316 ==
5822 17:16:34.195051 DQS Delay:
5823 17:16:34.195135 DQS0 = 0, DQS1 = 0
5824 17:16:34.198628 DQM Delay:
5825 17:16:34.198715 DQM0 = 97, DQM1 = 94
5826 17:16:34.198785 DQ Delay:
5827 17:16:34.201983 DQ0 =104, DQ1 =92, DQ2 =86, DQ3 =98
5828 17:16:34.204917 DQ4 =94, DQ5 =106, DQ6 =108, DQ7 =94
5829 17:16:34.208449 DQ8 =80, DQ9 =84, DQ10 =94, DQ11 =88
5830 17:16:34.214913 DQ12 =102, DQ13 =102, DQ14 =102, DQ15 =104
5831 17:16:34.215009
5832 17:16:34.215090
5833 17:16:34.221593 [DQSOSCAuto] RK0, (LSB)MR18= 0xb1a, (MSB)MR19= 0x505, tDQSOscB0 = 413 ps tDQSOscB1 = 418 ps
5834 17:16:34.224922 CH1 RK0: MR19=505, MR18=B1A
5835 17:16:34.231061 CH1_RK0: MR19=0x505, MR18=0xB1A, DQSOSC=413, MR23=63, INC=63, DEC=42
5836 17:16:34.231149
5837 17:16:34.234452 ----->DramcWriteLeveling(PI) begin...
5838 17:16:34.234540 ==
5839 17:16:34.237815 Dram Type= 6, Freq= 0, CH_1, rank 1
5840 17:16:34.241181 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5841 17:16:34.241269 ==
5842 17:16:34.244501 Write leveling (Byte 0): 27 => 27
5843 17:16:34.247631 Write leveling (Byte 1): 28 => 28
5844 17:16:34.251152 DramcWriteLeveling(PI) end<-----
5845 17:16:34.251238
5846 17:16:34.251306 ==
5847 17:16:34.254555 Dram Type= 6, Freq= 0, CH_1, rank 1
5848 17:16:34.257416 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5849 17:16:34.257502 ==
5850 17:16:34.260693 [Gating] SW mode calibration
5851 17:16:34.267287 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 22 , u4TDQSCK_UI_min 2, 1:4ExtraMCK 0
5852 17:16:34.274026 RX_Path_delay_UI(38) -3 - DQSINCTL_UI(24) = u1StartUI(14)
5853 17:16:34.277478 0 14 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5854 17:16:34.283741 0 14 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5855 17:16:34.286904 0 14 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5856 17:16:34.290319 0 14 12 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5857 17:16:34.296980 0 14 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5858 17:16:34.300296 0 14 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
5859 17:16:34.303454 0 14 24 | B1->B0 | 3434 2e2e | 0 1 | (0 0) (1 1)
5860 17:16:34.309651 0 14 28 | B1->B0 | 2b2b 2323 | 0 0 | (0 1) (1 0)
5861 17:16:34.312949 0 15 0 | B1->B0 | 2424 2323 | 0 0 | (0 0) (0 0)
5862 17:16:34.316335 0 15 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5863 17:16:34.322875 0 15 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5864 17:16:34.326631 0 15 12 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5865 17:16:34.329309 0 15 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5866 17:16:34.336143 0 15 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
5867 17:16:34.339409 0 15 24 | B1->B0 | 2323 3131 | 0 1 | (0 0) (0 0)
5868 17:16:34.342604 0 15 28 | B1->B0 | 3b3b 4545 | 0 0 | (0 0) (0 0)
5869 17:16:34.349620 1 0 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5870 17:16:34.353014 1 0 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5871 17:16:34.355722 1 0 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5872 17:16:34.362654 1 0 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5873 17:16:34.365839 1 0 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5874 17:16:34.369135 1 0 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5875 17:16:34.372573
5876 17:16:34.375434 1 0 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
5877 17:16:34.378821 1 0 28 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5878 17:16:34.382274 1 1 0 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
5879 17:16:34.385569
5880 17:16:34.388818 1 1 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5881 17:16:34.392351 1 1 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5882 17:16:34.398374 1 1 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5883 17:16:34.401938 1 1 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5884 17:16:34.405156 1 1 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5885 17:16:34.412070 1 1 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5886 17:16:34.414725 1 1 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5887 17:16:34.418095 1 2 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5888 17:16:34.424795 1 2 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5889 17:16:34.428159 1 2 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5890 17:16:34.431664 1 2 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5891 17:16:34.437924 1 2 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5892 17:16:34.441201 1 2 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
5893 17:16:34.444460 1 2 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
5894 17:16:34.451267 1 2 28 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
5895 17:16:34.451354 Total UI for P1: 0, mck2ui 16
5896 17:16:34.457510 best dqsien dly found for B0: ( 1, 2, 24)
5897 17:16:34.460817 1 3 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
5898 17:16:34.464118 Total UI for P1: 0, mck2ui 16
5899 17:16:34.467284 best dqsien dly found for B1: ( 1, 2, 28)
5900 17:16:34.470623 best DQS0 dly(MCK, UI, PI) = (1, 2, 24)
5901 17:16:34.474164 best DQS1 dly(MCK, UI, PI) = (1, 2, 28)
5902 17:16:34.474251
5903 17:16:34.477556 best DQS0 P1 dly(MCK, UI, PI) = (1, 6, 24)
5904 17:16:34.480433 best DQS1 P1 dly(MCK, UI, PI) = (1, 6, 28)
5905 17:16:34.483762 [Gating] SW calibration Done
5906 17:16:34.483852 ==
5907 17:16:34.487165 Dram Type= 6, Freq= 0, CH_1, rank 1
5908 17:16:34.493439 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5909 17:16:34.493526 ==
5910 17:16:34.493595 RX Vref Scan: 0
5911 17:16:34.493667
5912 17:16:34.496866 RX Vref 0 -> 0, step: 1
5913 17:16:34.496946
5914 17:16:34.500323 RX Delay -80 -> 252, step: 8
5915 17:16:34.503601 iDelay=208, Bit 0, Center 103 (8 ~ 199) 192
5916 17:16:34.507037 iDelay=208, Bit 1, Center 91 (-8 ~ 191) 200
5917 17:16:34.509799 iDelay=208, Bit 2, Center 87 (-8 ~ 183) 192
5918 17:16:34.513255 iDelay=208, Bit 3, Center 95 (0 ~ 191) 192
5919 17:16:34.520195 iDelay=208, Bit 4, Center 95 (0 ~ 191) 192
5920 17:16:34.522877 iDelay=208, Bit 5, Center 107 (8 ~ 207) 200
5921 17:16:34.526207 iDelay=208, Bit 6, Center 103 (8 ~ 199) 192
5922 17:16:34.530219 iDelay=208, Bit 7, Center 95 (0 ~ 191) 192
5923 17:16:34.532974 iDelay=208, Bit 8, Center 83 (-8 ~ 175) 184
5924 17:16:34.536368 iDelay=208, Bit 9, Center 83 (-8 ~ 175) 184
5925 17:16:34.543207 iDelay=208, Bit 10, Center 95 (0 ~ 191) 192
5926 17:16:34.545947 iDelay=208, Bit 11, Center 87 (-8 ~ 183) 192
5927 17:16:34.549452 iDelay=208, Bit 12, Center 103 (8 ~ 199) 192
5928 17:16:34.552900 iDelay=208, Bit 13, Center 103 (8 ~ 199) 192
5929 17:16:34.556267 iDelay=208, Bit 14, Center 95 (0 ~ 191) 192
5930 17:16:34.563018 iDelay=208, Bit 15, Center 103 (8 ~ 199) 192
5931 17:16:34.563103 ==
5932 17:16:34.566329 Dram Type= 6, Freq= 0, CH_1, rank 1
5933 17:16:34.569633 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5934 17:16:34.569715 ==
5935 17:16:34.569782 DQS Delay:
5936 17:16:34.572410 DQS0 = 0, DQS1 = 0
5937 17:16:34.572490 DQM Delay:
5938 17:16:34.575976 DQM0 = 97, DQM1 = 94
5939 17:16:34.576074 DQ Delay:
5940 17:16:34.579409 DQ0 =103, DQ1 =91, DQ2 =87, DQ3 =95
5941 17:16:34.582186 DQ4 =95, DQ5 =107, DQ6 =103, DQ7 =95
5942 17:16:34.585642 DQ8 =83, DQ9 =83, DQ10 =95, DQ11 =87
5943 17:16:34.588953 DQ12 =103, DQ13 =103, DQ14 =95, DQ15 =103
5944 17:16:34.589040
5945 17:16:34.589132
5946 17:16:34.589206 ==
5947 17:16:34.592461 Dram Type= 6, Freq= 0, CH_1, rank 1
5948 17:16:34.598591 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5949 17:16:34.598677 ==
5950 17:16:34.598745
5951 17:16:34.598813
5952 17:16:34.598875 TX Vref Scan disable
5953 17:16:34.602680 == TX Byte 0 ==
5954 17:16:34.605417 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5955 17:16:34.612386 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5956 17:16:34.612475 == TX Byte 1 ==
5957 17:16:34.615170 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5958 17:16:34.621875 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5959 17:16:34.621963 ==
5960 17:16:34.625295 Dram Type= 6, Freq= 0, CH_1, rank 1
5961 17:16:34.628726 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5962 17:16:34.628817 ==
5963 17:16:34.628885
5964 17:16:34.628949
5965 17:16:34.632123 TX Vref Scan disable
5966 17:16:34.635425 == TX Byte 0 ==
5967 17:16:34.638225 Update DQ dly =710 (2 ,5, 38) DQ OEN =(2 ,2)
5968 17:16:34.641733 Update DQM dly =710 (2 ,5, 38) DQM OEN =(2 ,2)
5969 17:16:34.645033 == TX Byte 1 ==
5970 17:16:34.648319 Update DQ dly =711 (2 ,5, 39) DQ OEN =(2 ,2)
5971 17:16:34.651861 Update DQM dly =711 (2 ,5, 39) DQM OEN =(2 ,2)
5972 17:16:34.651948
5973 17:16:34.652017 [DATLAT]
5974 17:16:34.654602 Freq=933, CH1 RK1
5975 17:16:34.654690
5976 17:16:34.657842 DATLAT Default: 0xb
5977 17:16:34.657929 0, 0xFFFF, sum = 0
5978 17:16:34.661286 1, 0xFFFF, sum = 0
5979 17:16:34.661373 2, 0xFFFF, sum = 0
5980 17:16:34.664658 3, 0xFFFF, sum = 0
5981 17:16:34.664746 4, 0xFFFF, sum = 0
5982 17:16:34.668131 5, 0xFFFF, sum = 0
5983 17:16:34.668226 6, 0xFFFF, sum = 0
5984 17:16:34.671470 7, 0xFFFF, sum = 0
5985 17:16:34.671558 8, 0xFFFF, sum = 0
5986 17:16:34.674697 9, 0xFFFF, sum = 0
5987 17:16:34.674793 10, 0x0, sum = 1
5988 17:16:34.678008 11, 0x0, sum = 2
5989 17:16:34.678097 12, 0x0, sum = 3
5990 17:16:34.680844 13, 0x0, sum = 4
5991 17:16:34.680932 best_step = 11
5992 17:16:34.681001
5993 17:16:34.681065 ==
5994 17:16:34.684099 Dram Type= 6, Freq= 0, CH_1, rank 1
5995 17:16:34.691023 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
5996 17:16:34.691110 ==
5997 17:16:34.691184 RX Vref Scan: 0
5998 17:16:34.691251
5999 17:16:34.694432 RX Vref 0 -> 0, step: 1
6000 17:16:34.694518
6001 17:16:34.697096 RX Delay -53 -> 252, step: 4
6002 17:16:34.700382 iDelay=199, Bit 0, Center 102 (11 ~ 194) 184
6003 17:16:34.703734 iDelay=199, Bit 1, Center 94 (-1 ~ 190) 192
6004 17:16:34.710370 iDelay=199, Bit 2, Center 88 (-5 ~ 182) 188
6005 17:16:34.713664 iDelay=199, Bit 3, Center 92 (-1 ~ 186) 188
6006 17:16:34.717098 iDelay=199, Bit 4, Center 96 (3 ~ 190) 188
6007 17:16:34.720416 iDelay=199, Bit 5, Center 106 (15 ~ 198) 184
6008 17:16:34.723668 iDelay=199, Bit 6, Center 104 (11 ~ 198) 188
6009 17:16:34.730332 iDelay=199, Bit 7, Center 94 (-1 ~ 190) 192
6010 17:16:34.733714 iDelay=199, Bit 8, Center 80 (-9 ~ 170) 180
6011 17:16:34.736961 iDelay=199, Bit 9, Center 82 (-9 ~ 174) 184
6012 17:16:34.740381 iDelay=199, Bit 10, Center 92 (-1 ~ 186) 188
6013 17:16:34.743682 iDelay=199, Bit 11, Center 86 (-5 ~ 178) 184
6014 17:16:34.750337 iDelay=199, Bit 12, Center 98 (7 ~ 190) 184
6015 17:16:34.753045 iDelay=199, Bit 13, Center 100 (7 ~ 194) 188
6016 17:16:34.756408 iDelay=199, Bit 14, Center 98 (7 ~ 190) 184
6017 17:16:34.759860 iDelay=199, Bit 15, Center 102 (11 ~ 194) 184
6018 17:16:34.759989 ==
6019 17:16:34.763238 Dram Type= 6, Freq= 0, CH_1, rank 1
6020 17:16:34.766678 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 1
6021 17:16:34.769403 ==
6022 17:16:34.769521 DQS Delay:
6023 17:16:34.769596 DQS0 = 0, DQS1 = 0
6024 17:16:34.772863 DQM Delay:
6025 17:16:34.773001 DQM0 = 97, DQM1 = 92
6026 17:16:34.776160 DQ Delay:
6027 17:16:34.779586 DQ0 =102, DQ1 =94, DQ2 =88, DQ3 =92
6028 17:16:34.783097 DQ4 =96, DQ5 =106, DQ6 =104, DQ7 =94
6029 17:16:34.785916 DQ8 =80, DQ9 =82, DQ10 =92, DQ11 =86
6030 17:16:34.789354 DQ12 =98, DQ13 =100, DQ14 =98, DQ15 =102
6031 17:16:34.789453
6032 17:16:34.789539
6033 17:16:34.795738 [DQSOSCAuto] RK1, (LSB)MR18= 0xe25, (MSB)MR19= 0x505, tDQSOscB0 = 410 ps tDQSOscB1 = 417 ps
6034 17:16:34.799220 CH1 RK1: MR19=505, MR18=E25
6035 17:16:34.806238 CH1_RK1: MR19=0x505, MR18=0xE25, DQSOSC=410, MR23=63, INC=64, DEC=42
6036 17:16:34.808991 [RxdqsGatingPostProcess] freq 933
6037 17:16:34.812180 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 1, u1TXDLY_Cal_min 2
6038 17:16:34.815388 best DQS0 dly(2T, 0.5T) = (0, 10)
6039 17:16:34.819064 best DQS1 dly(2T, 0.5T) = (0, 10)
6040 17:16:34.822419 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6041 17:16:34.825406 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6042 17:16:34.828736 best DQS0 dly(2T, 0.5T) = (0, 10)
6043 17:16:34.832192 best DQS1 dly(2T, 0.5T) = (0, 10)
6044 17:16:34.835305 best DQS0 P1 dly(2T, 0.5T) = (0, 14)
6045 17:16:34.838623 best DQS1 P1 dly(2T, 0.5T) = (0, 14)
6046 17:16:34.842043 Pre-setting of DQS Precalculation
6047 17:16:34.848205 [DualRankRxdatlatCal] RK0: 11, RK1: 11, Final_Datlat 11
6048 17:16:34.855052 sync_frequency_calibration_params sync calibration params of frequency 933 to shu:3
6049 17:16:34.861673 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
6050 17:16:34.861759
6051 17:16:34.861826
6052 17:16:34.865104 [Calibration Summary] 1866 Mbps
6053 17:16:34.865189 CH 0, Rank 0
6054 17:16:34.867819 SW Impedance : PASS
6055 17:16:34.871181 DUTY Scan : NO K
6056 17:16:34.871267 ZQ Calibration : PASS
6057 17:16:34.874628 Jitter Meter : NO K
6058 17:16:34.877730 CBT Training : PASS
6059 17:16:34.877815 Write leveling : PASS
6060 17:16:34.880998 RX DQS gating : PASS
6061 17:16:34.884350 RX DQ/DQS(RDDQC) : PASS
6062 17:16:34.884431 TX DQ/DQS : PASS
6063 17:16:34.887849 RX DATLAT : PASS
6064 17:16:34.891367 RX DQ/DQS(Engine): PASS
6065 17:16:34.891446 TX OE : NO K
6066 17:16:34.891516 All Pass.
6067 17:16:34.893938
6068 17:16:34.894020
6069 17:16:34.894086 CH 0, Rank 1
6070 17:16:34.897570 SW Impedance : PASS
6071 17:16:34.897643 DUTY Scan : NO K
6072 17:16:34.900891 ZQ Calibration : PASS
6073 17:16:34.904168 Jitter Meter : NO K
6074 17:16:34.904248 CBT Training : PASS
6075 17:16:34.907615 Write leveling : PASS
6076 17:16:34.911019 RX DQS gating : PASS
6077 17:16:34.911119 RX DQ/DQS(RDDQC) : PASS
6078 17:16:34.913724 TX DQ/DQS : PASS
6079 17:16:34.913823 RX DATLAT : PASS
6080 17:16:34.917070
6081 17:16:34.917154 RX DQ/DQS(Engine): PASS
6082 17:16:34.920482 TX OE : NO K
6083 17:16:34.920565 All Pass.
6084 17:16:34.920630
6085 17:16:34.923930 CH 1, Rank 0
6086 17:16:34.924015 SW Impedance : PASS
6087 17:16:34.927202 DUTY Scan : NO K
6088 17:16:34.927287 ZQ Calibration : PASS
6089 17:16:34.930652 Jitter Meter : NO K
6090 17:16:34.934140 CBT Training : PASS
6091 17:16:34.934224 Write leveling : PASS
6092 17:16:34.936712 RX DQS gating : PASS
6093 17:16:34.940096 RX DQ/DQS(RDDQC) : PASS
6094 17:16:34.940181 TX DQ/DQS : PASS
6095 17:16:34.943481 RX DATLAT : PASS
6096 17:16:34.946820 RX DQ/DQS(Engine): PASS
6097 17:16:34.946914 TX OE : NO K
6098 17:16:34.950319 All Pass.
6099 17:16:34.950403
6100 17:16:34.950470 CH 1, Rank 1
6101 17:16:34.953404 SW Impedance : PASS
6102 17:16:34.953489 DUTY Scan : NO K
6103 17:16:34.956648 ZQ Calibration : PASS
6104 17:16:34.960067 Jitter Meter : NO K
6105 17:16:34.960158 CBT Training : PASS
6106 17:16:34.963409 Write leveling : PASS
6107 17:16:34.966722 RX DQS gating : PASS
6108 17:16:34.966815 RX DQ/DQS(RDDQC) : PASS
6109 17:16:34.969338 TX DQ/DQS : PASS
6110 17:16:34.972719 RX DATLAT : PASS
6111 17:16:34.972804 RX DQ/DQS(Engine): PASS
6112 17:16:34.976216 TX OE : NO K
6113 17:16:34.976302 All Pass.
6114 17:16:34.976369
6115 17:16:34.979508 DramC Write-DBI off
6116 17:16:34.982876 PER_BANK_REFRESH: Hybrid Mode
6117 17:16:34.982974 TX_TRACKING: ON
6118 17:16:34.992497 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 53, TRFC_05T 1, TXREFCNT 68, TRFCpb 21, TRFCpb_05T 0
6119 17:16:34.995914 [FAST_K] Save calibration result to emmc
6120 17:16:34.999312 dramc_set_vcore_voltage set vcore to 650000
6121 17:16:35.001992 Read voltage for 400, 6
6122 17:16:35.002080 Vio18 = 0
6123 17:16:35.005525 Vcore = 650000
6124 17:16:35.005634 Vdram = 0
6125 17:16:35.005703 Vddq = 0
6126 17:16:35.005764 Vmddr = 0
6127 17:16:35.012314 [FAST_K] DramcSave_Time_For_Cal_Init SHU2, femmc_Ready=0
6128 17:16:35.018302 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
6129 17:16:35.018387 MEM_TYPE=3, freq_sel=20
6130 17:16:35.021829 sv_algorithm_assistance_LP4_800
6131 17:16:35.025232 ============ PULL DRAM RESETB DOWN ============
6132 17:16:35.031625 ========== PULL DRAM RESETB DOWN end =========
6133 17:16:35.035156 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6134 17:16:35.038277 ===================================
6135 17:16:35.041591 LPDDR4 DRAM CONFIGURATION
6136 17:16:35.045063 ===================================
6137 17:16:35.045166 EX_ROW_EN[0] = 0x0
6138 17:16:35.048581 EX_ROW_EN[1] = 0x0
6139 17:16:35.051258 LP4Y_EN = 0x0
6140 17:16:35.051339 WORK_FSP = 0x0
6141 17:16:35.054553 WL = 0x2
6142 17:16:35.054634 RL = 0x2
6143 17:16:35.058013 BL = 0x2
6144 17:16:35.058109 RPST = 0x0
6145 17:16:35.061400 RD_PRE = 0x0
6146 17:16:35.061503 WR_PRE = 0x1
6147 17:16:35.064855 WR_PST = 0x0
6148 17:16:35.064950 DBI_WR = 0x0
6149 17:16:35.067435 DBI_RD = 0x0
6150 17:16:35.067520 OTF = 0x1
6151 17:16:35.070804 ===================================
6152 17:16:35.074292 ===================================
6153 17:16:35.077635 ANA top config
6154 17:16:35.081005 ===================================
6155 17:16:35.084569 DLL_ASYNC_EN = 0
6156 17:16:35.084662 ALL_SLAVE_EN = 1
6157 17:16:35.087276 NEW_RANK_MODE = 1
6158 17:16:35.090686 DLL_IDLE_MODE = 1
6159 17:16:35.094381 LP45_APHY_COMB_EN = 1
6160 17:16:35.094466 TX_ODT_DIS = 1
6161 17:16:35.097025
6162 17:16:35.097110 NEW_8X_MODE = 1
6163 17:16:35.100520 ===================================
6164 17:16:35.103938 ===================================
6165 17:16:35.107508 data_rate = 800
6166 17:16:35.110748 CKR = 1
6167 17:16:35.113647 DQ_P2S_RATIO = 4
6168 17:16:35.117047 ===================================
6169 17:16:35.120546 CA_P2S_RATIO = 4
6170 17:16:35.123262 DQ_CA_OPEN = 0
6171 17:16:35.123343 DQ_SEMI_OPEN = 1
6172 17:16:35.126660 CA_SEMI_OPEN = 1
6173 17:16:35.130296 CA_FULL_RATE = 0
6174 17:16:35.133715 DQ_CKDIV4_EN = 0
6175 17:16:35.136414 CA_CKDIV4_EN = 1
6176 17:16:35.139780 CA_PREDIV_EN = 0
6177 17:16:35.139865 PH8_DLY = 0
6178 17:16:35.143059 SEMI_OPEN_CA_PICK_MCK_RATIO= 4
6179 17:16:35.146418 DQ_AAMCK_DIV = 0
6180 17:16:35.149867 CA_AAMCK_DIV = 0
6181 17:16:35.153367 CA_ADMCK_DIV = 4
6182 17:16:35.156090 DQ_TRACK_CA_EN = 0
6183 17:16:35.159458 CA_PICK = 800
6184 17:16:35.159537 CA_MCKIO = 400
6185 17:16:35.162689 MCKIO_SEMI = 400
6186 17:16:35.166094 PLL_FREQ = 3016
6187 17:16:35.169695 DQ_UI_PI_RATIO = 32
6188 17:16:35.172434 CA_UI_PI_RATIO = 32
6189 17:16:35.175975 ===================================
6190 17:16:35.179438 ===================================
6191 17:16:35.182769 memory_type:LPDDR4
6192 17:16:35.182855 GP_NUM : 10
6193 17:16:35.186145 SRAM_EN : 1
6194 17:16:35.189428 MD32_EN : 0
6195 17:16:35.192203 ===================================
6196 17:16:35.192288 [ANA_INIT] >>>>>>>>>>>>>>
6197 17:16:35.195682 <<<<<< [CONFIGURE PHASE]: ANA_TX
6198 17:16:35.199074 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
6199 17:16:35.202509 ===================================
6200 17:16:35.205268 data_rate = 800,PCW = 0X7400
6201 17:16:35.208660 ===================================
6202 17:16:35.212177 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
6203 17:16:35.218371 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6204 17:16:35.228673 WARN: tr->DQ_AAMCK_DIV= 0, Because of DQ_SEMI_OPEN, It's don't care.<<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
6205 17:16:35.234958 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
6206 17:16:35.238445 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
6207 17:16:35.241747 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
6208 17:16:35.241835 [ANA_INIT] flow start
6209 17:16:35.244941 [ANA_INIT] PLL >>>>>>>>
6210 17:16:35.248278 [ANA_INIT] PLL <<<<<<<<
6211 17:16:35.248364 [ANA_INIT] MIDPI >>>>>>>>
6212 17:16:35.251824 [ANA_INIT] MIDPI <<<<<<<<
6213 17:16:35.254555 [ANA_INIT] DLL >>>>>>>>
6214 17:16:35.254636 [ANA_INIT] flow end
6215 17:16:35.261351 ============ LP4 DIFF to SE enter ============
6216 17:16:35.264740 ============ LP4 DIFF to SE exit ============
6217 17:16:35.268156 [ANA_INIT] <<<<<<<<<<<<<
6218 17:16:35.270878 [Flow] Enable top DCM control >>>>>
6219 17:16:35.274293 [Flow] Enable top DCM control <<<<<
6220 17:16:35.277845 Enable DLL master slave shuffle
6221 17:16:35.281245 ==============================================================
6222 17:16:35.284531 Gating Mode config
6223 17:16:35.290678 ==============================================================
6224 17:16:35.290766 Config description:
6225 17:16:35.300526 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
6226 17:16:35.307280 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
6227 17:16:35.310136 SELPH_MODE 0: By rank 1: By Phase
6228 17:16:35.313475
6229 17:16:35.316941 ==============================================================
6230 17:16:35.320414 GAT_TRACK_EN = 0
6231 17:16:35.323891 RX_GATING_MODE = 2
6232 17:16:35.326560 RX_GATING_TRACK_MODE = 2
6233 17:16:35.330081 SELPH_MODE = 1
6234 17:16:35.333406 PICG_EARLY_EN = 1
6235 17:16:35.336929 VALID_LAT_VALUE = 1
6236 17:16:35.339703 ==============================================================
6237 17:16:35.343163 Enter into Gating configuration >>>>
6238 17:16:35.346397 Exit from Gating configuration <<<<
6239 17:16:35.349623 Enter into DVFS_PRE_config >>>>>
6240 17:16:35.362730 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
6241 17:16:35.366164 Exit from DVFS_PRE_config <<<<<
6242 17:16:35.369699 Enter into PICG configuration >>>>
6243 17:16:35.372927 Exit from PICG configuration <<<<
6244 17:16:35.373036 [RX_INPUT] configuration >>>>>
6245 17:16:35.375687 [RX_INPUT] configuration <<<<<
6246 17:16:35.382609 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
6247 17:16:35.389595 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
6248 17:16:35.392183 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
6249 17:16:35.398873 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
6250 17:16:35.405860 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
6251 17:16:35.411854 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
6252 17:16:35.415235 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
6253 17:16:35.418613 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
6254 17:16:35.425292 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
6255 17:16:35.428601 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
6256 17:16:35.432092 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
6257 17:16:35.438346 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6258 17:16:35.441810 ===================================
6259 17:16:35.441891 LPDDR4 DRAM CONFIGURATION
6260 17:16:35.445000 ===================================
6261 17:16:35.448255 EX_ROW_EN[0] = 0x0
6262 17:16:35.451533 EX_ROW_EN[1] = 0x0
6263 17:16:35.451611 LP4Y_EN = 0x0
6264 17:16:35.454864 WORK_FSP = 0x0
6265 17:16:35.454951 WL = 0x2
6266 17:16:35.458277 RL = 0x2
6267 17:16:35.458358 BL = 0x2
6268 17:16:35.461593 RPST = 0x0
6269 17:16:35.461685 RD_PRE = 0x0
6270 17:16:35.464952 WR_PRE = 0x1
6271 17:16:35.465042 WR_PST = 0x0
6272 17:16:35.468391 DBI_WR = 0x0
6273 17:16:35.468469 DBI_RD = 0x0
6274 17:16:35.471108 OTF = 0x1
6275 17:16:35.474513 ===================================
6276 17:16:35.477656 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
6277 17:16:35.481027 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
6278 17:16:35.487758 [ModeRegister RLWL Config] data_rate: 800-MR2_RLWL:2
6279 17:16:35.490897 ===================================
6280 17:16:35.490995 LPDDR4 DRAM CONFIGURATION
6281 17:16:35.494338 ===================================
6282 17:16:35.497798 EX_ROW_EN[0] = 0x10
6283 17:16:35.501205 EX_ROW_EN[1] = 0x0
6284 17:16:35.501305 LP4Y_EN = 0x0
6285 17:16:35.504466 WORK_FSP = 0x0
6286 17:16:35.504547 WL = 0x2
6287 17:16:35.507244 RL = 0x2
6288 17:16:35.507321 BL = 0x2
6289 17:16:35.511269 RPST = 0x0
6290 17:16:35.511344 RD_PRE = 0x0
6291 17:16:35.514490 WR_PRE = 0x1
6292 17:16:35.514564 WR_PST = 0x0
6293 17:16:35.517196 DBI_WR = 0x0
6294 17:16:35.517275 DBI_RD = 0x0
6295 17:16:35.520593 OTF = 0x1
6296 17:16:35.524046 ===================================
6297 17:16:35.530502 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
6298 17:16:35.533916 nWR fixed to 30
6299 17:16:35.537248 [ModeRegInit_LP4] CH0 RK0
6300 17:16:35.537332 [ModeRegInit_LP4] CH0 RK1
6301 17:16:35.540539 [ModeRegInit_LP4] CH1 RK0
6302 17:16:35.543241 [ModeRegInit_LP4] CH1 RK1
6303 17:16:35.543329 match AC timing 19
6304 17:16:35.550459 dramType 5, freq 400, readDBI 0, DivMode 2, cbtMode 1
6305 17:16:35.553765 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
6306 17:16:35.556477 [WriteLatency GET] Version:0-MR_RL_field_value:2-WL: 8
6307 17:16:35.563219 [TX_path_calculate] data rate=800, WL=8, DQS_TotalUI=17
6308 17:16:35.566653 [TX_path_calculate] DQS = (4,1) DQS_OE = (3,2)
6309 17:16:35.566744 ==
6310 17:16:35.569970 Dram Type= 6, Freq= 0, CH_0, rank 0
6311 17:16:35.573300 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6312 17:16:35.573377 ==
6313 17:16:35.576670
6314 17:16:35.580000 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6315 17:16:35.586671 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6316 17:16:35.590007 [CA 0] Center 36 (8~64) winsize 57
6317 17:16:35.592675 [CA 1] Center 36 (8~64) winsize 57
6318 17:16:35.595922 [CA 2] Center 36 (8~64) winsize 57
6319 17:16:35.599360 [CA 3] Center 36 (8~64) winsize 57
6320 17:16:35.602524 [CA 4] Center 36 (8~64) winsize 57
6321 17:16:35.605901 [CA 5] Center 36 (8~64) winsize 57
6322 17:16:35.605982
6323 17:16:35.609426 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6324 17:16:35.609508
6325 17:16:35.612702 [CATrainingPosCal] consider 1 rank data
6326 17:16:35.615937 u2DelayCellTimex100 = 270/100 ps
6327 17:16:35.619333 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6328 17:16:35.622744 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6329 17:16:35.625426 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6330 17:16:35.628623 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6331 17:16:35.631941 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6332 17:16:35.635345 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6333 17:16:35.635427
6334 17:16:35.638746
6335 17:16:35.642289 CA PerBit enable=1, Macro0, CA PI delay=36
6336 17:16:35.642410
6337 17:16:35.645620 [CBTSetCACLKResult] CA Dly = 36
6338 17:16:35.645701 CS Dly: 1 (0~32)
6339 17:16:35.645764 ==
6340 17:16:35.648851 Dram Type= 6, Freq= 0, CH_0, rank 1
6341 17:16:35.652192 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6342 17:16:35.652274 ==
6343 17:16:35.658207 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6344 17:16:35.664879 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6345 17:16:35.668102 [CA 0] Center 36 (8~64) winsize 57
6346 17:16:35.671371 [CA 1] Center 36 (8~64) winsize 57
6347 17:16:35.674832 [CA 2] Center 36 (8~64) winsize 57
6348 17:16:35.678282 [CA 3] Center 36 (8~64) winsize 57
6349 17:16:35.681634 [CA 4] Center 36 (8~64) winsize 57
6350 17:16:35.684952 [CA 5] Center 36 (8~64) winsize 57
6351 17:16:35.685034
6352 17:16:35.688178 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6353 17:16:35.688259
6354 17:16:35.691419 [CATrainingPosCal] consider 2 rank data
6355 17:16:35.694658 u2DelayCellTimex100 = 270/100 ps
6356 17:16:35.698011 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6357 17:16:35.701471 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6358 17:16:35.704026 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6359 17:16:35.707502 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6360 17:16:35.710885 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6361 17:16:35.714152 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6362 17:16:35.714250
6363 17:16:35.720447 CA PerBit enable=1, Macro0, CA PI delay=36
6364 17:16:35.720529
6365 17:16:35.724290 [CBTSetCACLKResult] CA Dly = 36
6366 17:16:35.724372 CS Dly: 1 (0~32)
6367 17:16:35.724436
6368 17:16:35.727071 ----->DramcWriteLeveling(PI) begin...
6369 17:16:35.727155 ==
6370 17:16:35.730511 Dram Type= 6, Freq= 0, CH_0, rank 0
6371 17:16:35.733867 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6372 17:16:35.737142 ==
6373 17:16:35.737224 Write leveling (Byte 0): 40 => 8
6374 17:16:35.740746 Write leveling (Byte 1): 40 => 8
6375 17:16:35.743614 DramcWriteLeveling(PI) end<-----
6376 17:16:35.743743
6377 17:16:35.743822 ==
6378 17:16:35.747008 Dram Type= 6, Freq= 0, CH_0, rank 0
6379 17:16:35.753801 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6380 17:16:35.753915 ==
6381 17:16:35.754027 [Gating] SW mode calibration
6382 17:16:35.763299 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6383 17:16:35.766749 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6384 17:16:35.773496 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6385 17:16:35.777028 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6386 17:16:35.779791 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6387 17:16:35.786470 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6388 17:16:35.789809 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6389 17:16:35.793191 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6390 17:16:35.799290 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6391 17:16:35.802613 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6392 17:16:35.806208 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6393 17:16:35.809197 Total UI for P1: 0, mck2ui 16
6394 17:16:35.812640 best dqsien dly found for B0: ( 0, 14, 24)
6395 17:16:35.816044 Total UI for P1: 0, mck2ui 16
6396 17:16:35.819481 best dqsien dly found for B1: ( 0, 14, 24)
6397 17:16:35.823069 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6398 17:16:35.825668 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6399 17:16:35.825763
6400 17:16:35.829201
6401 17:16:35.832686 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6402 17:16:35.835565 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6403 17:16:35.839162 [Gating] SW calibration Done
6404 17:16:35.839275 ==
6405 17:16:35.841929 Dram Type= 6, Freq= 0, CH_0, rank 0
6406 17:16:35.845531 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6407 17:16:35.845649 ==
6408 17:16:35.845718 RX Vref Scan: 0
6409 17:16:35.848994
6410 17:16:35.849079
6411 17:16:35.849145 RX Vref 0 -> 0, step: 1
6412 17:16:35.849207
6413 17:16:35.852245 RX Delay -410 -> 252, step: 16
6414 17:16:35.854898 iDelay=230, Bit 0, Center -35 (-282 ~ 213) 496
6415 17:16:35.861724 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6416 17:16:35.865129 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6417 17:16:35.868643 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6418 17:16:35.874824 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6419 17:16:35.878180 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6420 17:16:35.881662 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6421 17:16:35.884294 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6422 17:16:35.891117 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6423 17:16:35.894613 iDelay=230, Bit 9, Center -59 (-314 ~ 197) 512
6424 17:16:35.897938 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6425 17:16:35.901424 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6426 17:16:35.907532 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6427 17:16:35.911029 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6428 17:16:35.913765 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6429 17:16:35.920799 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6430 17:16:35.920898 ==
6431 17:16:35.924243 Dram Type= 6, Freq= 0, CH_0, rank 0
6432 17:16:35.926886 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6433 17:16:35.926970 ==
6434 17:16:35.927039 DQS Delay:
6435 17:16:35.930512 DQS0 = 35, DQS1 = 59
6436 17:16:35.930588 DQM Delay:
6437 17:16:35.933967 DQM0 = 5, DQM1 = 17
6438 17:16:35.934051 DQ Delay:
6439 17:16:35.936578 DQ0 =0, DQ1 =0, DQ2 =0, DQ3 =0
6440 17:16:35.939959 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6441 17:16:35.943632 DQ8 =8, DQ9 =0, DQ10 =24, DQ11 =8
6442 17:16:35.947061 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6443 17:16:35.947145
6444 17:16:35.947210
6445 17:16:35.947272 ==
6446 17:16:35.949647 Dram Type= 6, Freq= 0, CH_0, rank 0
6447 17:16:35.953135 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6448 17:16:35.953220 ==
6449 17:16:35.953286
6450 17:16:35.953347
6451 17:16:35.956593
6452 17:16:35.956677 TX Vref Scan disable
6453 17:16:35.960057 == TX Byte 0 ==
6454 17:16:35.962759 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6455 17:16:35.966135 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6456 17:16:35.969625 == TX Byte 1 ==
6457 17:16:35.973201 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6458 17:16:35.976555 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6459 17:16:35.976637 ==
6460 17:16:35.979282 Dram Type= 6, Freq= 0, CH_0, rank 0
6461 17:16:35.982751 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6462 17:16:35.986227 ==
6463 17:16:35.986309
6464 17:16:35.986377
6465 17:16:35.986442 TX Vref Scan disable
6466 17:16:35.989115 == TX Byte 0 ==
6467 17:16:35.992443 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6468 17:16:35.995902 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6469 17:16:35.999337 == TX Byte 1 ==
6470 17:16:36.002664 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6471 17:16:36.005414 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6472 17:16:36.005498
6473 17:16:36.009064 [DATLAT]
6474 17:16:36.009144 Freq=400, CH0 RK0
6475 17:16:36.009209
6476 17:16:36.012639 DATLAT Default: 0xf
6477 17:16:36.012721 0, 0xFFFF, sum = 0
6478 17:16:36.015364 1, 0xFFFF, sum = 0
6479 17:16:36.015447 2, 0xFFFF, sum = 0
6480 17:16:36.018724 3, 0xFFFF, sum = 0
6481 17:16:36.018804 4, 0xFFFF, sum = 0
6482 17:16:36.022152 5, 0xFFFF, sum = 0
6483 17:16:36.022235 6, 0xFFFF, sum = 0
6484 17:16:36.025684 7, 0xFFFF, sum = 0
6485 17:16:36.025765 8, 0xFFFF, sum = 0
6486 17:16:36.028362 9, 0xFFFF, sum = 0
6487 17:16:36.028446 10, 0xFFFF, sum = 0
6488 17:16:36.031832
6489 17:16:36.031912 11, 0xFFFF, sum = 0
6490 17:16:36.035148 12, 0xFFFF, sum = 0
6491 17:16:36.035232 13, 0x0, sum = 1
6492 17:16:36.038512 14, 0x0, sum = 2
6493 17:16:36.038594 15, 0x0, sum = 3
6494 17:16:36.038661 16, 0x0, sum = 4
6495 17:16:36.041949
6496 17:16:36.042029 best_step = 14
6497 17:16:36.042097
6498 17:16:36.042162 ==
6499 17:16:36.044723 Dram Type= 6, Freq= 0, CH_0, rank 0
6500 17:16:36.048088 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6501 17:16:36.048195 ==
6502 17:16:36.051538 RX Vref Scan: 1
6503 17:16:36.051616
6504 17:16:36.054977 RX Vref 0 -> 0, step: 1
6505 17:16:36.055054
6506 17:16:36.055126 RX Delay -359 -> 252, step: 8
6507 17:16:36.055188
6508 17:16:36.058388
6509 17:16:36.058469 Set Vref, RX VrefLevel [Byte0]: 57
6510 17:16:36.061120 [Byte1]: 58
6511 17:16:36.067350
6512 17:16:36.067435 Final RX Vref Byte 0 = 57 to rank0
6513 17:16:36.070021 Final RX Vref Byte 1 = 58 to rank0
6514 17:16:36.073609 Final RX Vref Byte 0 = 57 to rank1
6515 17:16:36.076964 Final RX Vref Byte 1 = 58 to rank1==
6516 17:16:36.080399 Dram Type= 6, Freq= 0, CH_0, rank 0
6517 17:16:36.086600 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6518 17:16:36.086684 ==
6519 17:16:36.086752 DQS Delay:
6520 17:16:36.090184 DQS0 = 44, DQS1 = 60
6521 17:16:36.090263 DQM Delay:
6522 17:16:36.090331 DQM0 = 11, DQM1 = 16
6523 17:16:36.093565 DQ Delay:
6524 17:16:36.096761 DQ0 =12, DQ1 =12, DQ2 =8, DQ3 =4
6525 17:16:36.100072 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =20
6526 17:16:36.100152 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6527 17:16:36.106699 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6528 17:16:36.106784
6529 17:16:36.106853
6530 17:16:36.112959 [DQSOSCAuto] RK0, (LSB)MR18= 0x9487, (MSB)MR19= 0xc0c, tDQSOscB0 = 392 ps tDQSOscB1 = 391 ps
6531 17:16:36.116313 CH0 RK0: MR19=C0C, MR18=9487
6532 17:16:36.123036 CH0_RK0: MR19=0xC0C, MR18=0x9487, DQSOSC=391, MR23=63, INC=386, DEC=257
6533 17:16:36.123119 ==
6534 17:16:36.126387 Dram Type= 6, Freq= 0, CH_0, rank 1
6535 17:16:36.129728 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6536 17:16:36.129807 ==
6537 17:16:36.132509 [Gating] SW mode calibration
6538 17:16:36.139311 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6539 17:16:36.146202 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6540 17:16:36.149566 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6541 17:16:36.152382 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6542 17:16:36.159262 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6543 17:16:36.162622 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6544 17:16:36.166038 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6545 17:16:36.172184 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6546 17:16:36.175530 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6547 17:16:36.178798 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6548 17:16:36.182124
6549 17:16:36.185450 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6550 17:16:36.188845 Total UI for P1: 0, mck2ui 16
6551 17:16:36.192232 best dqsien dly found for B0: ( 0, 14, 24)
6552 17:16:36.194985 Total UI for P1: 0, mck2ui 16
6553 17:16:36.198474 best dqsien dly found for B1: ( 0, 14, 24)
6554 17:16:36.201943 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6555 17:16:36.205336 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6556 17:16:36.205422
6557 17:16:36.208009 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6558 17:16:36.211485 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6559 17:16:36.215028 [Gating] SW calibration Done
6560 17:16:36.215105 ==
6561 17:16:36.218006 Dram Type= 6, Freq= 0, CH_0, rank 1
6562 17:16:36.221482 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6563 17:16:36.224877 ==
6564 17:16:36.224956 RX Vref Scan: 0
6565 17:16:36.225035
6566 17:16:36.228175 RX Vref 0 -> 0, step: 1
6567 17:16:36.228255
6568 17:16:36.231081 RX Delay -410 -> 252, step: 16
6569 17:16:36.234475 iDelay=230, Bit 0, Center -27 (-266 ~ 213) 480
6570 17:16:36.237911 iDelay=230, Bit 1, Center -19 (-266 ~ 229) 496
6571 17:16:36.241134 iDelay=230, Bit 2, Center -35 (-282 ~ 213) 496
6572 17:16:36.244470
6573 17:16:36.247286 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6574 17:16:36.250573 iDelay=230, Bit 4, Center -27 (-266 ~ 213) 480
6575 17:16:36.254050 iDelay=230, Bit 5, Center -35 (-282 ~ 213) 496
6576 17:16:36.260819 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6577 17:16:36.264285 iDelay=230, Bit 7, Center -19 (-266 ~ 229) 496
6578 17:16:36.267722 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6579 17:16:36.270362 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6580 17:16:36.277384 iDelay=230, Bit 10, Center -43 (-298 ~ 213) 512
6581 17:16:36.280164 iDelay=230, Bit 11, Center -51 (-298 ~ 197) 496
6582 17:16:36.283492 iDelay=230, Bit 12, Center -35 (-282 ~ 213) 496
6583 17:16:36.286945 iDelay=230, Bit 13, Center -35 (-282 ~ 213) 496
6584 17:16:36.290363
6585 17:16:36.293134 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6586 17:16:36.296467 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6587 17:16:36.296543 ==
6588 17:16:36.299846 Dram Type= 6, Freq= 0, CH_0, rank 1
6589 17:16:36.303255 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6590 17:16:36.306581 ==
6591 17:16:36.306662 DQS Delay:
6592 17:16:36.306727 DQS0 = 35, DQS1 = 51
6593 17:16:36.309787 DQM Delay:
6594 17:16:36.309869 DQM0 = 8, DQM1 = 9
6595 17:16:36.313251 DQ Delay:
6596 17:16:36.313333 DQ0 =8, DQ1 =16, DQ2 =0, DQ3 =0
6597 17:16:36.316757 DQ4 =8, DQ5 =0, DQ6 =16, DQ7 =16
6598 17:16:36.319424 DQ8 =0, DQ9 =0, DQ10 =8, DQ11 =0
6599 17:16:36.322862 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6600 17:16:36.322956
6601 17:16:36.323021
6602 17:16:36.323080 ==
6603 17:16:36.326188 Dram Type= 6, Freq= 0, CH_0, rank 1
6604 17:16:36.332949 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6605 17:16:36.333027 ==
6606 17:16:36.333092
6607 17:16:36.333160
6608 17:16:36.336342 TX Vref Scan disable
6609 17:16:36.336424 == TX Byte 0 ==
6610 17:16:36.339658 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6611 17:16:36.345741 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6612 17:16:36.345832 == TX Byte 1 ==
6613 17:16:36.349285 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6614 17:16:36.355455 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6615 17:16:36.355545 ==
6616 17:16:36.358844 Dram Type= 6, Freq= 0, CH_0, rank 1
6617 17:16:36.362252 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6618 17:16:36.362330 ==
6619 17:16:36.362401
6620 17:16:36.362470
6621 17:16:36.365512 TX Vref Scan disable
6622 17:16:36.365588 == TX Byte 0 ==
6623 17:16:36.368911 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6624 17:16:36.375588 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6625 17:16:36.375675 == TX Byte 1 ==
6626 17:16:36.378288 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
6627 17:16:36.385458 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
6628 17:16:36.385538
6629 17:16:36.385607 [DATLAT]
6630 17:16:36.385678 Freq=400, CH0 RK1
6631 17:16:36.388775
6632 17:16:36.388858
6633 17:16:36.388931 DATLAT Default: 0xe
6634 17:16:36.391395 0, 0xFFFF, sum = 0
6635 17:16:36.391488 1, 0xFFFF, sum = 0
6636 17:16:36.395015 2, 0xFFFF, sum = 0
6637 17:16:36.395094 3, 0xFFFF, sum = 0
6638 17:16:36.398308 4, 0xFFFF, sum = 0
6639 17:16:36.398430 5, 0xFFFF, sum = 0
6640 17:16:36.401078 6, 0xFFFF, sum = 0
6641 17:16:36.401165 7, 0xFFFF, sum = 0
6642 17:16:36.404399 8, 0xFFFF, sum = 0
6643 17:16:36.404482 9, 0xFFFF, sum = 0
6644 17:16:36.407782 10, 0xFFFF, sum = 0
6645 17:16:36.411006 11, 0xFFFF, sum = 0
6646 17:16:36.411092 12, 0xFFFF, sum = 0
6647 17:16:36.414396 13, 0x0, sum = 1
6648 17:16:36.414471 14, 0x0, sum = 2
6649 17:16:36.414536 15, 0x0, sum = 3
6650 17:16:36.417842
6651 17:16:36.417915 16, 0x0, sum = 4
6652 17:16:36.417978 best_step = 14
6653 17:16:36.418037
6654 17:16:36.421324 ==
6655 17:16:36.421406 Dram Type= 6, Freq= 0, CH_0, rank 1
6656 17:16:36.424604
6657 17:16:36.427965 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6658 17:16:36.428051 ==
6659 17:16:36.428118 RX Vref Scan: 0
6660 17:16:36.428187
6661 17:16:36.430509 RX Vref 0 -> 0, step: 1
6662 17:16:36.430583
6663 17:16:36.434021 RX Delay -343 -> 252, step: 8
6664 17:16:36.440847 iDelay=217, Bit 0, Center -36 (-271 ~ 200) 472
6665 17:16:36.444233 iDelay=217, Bit 1, Center -32 (-271 ~ 208) 480
6666 17:16:36.447561 iDelay=217, Bit 2, Center -40 (-279 ~ 200) 480
6667 17:16:36.454131 iDelay=217, Bit 3, Center -36 (-271 ~ 200) 472
6668 17:16:36.457604 iDelay=217, Bit 4, Center -32 (-271 ~ 208) 480
6669 17:16:36.460882 iDelay=217, Bit 5, Center -44 (-287 ~ 200) 488
6670 17:16:36.464221 iDelay=217, Bit 6, Center -24 (-263 ~ 216) 480
6671 17:16:36.470678 iDelay=217, Bit 7, Center -32 (-271 ~ 208) 480
6672 17:16:36.474234 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
6673 17:16:36.476896 iDelay=217, Bit 9, Center -60 (-303 ~ 184) 488
6674 17:16:36.480275 iDelay=217, Bit 10, Center -44 (-287 ~ 200) 488
6675 17:16:36.486767 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
6676 17:16:36.490094 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
6677 17:16:36.493543 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
6678 17:16:36.500342 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
6679 17:16:36.503635 iDelay=217, Bit 15, Center -36 (-279 ~ 208) 488
6680 17:16:36.503718 ==
6681 17:16:36.506342 Dram Type= 6, Freq= 0, CH_0, rank 1
6682 17:16:36.510293 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6683 17:16:36.510375 ==
6684 17:16:36.513597 DQS Delay:
6685 17:16:36.513677 DQS0 = 44, DQS1 = 60
6686 17:16:36.513740 DQM Delay:
6687 17:16:36.516379 DQM0 = 9, DQM1 = 16
6688 17:16:36.516461 DQ Delay:
6689 17:16:36.519833 DQ0 =8, DQ1 =12, DQ2 =4, DQ3 =8
6690 17:16:36.523168 DQ4 =12, DQ5 =0, DQ6 =20, DQ7 =12
6691 17:16:36.526555 DQ8 =8, DQ9 =0, DQ10 =16, DQ11 =8
6692 17:16:36.529976 DQ12 =24, DQ13 =24, DQ14 =24, DQ15 =24
6693 17:16:36.530057
6694 17:16:36.530120
6695 17:16:36.539466 [DQSOSCAuto] RK1, (LSB)MR18= 0x8a83, (MSB)MR19= 0xc0c, tDQSOscB0 = 393 ps tDQSOscB1 = 392 ps
6696 17:16:36.539549 CH0 RK1: MR19=C0C, MR18=8A83
6697 17:16:36.546331 CH0_RK1: MR19=0xC0C, MR18=0x8A83, DQSOSC=392, MR23=63, INC=384, DEC=256
6698 17:16:36.549658 [RxdqsGatingPostProcess] freq 400
6699 17:16:36.555878 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
6700 17:16:36.559149 best DQS0 dly(2T, 0.5T) = (0, 10)
6701 17:16:36.562491 best DQS1 dly(2T, 0.5T) = (0, 10)
6702 17:16:36.565818 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6703 17:16:36.569180 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6704 17:16:36.572396 best DQS0 dly(2T, 0.5T) = (0, 10)
6705 17:16:36.575669 best DQS1 dly(2T, 0.5T) = (0, 10)
6706 17:16:36.579052 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
6707 17:16:36.582343 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
6708 17:16:36.585719 Pre-setting of DQS Precalculation
6709 17:16:36.589076 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
6710 17:16:36.589160 ==
6711 17:16:36.591669 Dram Type= 6, Freq= 0, CH_1, rank 0
6712 17:16:36.595143 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6713 17:16:36.598548 ==
6714 17:16:36.601919 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6715 17:16:36.607893 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=37, u1VrefScanEnd=37
6716 17:16:36.611892 [CA 0] Center 36 (8~64) winsize 57
6717 17:16:36.614511 [CA 1] Center 36 (8~64) winsize 57
6718 17:16:36.618510 [CA 2] Center 36 (8~64) winsize 57
6719 17:16:36.621216 [CA 3] Center 36 (8~64) winsize 57
6720 17:16:36.624736 [CA 4] Center 36 (8~64) winsize 57
6721 17:16:36.627472 [CA 5] Center 36 (8~64) winsize 57
6722 17:16:36.627555
6723 17:16:36.630871 [CmdBusTrainingLP45] Vref(ca) range 1: 37
6724 17:16:36.630995
6725 17:16:36.634119 [CATrainingPosCal] consider 1 rank data
6726 17:16:36.637614 u2DelayCellTimex100 = 270/100 ps
6727 17:16:36.640900 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6728 17:16:36.644265 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6729 17:16:36.647512 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6730 17:16:36.650993 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6731 17:16:36.654337 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6732 17:16:36.660428 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6733 17:16:36.660512
6734 17:16:36.663840 CA PerBit enable=1, Macro0, CA PI delay=36
6735 17:16:36.663923
6736 17:16:36.667321 [CBTSetCACLKResult] CA Dly = 36
6737 17:16:36.667404 CS Dly: 1 (0~32)
6738 17:16:36.667469 ==
6739 17:16:36.670499 Dram Type= 6, Freq= 0, CH_1, rank 1
6740 17:16:36.673903 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6741 17:16:36.677439 ==
6742 17:16:36.680611 pi_start=-16, pi_end=95, pi_step=8, new_cbt_mode=1, autok=0
6743 17:16:36.687238 u1VRangeStart=1, u1VRangeEnd=1, u1VrefScanStart=35, u1VrefScanEnd=35
6744 17:16:36.690560 [CA 0] Center 36 (8~64) winsize 57
6745 17:16:36.693215 [CA 1] Center 36 (8~64) winsize 57
6746 17:16:36.696578 [CA 2] Center 36 (8~64) winsize 57
6747 17:16:36.699853 [CA 3] Center 36 (8~64) winsize 57
6748 17:16:36.703106 [CA 4] Center 36 (8~64) winsize 57
6749 17:16:36.706586 [CA 5] Center 36 (8~64) winsize 57
6750 17:16:36.706670
6751 17:16:36.709824 [CmdBusTrainingLP45] Vref(ca) range 1: 35
6752 17:16:36.709908
6753 17:16:36.713170 [CATrainingPosCal] consider 2 rank data
6754 17:16:36.716421 u2DelayCellTimex100 = 270/100 ps
6755 17:16:36.719524 CA0 delay=36 (8~64),Diff = 0 PI (0 cell)
6756 17:16:36.722951 CA1 delay=36 (8~64),Diff = 0 PI (0 cell)
6757 17:16:36.726328 CA2 delay=36 (8~64),Diff = 0 PI (0 cell)
6758 17:16:36.729686 CA3 delay=36 (8~64),Diff = 0 PI (0 cell)
6759 17:16:36.733089 CA4 delay=36 (8~64),Diff = 0 PI (0 cell)
6760 17:16:36.739664 CA5 delay=36 (8~64),Diff = 0 PI (0 cell)
6761 17:16:36.739747
6762 17:16:36.742413 CA PerBit enable=1, Macro0, CA PI delay=36
6763 17:16:36.742497
6764 17:16:36.746322 [CBTSetCACLKResult] CA Dly = 36
6765 17:16:36.746405 CS Dly: 1 (0~32)
6766 17:16:36.746470
6767 17:16:36.748984 ----->DramcWriteLeveling(PI) begin...
6768 17:16:36.749069 ==
6769 17:16:36.752390 Dram Type= 6, Freq= 0, CH_1, rank 0
6770 17:16:36.759108 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6771 17:16:36.759196 ==
6772 17:16:36.762446 Write leveling (Byte 0): 40 => 8
6773 17:16:36.762529 Write leveling (Byte 1): 40 => 8
6774 17:16:36.765853 DramcWriteLeveling(PI) end<-----
6775 17:16:36.765936
6776 17:16:36.766002 ==
6777 17:16:36.768590
6778 17:16:36.768674 Dram Type= 6, Freq= 0, CH_1, rank 0
6779 17:16:36.775247 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6780 17:16:36.775331 ==
6781 17:16:36.778561 [Gating] SW mode calibration
6782 17:16:36.785261 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6783 17:16:36.788618 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6784 17:16:36.795204 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6785 17:16:36.798582 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6786 17:16:36.801959 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6787 17:16:36.807999 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6788 17:16:36.811433 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6789 17:16:36.814576 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6790 17:16:36.821242 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6791 17:16:36.824518 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6792 17:16:36.827946 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6793 17:16:36.831276 Total UI for P1: 0, mck2ui 16
6794 17:16:36.834586 best dqsien dly found for B0: ( 0, 14, 24)
6795 17:16:36.837305 Total UI for P1: 0, mck2ui 16
6796 17:16:36.840639 best dqsien dly found for B1: ( 0, 14, 24)
6797 17:16:36.847458 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6798 17:16:36.850797 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6799 17:16:36.850972
6800 17:16:36.854158 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6801 17:16:36.857119 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6802 17:16:36.860785 [Gating] SW calibration Done
6803 17:16:36.860926 ==
6804 17:16:36.863972 Dram Type= 6, Freq= 0, CH_1, rank 0
6805 17:16:36.867501 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6806 17:16:36.867669 ==
6807 17:16:36.870056 RX Vref Scan: 0
6808 17:16:36.870173
6809 17:16:36.870273 RX Vref 0 -> 0, step: 1
6810 17:16:36.870373
6811 17:16:36.873335 RX Delay -410 -> 252, step: 16
6812 17:16:36.879991 iDelay=230, Bit 0, Center -19 (-266 ~ 229) 496
6813 17:16:36.883320 iDelay=230, Bit 1, Center -35 (-282 ~ 213) 496
6814 17:16:36.886685 iDelay=230, Bit 2, Center -43 (-282 ~ 197) 480
6815 17:16:36.890013 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6816 17:16:36.896793 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6817 17:16:36.900019 iDelay=230, Bit 5, Center -19 (-266 ~ 229) 496
6818 17:16:36.903495 iDelay=230, Bit 6, Center -19 (-266 ~ 229) 496
6819 17:16:36.906352 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6820 17:16:36.912961 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6821 17:16:36.916327 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6822 17:16:36.919851 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6823 17:16:36.926358 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6824 17:16:36.929190 iDelay=230, Bit 12, Center -19 (-266 ~ 229) 496
6825 17:16:36.932767 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6826 17:16:36.936082 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6827 17:16:36.942358 iDelay=230, Bit 15, Center -35 (-282 ~ 213) 496
6828 17:16:36.942509 ==
6829 17:16:36.945679 Dram Type= 6, Freq= 0, CH_1, rank 0
6830 17:16:36.949105 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6831 17:16:36.949202 ==
6832 17:16:36.949290 DQS Delay:
6833 17:16:36.952325 DQS0 = 43, DQS1 = 51
6834 17:16:36.952414 DQM Delay:
6835 17:16:36.955550 DQM0 = 13, DQM1 = 14
6836 17:16:36.955627 DQ Delay:
6837 17:16:36.958971 DQ0 =24, DQ1 =8, DQ2 =0, DQ3 =8
6838 17:16:36.962358 DQ4 =8, DQ5 =24, DQ6 =24, DQ7 =8
6839 17:16:36.965191 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6840 17:16:36.968710 DQ12 =32, DQ13 =24, DQ14 =16, DQ15 =16
6841 17:16:36.968807
6842 17:16:36.968925
6843 17:16:36.969027 ==
6844 17:16:36.971918 Dram Type= 6, Freq= 0, CH_1, rank 0
6845 17:16:36.975309 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6846 17:16:36.975414 ==
6847 17:16:36.978548
6848 17:16:36.978655
6849 17:16:36.978745
6850 17:16:36.978839 TX Vref Scan disable
6851 17:16:36.982122 == TX Byte 0 ==
6852 17:16:36.985274 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6853 17:16:36.988182 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6854 17:16:36.991678 == TX Byte 1 ==
6855 17:16:36.995072 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6856 17:16:36.998278 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6857 17:16:36.998389 ==
6858 17:16:37.001626 Dram Type= 6, Freq= 0, CH_1, rank 0
6859 17:16:37.008317 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6860 17:16:37.008415 ==
6861 17:16:37.008486
6862 17:16:37.008548
6863 17:16:37.008607 TX Vref Scan disable
6864 17:16:37.011077 == TX Byte 0 ==
6865 17:16:37.014546 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6866 17:16:37.017889 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6867 17:16:37.020934 == TX Byte 1 ==
6868 17:16:37.024379 Update DQ dly =580 (4 ,2, 4) DQ OEN =(3 ,3)
6869 17:16:37.027786 Update DQM dly =580 (4 ,2, 4) DQM OEN =(3 ,3)
6870 17:16:37.027871
6871 17:16:37.031033 [DATLAT]
6872 17:16:37.031117 Freq=400, CH1 RK0
6873 17:16:37.031184
6874 17:16:37.034300 DATLAT Default: 0xf
6875 17:16:37.034384 0, 0xFFFF, sum = 0
6876 17:16:37.037566 1, 0xFFFF, sum = 0
6877 17:16:37.037656 2, 0xFFFF, sum = 0
6878 17:16:37.040931 3, 0xFFFF, sum = 0
6879 17:16:37.041017 4, 0xFFFF, sum = 0
6880 17:16:37.044255 5, 0xFFFF, sum = 0
6881 17:16:37.044340 6, 0xFFFF, sum = 0
6882 17:16:37.047575
6883 17:16:37.047656 7, 0xFFFF, sum = 0
6884 17:16:37.051015 8, 0xFFFF, sum = 0
6885 17:16:37.051104 9, 0xFFFF, sum = 0
6886 17:16:37.054162 10, 0xFFFF, sum = 0
6887 17:16:37.054252 11, 0xFFFF, sum = 0
6888 17:16:37.057474 12, 0xFFFF, sum = 0
6889 17:16:37.057575 13, 0x0, sum = 1
6890 17:16:37.060235 14, 0x0, sum = 2
6891 17:16:37.060361 15, 0x0, sum = 3
6892 17:16:37.063675 16, 0x0, sum = 4
6893 17:16:37.063777 best_step = 14
6894 17:16:37.063853
6895 17:16:37.063932 ==
6896 17:16:37.067102 Dram Type= 6, Freq= 0, CH_1, rank 0
6897 17:16:37.070694 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6898 17:16:37.073368 ==
6899 17:16:37.073461 RX Vref Scan: 1
6900 17:16:37.073531
6901 17:16:37.076942 RX Vref 0 -> 0, step: 1
6902 17:16:37.077033
6903 17:16:37.080272 RX Delay -343 -> 252, step: 8
6904 17:16:37.080358
6905 17:16:37.083898 Set Vref, RX VrefLevel [Byte0]: 53
6906 17:16:37.086623 [Byte1]: 53
6907 17:16:37.086727
6908 17:16:37.089812 Final RX Vref Byte 0 = 53 to rank0
6909 17:16:37.093390 Final RX Vref Byte 1 = 53 to rank0
6910 17:16:37.096862 Final RX Vref Byte 0 = 53 to rank1
6911 17:16:37.099953 Final RX Vref Byte 1 = 53 to rank1==
6912 17:16:37.103081 Dram Type= 6, Freq= 0, CH_1, rank 0
6913 17:16:37.106541 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6914 17:16:37.109583 ==
6915 17:16:37.109681 DQS Delay:
6916 17:16:37.109749 DQS0 = 44, DQS1 = 52
6917 17:16:37.112890 DQM Delay:
6918 17:16:37.112976 DQM0 = 9, DQM1 = 10
6919 17:16:37.116195 DQ Delay:
6920 17:16:37.116282 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
6921 17:16:37.119431 DQ4 =4, DQ5 =16, DQ6 =20, DQ7 =4
6922 17:16:37.122643 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =4
6923 17:16:37.126001 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =16
6924 17:16:37.126109
6925 17:16:37.126184
6926 17:16:37.136220 [DQSOSCAuto] RK0, (LSB)MR18= 0x688f, (MSB)MR19= 0xc0c, tDQSOscB0 = 391 ps tDQSOscB1 = 396 ps
6927 17:16:37.139188 CH1 RK0: MR19=C0C, MR18=688F
6928 17:16:37.145810 CH1_RK0: MR19=0xC0C, MR18=0x688F, DQSOSC=391, MR23=63, INC=386, DEC=257
6929 17:16:37.145926 ==
6930 17:16:37.149343 Dram Type= 6, Freq= 0, CH_1, rank 1
6931 17:16:37.152062 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6932 17:16:37.152171 ==
6933 17:16:37.155484 [Gating] SW mode calibration
6934 17:16:37.162188 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 16 , u4TDQSCK_UI_min 1, 1:4ExtraMCK 1
6935 17:16:37.168869 RX_Path_delay_UI(31) -3 - DQSINCTL_UI(20) = u1StartUI(11)
6936 17:16:37.172102 0 11 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6937 17:16:37.174883 0 11 16 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
6938 17:16:37.181410 0 12 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6939 17:16:37.185367 0 12 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6940 17:16:37.188030 0 13 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6941 17:16:37.194963 0 13 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6942 17:16:37.198329 0 14 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6943 17:16:37.201446 0 14 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
6944 17:16:37.207925 0 15 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
6945 17:16:37.208043 Total UI for P1: 0, mck2ui 16
6946 17:16:37.214696 best dqsien dly found for B0: ( 0, 14, 24)
6947 17:16:37.214801 Total UI for P1: 0, mck2ui 16
6948 17:16:37.221417 best dqsien dly found for B1: ( 0, 14, 24)
6949 17:16:37.224599 best DQS0 dly(MCK, UI, PI) = (0, 14, 24)
6950 17:16:37.227909 best DQS1 dly(MCK, UI, PI) = (0, 14, 24)
6951 17:16:37.228002
6952 17:16:37.230567 best DQS0 P1 dly(MCK, UI, PI) = (1, 0, 24)
6953 17:16:37.233905 best DQS1 P1 dly(MCK, UI, PI) = (1, 0, 24)
6954 17:16:37.237327 [Gating] SW calibration Done
6955 17:16:37.237419 ==
6956 17:16:37.240609 Dram Type= 6, Freq= 0, CH_1, rank 1
6957 17:16:37.244050 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6958 17:16:37.244134 ==
6959 17:16:37.247365 RX Vref Scan: 0
6960 17:16:37.247444
6961 17:16:37.250814 RX Vref 0 -> 0, step: 1
6962 17:16:37.250903
6963 17:16:37.250970 RX Delay -410 -> 252, step: 16
6964 17:16:37.257314 iDelay=230, Bit 0, Center -27 (-282 ~ 229) 512
6965 17:16:37.260396 iDelay=230, Bit 1, Center -43 (-298 ~ 213) 512
6966 17:16:37.263703 iDelay=230, Bit 2, Center -43 (-298 ~ 213) 512
6967 17:16:37.270121 iDelay=230, Bit 3, Center -35 (-282 ~ 213) 496
6968 17:16:37.273772 iDelay=230, Bit 4, Center -35 (-282 ~ 213) 496
6969 17:16:37.277064 iDelay=230, Bit 5, Center -27 (-282 ~ 229) 512
6970 17:16:37.280468 iDelay=230, Bit 6, Center -27 (-282 ~ 229) 512
6971 17:16:37.286576 iDelay=230, Bit 7, Center -35 (-282 ~ 213) 496
6972 17:16:37.289990 iDelay=230, Bit 8, Center -51 (-298 ~ 197) 496
6973 17:16:37.293504 iDelay=230, Bit 9, Center -51 (-298 ~ 197) 496
6974 17:16:37.296377 iDelay=230, Bit 10, Center -35 (-282 ~ 213) 496
6975 17:16:37.303119 iDelay=230, Bit 11, Center -43 (-298 ~ 213) 512
6976 17:16:37.306519 iDelay=230, Bit 12, Center -27 (-282 ~ 229) 512
6977 17:16:37.309223 iDelay=230, Bit 13, Center -27 (-282 ~ 229) 512
6978 17:16:37.316123 iDelay=230, Bit 14, Center -35 (-282 ~ 213) 496
6979 17:16:37.319542 iDelay=230, Bit 15, Center -27 (-282 ~ 229) 512
6980 17:16:37.319644 ==
6981 17:16:37.322867 Dram Type= 6, Freq= 0, CH_1, rank 1
6982 17:16:37.325962 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6983 17:16:37.326062 ==
6984 17:16:37.329338 DQS Delay:
6985 17:16:37.329423 DQS0 = 43, DQS1 = 51
6986 17:16:37.332665 DQM Delay:
6987 17:16:37.332755 DQM0 = 9, DQM1 = 14
6988 17:16:37.332830 DQ Delay:
6989 17:16:37.336088 DQ0 =16, DQ1 =0, DQ2 =0, DQ3 =8
6990 17:16:37.338874 DQ4 =8, DQ5 =16, DQ6 =16, DQ7 =8
6991 17:16:37.342212 DQ8 =0, DQ9 =0, DQ10 =16, DQ11 =8
6992 17:16:37.345404 DQ12 =24, DQ13 =24, DQ14 =16, DQ15 =24
6993 17:16:37.345489
6994 17:16:37.345577
6995 17:16:37.345642 ==
6996 17:16:37.348863 Dram Type= 6, Freq= 0, CH_1, rank 1
6997 17:16:37.355631 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
6998 17:16:37.355721 ==
6999 17:16:37.355809
7000 17:16:37.355896
7001 17:16:37.355966 TX Vref Scan disable
7002 17:16:37.358715 == TX Byte 0 ==
7003 17:16:37.362348 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7004 17:16:37.365641 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7005 17:16:37.368997 == TX Byte 1 ==
7006 17:16:37.371540 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7007 17:16:37.375082 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7008 17:16:37.375173 ==
7009 17:16:37.378252
7010 17:16:37.378340 Dram Type= 6, Freq= 0, CH_1, rank 1
7011 17:16:37.385243 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7012 17:16:37.385335 ==
7013 17:16:37.385403
7014 17:16:37.385482
7015 17:16:37.387879 TX Vref Scan disable
7016 17:16:37.387966 == TX Byte 0 ==
7017 17:16:37.391239 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7018 17:16:37.398201 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7019 17:16:37.398311 == TX Byte 1 ==
7020 17:16:37.401183 Update DQ dly =583 (4 ,2, 7) DQ OEN =(3 ,3)
7021 17:16:37.407592 Update DQM dly =583 (4 ,2, 7) DQM OEN =(3 ,3)
7022 17:16:37.407700
7023 17:16:37.407773 [DATLAT]
7024 17:16:37.407838 Freq=400, CH1 RK1
7025 17:16:37.407907
7026 17:16:37.410876 DATLAT Default: 0xe
7027 17:16:37.410972 0, 0xFFFF, sum = 0
7028 17:16:37.414262
7029 17:16:37.414353 1, 0xFFFF, sum = 0
7030 17:16:37.417452 2, 0xFFFF, sum = 0
7031 17:16:37.417544 3, 0xFFFF, sum = 0
7032 17:16:37.421029 4, 0xFFFF, sum = 0
7033 17:16:37.421120 5, 0xFFFF, sum = 0
7034 17:16:37.424332 6, 0xFFFF, sum = 0
7035 17:16:37.424420 7, 0xFFFF, sum = 0
7036 17:16:37.427543 8, 0xFFFF, sum = 0
7037 17:16:37.427630 9, 0xFFFF, sum = 0
7038 17:16:37.430821 10, 0xFFFF, sum = 0
7039 17:16:37.430916 11, 0xFFFF, sum = 0
7040 17:16:37.434263 12, 0xFFFF, sum = 0
7041 17:16:37.434350 13, 0x0, sum = 1
7042 17:16:37.437666 14, 0x0, sum = 2
7043 17:16:37.437756 15, 0x0, sum = 3
7044 17:16:37.440453 16, 0x0, sum = 4
7045 17:16:37.440541 best_step = 14
7046 17:16:37.440608
7047 17:16:37.440670 ==
7048 17:16:37.443919 Dram Type= 6, Freq= 0, CH_1, rank 1
7049 17:16:37.450807 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7050 17:16:37.450906 ==
7051 17:16:37.450976 RX Vref Scan: 0
7052 17:16:37.451039
7053 17:16:37.453934 RX Vref 0 -> 0, step: 1
7054 17:16:37.454020
7055 17:16:37.456784 RX Delay -343 -> 252, step: 8
7056 17:16:37.463606 iDelay=217, Bit 0, Center -32 (-279 ~ 216) 496
7057 17:16:37.466964 iDelay=217, Bit 1, Center -40 (-287 ~ 208) 496
7058 17:16:37.470205 iDelay=217, Bit 2, Center -48 (-295 ~ 200) 496
7059 17:16:37.473780 iDelay=217, Bit 3, Center -40 (-287 ~ 208) 496
7060 17:16:37.479976 iDelay=217, Bit 4, Center -40 (-287 ~ 208) 496
7061 17:16:37.483402 iDelay=217, Bit 5, Center -28 (-271 ~ 216) 488
7062 17:16:37.486670 iDelay=217, Bit 6, Center -28 (-271 ~ 216) 488
7063 17:16:37.490056 iDelay=217, Bit 7, Center -40 (-287 ~ 208) 496
7064 17:16:37.492866
7065 17:16:37.496306 iDelay=217, Bit 8, Center -52 (-295 ~ 192) 488
7066 17:16:37.499584 iDelay=217, Bit 9, Center -52 (-295 ~ 192) 488
7067 17:16:37.502981 iDelay=217, Bit 10, Center -40 (-287 ~ 208) 496
7068 17:16:37.509535 iDelay=217, Bit 11, Center -52 (-295 ~ 192) 488
7069 17:16:37.512787 iDelay=217, Bit 12, Center -36 (-279 ~ 208) 488
7070 17:16:37.516164 iDelay=217, Bit 13, Center -36 (-279 ~ 208) 488
7071 17:16:37.518992 iDelay=217, Bit 14, Center -36 (-279 ~ 208) 488
7072 17:16:37.525707 iDelay=217, Bit 15, Center -32 (-279 ~ 216) 496
7073 17:16:37.525809 ==
7074 17:16:37.529117 Dram Type= 6, Freq= 0, CH_1, rank 1
7075 17:16:37.532445 fsp= 0, odt_onoff= 0, Byte mode= 1, DivMode= 2
7076 17:16:37.532553 ==
7077 17:16:37.535909 DQS Delay:
7078 17:16:37.535996 DQS0 = 48, DQS1 = 52
7079 17:16:37.536073 DQM Delay:
7080 17:16:37.538823 DQM0 = 11, DQM1 = 10
7081 17:16:37.538917 DQ Delay:
7082 17:16:37.542173 DQ0 =16, DQ1 =8, DQ2 =0, DQ3 =8
7083 17:16:37.545545 DQ4 =8, DQ5 =20, DQ6 =20, DQ7 =8
7084 17:16:37.548911 DQ8 =0, DQ9 =0, DQ10 =12, DQ11 =0
7085 17:16:37.551881 DQ12 =16, DQ13 =16, DQ14 =16, DQ15 =20
7086 17:16:37.551966
7087 17:16:37.552041
7088 17:16:37.561825 [DQSOSCAuto] RK1, (LSB)MR18= 0x78ae, (MSB)MR19= 0xc0c, tDQSOscB0 = 388 ps tDQSOscB1 = 394 ps
7089 17:16:37.561936 CH1 RK1: MR19=C0C, MR18=78AE
7090 17:16:37.568556 CH1_RK1: MR19=0xC0C, MR18=0x78AE, DQSOSC=388, MR23=63, INC=392, DEC=261
7091 17:16:37.571859 [RxdqsGatingPostProcess] freq 400
7092 17:16:37.578433 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
7093 17:16:37.581995 best DQS0 dly(2T, 0.5T) = (0, 10)
7094 17:16:37.584685 best DQS1 dly(2T, 0.5T) = (0, 10)
7095 17:16:37.587981 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7096 17:16:37.591349 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7097 17:16:37.594740 best DQS0 dly(2T, 0.5T) = (0, 10)
7098 17:16:37.597964 best DQS1 dly(2T, 0.5T) = (0, 10)
7099 17:16:37.601142 best DQS0 P1 dly(2T, 0.5T) = (0, 12)
7100 17:16:37.604426 best DQS1 P1 dly(2T, 0.5T) = (0, 12)
7101 17:16:37.608039 Pre-setting of DQS Precalculation
7102 17:16:37.611239 [DualRankRxdatlatCal] RK0: 14, RK1: 14, Final_Datlat 14
7103 17:16:37.617813 sync_frequency_calibration_params sync calibration params of frequency 400 to shu:6
7104 17:16:37.624659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
7105 17:16:37.624746
7106 17:16:37.627317
7107 17:16:37.627435 [Calibration Summary] 800 Mbps
7108 17:16:37.630622 CH 0, Rank 0
7109 17:16:37.630701 SW Impedance : PASS
7110 17:16:37.633833 DUTY Scan : NO K
7111 17:16:37.637138 ZQ Calibration : PASS
7112 17:16:37.637219 Jitter Meter : NO K
7113 17:16:37.640588 CBT Training : PASS
7114 17:16:37.643893 Write leveling : PASS
7115 17:16:37.643976 RX DQS gating : PASS
7116 17:16:37.647175 RX DQ/DQS(RDDQC) : PASS
7117 17:16:37.650496 TX DQ/DQS : PASS
7118 17:16:37.650575 RX DATLAT : PASS
7119 17:16:37.653826 RX DQ/DQS(Engine): PASS
7120 17:16:37.657229 TX OE : NO K
7121 17:16:37.657310 All Pass.
7122 17:16:37.657375
7123 17:16:37.657469 CH 0, Rank 1
7124 17:16:37.660713 SW Impedance : PASS
7125 17:16:37.663345 DUTY Scan : NO K
7126 17:16:37.663422 ZQ Calibration : PASS
7127 17:16:37.666503 Jitter Meter : NO K
7128 17:16:37.670000 CBT Training : PASS
7129 17:16:37.670077 Write leveling : NO K
7130 17:16:37.673159 RX DQS gating : PASS
7131 17:16:37.676438 RX DQ/DQS(RDDQC) : PASS
7132 17:16:37.676515 TX DQ/DQS : PASS
7133 17:16:37.679759 RX DATLAT : PASS
7134 17:16:37.683201 RX DQ/DQS(Engine): PASS
7135 17:16:37.683277 TX OE : NO K
7136 17:16:37.686431 All Pass.
7137 17:16:37.686506
7138 17:16:37.686570 CH 1, Rank 0
7139 17:16:37.689642 SW Impedance : PASS
7140 17:16:37.689717 DUTY Scan : NO K
7141 17:16:37.693080 ZQ Calibration : PASS
7142 17:16:37.696542 Jitter Meter : NO K
7143 17:16:37.696619 CBT Training : PASS
7144 17:16:37.699320 Write leveling : PASS
7145 17:16:37.699396 RX DQS gating : PASS
7146 17:16:37.703330
7147 17:16:37.703408 RX DQ/DQS(RDDQC) : PASS
7148 17:16:37.706176 TX DQ/DQS : PASS
7149 17:16:37.706260 RX DATLAT : PASS
7150 17:16:37.709590 RX DQ/DQS(Engine): PASS
7151 17:16:37.713065 TX OE : NO K
7152 17:16:37.713145 All Pass.
7153 17:16:37.713212
7154 17:16:37.713275 CH 1, Rank 1
7155 17:16:37.716219 SW Impedance : PASS
7156 17:16:37.719609 DUTY Scan : NO K
7157 17:16:37.719689 ZQ Calibration : PASS
7158 17:16:37.722921 Jitter Meter : NO K
7159 17:16:37.726405 CBT Training : PASS
7160 17:16:37.726483 Write leveling : NO K
7161 17:16:37.729114 RX DQS gating : PASS
7162 17:16:37.732519 RX DQ/DQS(RDDQC) : PASS
7163 17:16:37.732596 TX DQ/DQS : PASS
7164 17:16:37.736039 RX DATLAT : PASS
7165 17:16:37.739607 RX DQ/DQS(Engine): PASS
7166 17:16:37.739695 TX OE : NO K
7167 17:16:37.742365 All Pass.
7168 17:16:37.742452
7169 17:16:37.742518 DramC Write-DBI off
7170 17:16:37.745756 PER_BANK_REFRESH: Hybrid Mode
7171 17:16:37.745830 TX_TRACKING: ON
7172 17:16:37.755804 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 44, TRFC_05T 0, TXREFCNT 58, TRFCpb 16, TRFCpb_05T 0
7173 17:16:37.759294 [FAST_K] Save calibration result to emmc
7174 17:16:37.762486 dramc_set_vcore_voltage set vcore to 725000
7175 17:16:37.765861 Read voltage for 1600, 0
7176 17:16:37.765954 Vio18 = 0
7177 17:16:37.768510 Vcore = 725000
7178 17:16:37.768599 Vdram = 0
7179 17:16:37.768666 Vddq = 0
7180 17:16:37.771864 Vmddr = 0
7181 17:16:37.775352 [FAST_K] DramcSave_Time_For_Cal_Init SHU1, femmc_Ready=0
7182 17:16:37.782217 [FAST_K] Bypass_RDDQC 0, Bypass_RXWINDOW=0, Bypass_TXWINDOW=0
7183 17:16:37.784901 MEM_TYPE=3, freq_sel=13
7184 17:16:37.784979 sv_algorithm_assistance_LP4_3733
7185 17:16:37.791703 ============ PULL DRAM RESETB DOWN ============
7186 17:16:37.794943 ========== PULL DRAM RESETB DOWN end =========
7187 17:16:37.798249 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7188 17:16:37.801731 ===================================
7189 17:16:37.804781 LPDDR4 DRAM CONFIGURATION
7190 17:16:37.808327 ===================================
7191 17:16:37.811588 EX_ROW_EN[0] = 0x0
7192 17:16:37.811676 EX_ROW_EN[1] = 0x0
7193 17:16:37.814843 LP4Y_EN = 0x0
7194 17:16:37.814940 WORK_FSP = 0x1
7195 17:16:37.818076 WL = 0x5
7196 17:16:37.818153 RL = 0x5
7197 17:16:37.821268 BL = 0x2
7198 17:16:37.821349 RPST = 0x0
7199 17:16:37.824679 RD_PRE = 0x0
7200 17:16:37.827942 WR_PRE = 0x1
7201 17:16:37.828021 WR_PST = 0x1
7202 17:16:37.831319 DBI_WR = 0x0
7203 17:16:37.831396 DBI_RD = 0x0
7204 17:16:37.834697 OTF = 0x1
7205 17:16:37.837996 ===================================
7206 17:16:37.841290 ===================================
7207 17:16:37.841371 ANA top config
7208 17:16:37.844711 ===================================
7209 17:16:37.847518 DLL_ASYNC_EN = 0
7210 17:16:37.850823 ALL_SLAVE_EN = 0
7211 17:16:37.850937 NEW_RANK_MODE = 1
7212 17:16:37.854178 DLL_IDLE_MODE = 1
7213 17:16:37.857318 LP45_APHY_COMB_EN = 1
7214 17:16:37.860640 TX_ODT_DIS = 0
7215 17:16:37.864050 NEW_8X_MODE = 1
7216 17:16:37.867523 ===================================
7217 17:16:37.870661 ===================================
7218 17:16:37.870740 data_rate = 3200
7219 17:16:37.874112 CKR = 1
7220 17:16:37.877453 DQ_P2S_RATIO = 8
7221 17:16:37.880910 ===================================
7222 17:16:37.883526 CA_P2S_RATIO = 8
7223 17:16:37.886699 DQ_CA_OPEN = 0
7224 17:16:37.890150 DQ_SEMI_OPEN = 0
7225 17:16:37.893491 CA_SEMI_OPEN = 0
7226 17:16:37.893616 CA_FULL_RATE = 0
7227 17:16:37.896333 DQ_CKDIV4_EN = 0
7228 17:16:37.900501 CA_CKDIV4_EN = 0
7229 17:16:37.903100 CA_PREDIV_EN = 0
7230 17:16:37.906428 PH8_DLY = 12
7231 17:16:37.909772 SEMI_OPEN_CA_PICK_MCK_RATIO= 0
7232 17:16:37.909894 DQ_AAMCK_DIV = 4
7233 17:16:37.913287 CA_AAMCK_DIV = 4
7234 17:16:37.916083 CA_ADMCK_DIV = 4
7235 17:16:37.919391 DQ_TRACK_CA_EN = 0
7236 17:16:37.922714 CA_PICK = 1600
7237 17:16:37.925930 CA_MCKIO = 1600
7238 17:16:37.929211 MCKIO_SEMI = 0
7239 17:16:37.932526 PLL_FREQ = 3068
7240 17:16:37.932611 DQ_UI_PI_RATIO = 32
7241 17:16:37.936142 CA_UI_PI_RATIO = 0
7242 17:16:37.939559 ===================================
7243 17:16:37.942717 ===================================
7244 17:16:37.946181 memory_type:LPDDR4
7245 17:16:37.949475 GP_NUM : 10
7246 17:16:37.949567 SRAM_EN : 1
7247 17:16:37.952972 MD32_EN : 0
7248 17:16:37.955694 ===================================
7249 17:16:37.959064 [ANA_INIT] >>>>>>>>>>>>>>
7250 17:16:37.959149 <<<<<< [CONFIGURE PHASE]: ANA_TX
7251 17:16:37.965857 >>>>>> [CONFIGURE PHASE][SHUFFLE]: PLL
7252 17:16:37.968688 ===================================
7253 17:16:37.968768 data_rate = 3200,PCW = 0X7600
7254 17:16:37.971878 ===================================
7255 17:16:37.975283 <<<<<< [CONFIGURE PHASE][SHUFFLE]: PLL
7256 17:16:37.981995 >>>>>> [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7257 17:16:37.988284 <<<<<< [CONFIGURE PHASE][SHUFFLE]: ANA CLOCK DIV configuration
7258 17:16:37.991778 >>>>>> [CONFIGURE PHASE][SHUFFLE]: Add DLL Gain = 2
7259 17:16:37.994991 >>>>>> [CONFIGURE PHASE][SHUFFLE]: DLL
7260 17:16:37.998411 <<<<<< [CONFIGURE PHASE][SHUFFLE]: DLL
7261 17:16:38.001470 [ANA_INIT] flow start
7262 17:16:38.005063 [ANA_INIT] PLL >>>>>>>>
7263 17:16:38.005157 [ANA_INIT] PLL <<<<<<<<
7264 17:16:38.008328 [ANA_INIT] MIDPI >>>>>>>>
7265 17:16:38.011915 [ANA_INIT] MIDPI <<<<<<<<
7266 17:16:38.012001 [ANA_INIT] DLL >>>>>>>>
7267 17:16:38.015170 [ANA_INIT] DLL <<<<<<<<
7268 17:16:38.017828 [ANA_INIT] flow end
7269 17:16:38.021118 ============ LP4 DIFF to SE enter ============
7270 17:16:38.024636 ============ LP4 DIFF to SE exit ============
7271 17:16:38.028008 [ANA_INIT] <<<<<<<<<<<<<
7272 17:16:38.031565 [Flow] Enable top DCM control >>>>>
7273 17:16:38.034734 [Flow] Enable top DCM control <<<<<
7274 17:16:38.037589 Enable DLL master slave shuffle
7275 17:16:38.040890 ==============================================================
7276 17:16:38.044112 Gating Mode config
7277 17:16:38.050862 ==============================================================
7278 17:16:38.050955 Config description:
7279 17:16:38.061009 RX_GATING_MODE 0: Pulse Mode 1: Burst Mode(8UI) 2: Burst Mode(7UI) 3: Original Burst Mode
7280 17:16:38.067134 RX_GATING_TRACK_MODE 0: Valid DLY Mode 1: Valid Mode (-like) 2: FIFO mode
7281 17:16:38.073951 SELPH_MODE 0: By rank 1: By Phase
7282 17:16:38.077358 ==============================================================
7283 17:16:38.080130 GAT_TRACK_EN = 1
7284 17:16:38.083462 RX_GATING_MODE = 2
7285 17:16:38.086940 RX_GATING_TRACK_MODE = 2
7286 17:16:38.090469 SELPH_MODE = 1
7287 17:16:38.093783 PICG_EARLY_EN = 1
7288 17:16:38.096696 VALID_LAT_VALUE = 1
7289 17:16:38.103413 ==============================================================
7290 17:16:38.106857 Enter into Gating configuration >>>>
7291 17:16:38.110285 Exit from Gating configuration <<<<
7292 17:16:38.113012 Enter into DVFS_PRE_config >>>>>
7293 17:16:38.122796 Because of DLL_ASYNC_EN for indenpendent DLL NOT enable, salve channel's DVFS_DLL_CHA should set 0 to follow master CH's DLL.
7294 17:16:38.125960 Exit from DVFS_PRE_config <<<<<
7295 17:16:38.129490 Enter into PICG configuration >>>>
7296 17:16:38.133006 Exit from PICG configuration <<<<
7297 17:16:38.136353 [RX_INPUT] configuration >>>>>
7298 17:16:38.136439 [RX_INPUT] configuration <<<<<
7299 17:16:38.143074 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 >>>>>
7300 17:16:38.149165 [DIG_FREQ_CONFIG][TX_CA][Delay] ch_id: 0, group_id: 0 <<<<<
7301 17:16:38.156265 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 >>>>>
7302 17:16:38.159730 [DIG_FREQ_CONFIG][IMPDANCE][Configuration] ch_id: 0, group_id: 0 <<<<<
7303 17:16:38.166065 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 >>>>>
7304 17:16:38.172194 [DIG_FREQ_CONFIG][RX_INPUT][Configuration] ch_id: 0, group_id: 0 <<<<<
7305 17:16:38.175637 [DIG_SHUF_CONFIG] MISC >>>>>, group_id= 0
7306 17:16:38.182311 [DIG_SHUF_CONFIG] MISC <<<<<<, group_id= 0
7307 17:16:38.185103 [DIG_SHUF_CONFIG] DQSG_RETRY >>>>>>, group_id= 0
7308 17:16:38.188465 [DIG_SHUF_CONFIG] DQSG_RETRY <<<<<<, group_id= 0
7309 17:16:38.191800 [DIG_SHUF_CONFIG] DBI >>>>>>, group_id= 0
7310 17:16:38.198712 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7311 17:16:38.202142 ===================================
7312 17:16:38.204779 LPDDR4 DRAM CONFIGURATION
7313 17:16:38.208147 ===================================
7314 17:16:38.208245 EX_ROW_EN[0] = 0x0
7315 17:16:38.211590 EX_ROW_EN[1] = 0x0
7316 17:16:38.211673 LP4Y_EN = 0x0
7317 17:16:38.214846 WORK_FSP = 0x1
7318 17:16:38.214948 WL = 0x5
7319 17:16:38.218332 RL = 0x5
7320 17:16:38.218407 BL = 0x2
7321 17:16:38.221656 RPST = 0x0
7322 17:16:38.221739 RD_PRE = 0x0
7323 17:16:38.224408 WR_PRE = 0x1
7324 17:16:38.227608 WR_PST = 0x1
7325 17:16:38.227703 DBI_WR = 0x0
7326 17:16:38.230929 DBI_RD = 0x0
7327 17:16:38.231010 OTF = 0x1
7328 17:16:38.234298 ===================================
7329 17:16:38.237641 [DIG_SHUF_CONFIG] DBI <<<<<<, group_id= 0
7330 17:16:38.243881 [DIG_SHUF_CONFIG] DVFSRLWL >>>>>>, group_id= 0
7331 17:16:38.247168 [ModeRegister RLWL Config] data_rate:3200-MR2_RLWL:5
7332 17:16:38.250558 ===================================
7333 17:16:38.254062 LPDDR4 DRAM CONFIGURATION
7334 17:16:38.257372 ===================================
7335 17:16:38.257471 EX_ROW_EN[0] = 0x10
7336 17:16:38.260310 EX_ROW_EN[1] = 0x0
7337 17:16:38.260392 LP4Y_EN = 0x0
7338 17:16:38.263635
7339 17:16:38.263710 WORK_FSP = 0x1
7340 17:16:38.267489 WL = 0x5
7341 17:16:38.267575 RL = 0x5
7342 17:16:38.270133 BL = 0x2
7343 17:16:38.270226 RPST = 0x0
7344 17:16:38.273457 RD_PRE = 0x0
7345 17:16:38.273539 WR_PRE = 0x1
7346 17:16:38.276775 WR_PST = 0x1
7347 17:16:38.276854 DBI_WR = 0x0
7348 17:16:38.280120 DBI_RD = 0x0
7349 17:16:38.280198 OTF = 0x1
7350 17:16:38.283374 ===================================
7351 17:16:38.289667 [test_sa.c]====>ch_id: 0, group_id: 0, DPI_TBA_DVFS_WLRL_setting Exit
7352 17:16:38.289749 ==
7353 17:16:38.293080 Dram Type= 6, Freq= 0, CH_0, rank 0
7354 17:16:38.299899 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7355 17:16:38.299994 ==
7356 17:16:38.300060 [Duty_Offset_Calibration]
7357 17:16:38.302863 B0:2 B1:0 CA:4
7358 17:16:38.302951
7359 17:16:38.306217 [DutyScan_Calibration_Flow] k_type=0
7360 17:16:38.314807
7361 17:16:38.314905 ==CLK 0==
7362 17:16:38.317667 Final CLK duty delay cell = -4
7363 17:16:38.321183 [-4] MAX Duty = 5031%(X100), DQS PI = 16
7364 17:16:38.324570 [-4] MIN Duty = 4813%(X100), DQS PI = 8
7365 17:16:38.328077 [-4] AVG Duty = 4922%(X100)
7366 17:16:38.328159
7367 17:16:38.330817 CH0 CLK Duty spec in!! Max-Min= 218%
7368 17:16:38.334116 [DutyScan_Calibration_Flow] ====Done====
7369 17:16:38.334195
7370 17:16:38.337378 [DutyScan_Calibration_Flow] k_type=1
7371 17:16:38.354833
7372 17:16:38.354935 ==DQS 0 ==
7373 17:16:38.358319 Final DQS duty delay cell = 0
7374 17:16:38.361616 [0] MAX Duty = 5249%(X100), DQS PI = 38
7375 17:16:38.364994 [0] MIN Duty = 5093%(X100), DQS PI = 12
7376 17:16:38.368413 [0] AVG Duty = 5171%(X100)
7377 17:16:38.368492
7378 17:16:38.368557 ==DQS 1 ==
7379 17:16:38.371103 Final DQS duty delay cell = 0
7380 17:16:38.374574 [0] MAX Duty = 5187%(X100), DQS PI = 2
7381 17:16:38.378358 [0] MIN Duty = 4969%(X100), DQS PI = 10
7382 17:16:38.381140 [0] AVG Duty = 5078%(X100)
7383 17:16:38.381219
7384 17:16:38.384532 CH0 DQS 0 Duty spec in!! Max-Min= 156%
7385 17:16:38.384613
7386 17:16:38.387634 CH0 DQS 1 Duty spec in!! Max-Min= 218%
7387 17:16:38.391163 [DutyScan_Calibration_Flow] ====Done====
7388 17:16:38.391243
7389 17:16:38.394482 [DutyScan_Calibration_Flow] k_type=3
7390 17:16:38.411916
7391 17:16:38.412005 ==DQM 0 ==
7392 17:16:38.415204 Final DQM duty delay cell = 0
7393 17:16:38.418625 [0] MAX Duty = 5124%(X100), DQS PI = 20
7394 17:16:38.422055 [0] MIN Duty = 4907%(X100), DQS PI = 52
7395 17:16:38.425287 [0] AVG Duty = 5015%(X100)
7396 17:16:38.425382
7397 17:16:38.425472 ==DQM 1 ==
7398 17:16:38.428264 Final DQM duty delay cell = 0
7399 17:16:38.431536 [0] MAX Duty = 4969%(X100), DQS PI = 0
7400 17:16:38.434797 [0] MIN Duty = 4813%(X100), DQS PI = 16
7401 17:16:38.438324 [0] AVG Duty = 4891%(X100)
7402 17:16:38.438406
7403 17:16:38.441474 CH0 DQM 0 Duty spec in!! Max-Min= 217%
7404 17:16:38.441559
7405 17:16:38.444955 CH0 DQM 1 Duty spec in!! Max-Min= 156%
7406 17:16:38.448403 [DutyScan_Calibration_Flow] ====Done====
7407 17:16:38.448494
7408 17:16:38.451038 [DutyScan_Calibration_Flow] k_type=2
7409 17:16:38.468952
7410 17:16:38.469045 ==DQ 0 ==
7411 17:16:38.472303 Final DQ duty delay cell = 0
7412 17:16:38.475588 [0] MAX Duty = 5124%(X100), DQS PI = 20
7413 17:16:38.479107 [0] MIN Duty = 4938%(X100), DQS PI = 12
7414 17:16:38.479197 [0] AVG Duty = 5031%(X100)
7415 17:16:38.482302
7416 17:16:38.482384
7417 17:16:38.482450 ==DQ 1 ==
7418 17:16:38.485634 Final DQ duty delay cell = 0
7419 17:16:38.488887 [0] MAX Duty = 5187%(X100), DQS PI = 2
7420 17:16:38.492286 [0] MIN Duty = 4907%(X100), DQS PI = 32
7421 17:16:38.492367 [0] AVG Duty = 5047%(X100)
7422 17:16:38.495227
7423 17:16:38.495310
7424 17:16:38.498760 CH0 DQ 0 Duty spec in!! Max-Min= 186%
7425 17:16:38.498842
7426 17:16:38.502070 CH0 DQ 1 Duty spec in!! Max-Min= 280%
7427 17:16:38.505572 [DutyScan_Calibration_Flow] ====Done====
7428 17:16:38.505655 ==
7429 17:16:38.508312 Dram Type= 6, Freq= 0, CH_1, rank 0
7430 17:16:38.511562 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7431 17:16:38.511645 ==
7432 17:16:38.514990 [Duty_Offset_Calibration]
7433 17:16:38.515077 B0:0 B1:-1 CA:3
7434 17:16:38.515146
7435 17:16:38.518069 [DutyScan_Calibration_Flow] k_type=0
7436 17:16:38.528965
7437 17:16:38.529052 ==CLK 0==
7438 17:16:38.531665 Final CLK duty delay cell = -4
7439 17:16:38.534894 [-4] MAX Duty = 5031%(X100), DQS PI = 30
7440 17:16:38.538364 [-4] MIN Duty = 4844%(X100), DQS PI = 40
7441 17:16:38.541660 [-4] AVG Duty = 4937%(X100)
7442 17:16:38.541747
7443 17:16:38.545081 CH1 CLK Duty spec in!! Max-Min= 187%
7444 17:16:38.548207 [DutyScan_Calibration_Flow] ====Done====
7445 17:16:38.548293
7446 17:16:38.551548 [DutyScan_Calibration_Flow] k_type=1
7447 17:16:38.567659
7448 17:16:38.567749 ==DQS 0 ==
7449 17:16:38.571107 Final DQS duty delay cell = 0
7450 17:16:38.574479 [0] MAX Duty = 5250%(X100), DQS PI = 28
7451 17:16:38.577699 [0] MIN Duty = 4938%(X100), DQS PI = 42
7452 17:16:38.581000 [0] AVG Duty = 5094%(X100)
7453 17:16:38.581083
7454 17:16:38.581169 ==DQS 1 ==
7455 17:16:38.584510 Final DQS duty delay cell = -4
7456 17:16:38.587812 [-4] MAX Duty = 5000%(X100), DQS PI = 28
7457 17:16:38.591095 [-4] MIN Duty = 4844%(X100), DQS PI = 0
7458 17:16:38.593813 [-4] AVG Duty = 4922%(X100)
7459 17:16:38.593913
7460 17:16:38.597335 CH1 DQS 0 Duty spec in!! Max-Min= 312%
7461 17:16:38.597416
7462 17:16:38.600773 CH1 DQS 1 Duty spec in!! Max-Min= 156%
7463 17:16:38.604049 [DutyScan_Calibration_Flow] ====Done====
7464 17:16:38.604132
7465 17:16:38.607374 [DutyScan_Calibration_Flow] k_type=3
7466 17:16:38.625619
7467 17:16:38.625755 ==DQM 0 ==
7468 17:16:38.628337 Final DQM duty delay cell = 0
7469 17:16:38.631663 [0] MAX Duty = 5062%(X100), DQS PI = 30
7470 17:16:38.634854 [0] MIN Duty = 4750%(X100), DQS PI = 40
7471 17:16:38.638210 [0] AVG Duty = 4906%(X100)
7472 17:16:38.638332
7473 17:16:38.638410 ==DQM 1 ==
7474 17:16:38.641676 Final DQM duty delay cell = 0
7475 17:16:38.645070 [0] MAX Duty = 5000%(X100), DQS PI = 30
7476 17:16:38.648482 [0] MIN Duty = 4813%(X100), DQS PI = 0
7477 17:16:38.651628 [0] AVG Duty = 4906%(X100)
7478 17:16:38.651715
7479 17:16:38.654906 CH1 DQM 0 Duty spec in!! Max-Min= 312%
7480 17:16:38.654989
7481 17:16:38.658365 CH1 DQM 1 Duty spec in!! Max-Min= 187%
7482 17:16:38.661019 [DutyScan_Calibration_Flow] ====Done====
7483 17:16:38.661103
7484 17:16:38.664381 [DutyScan_Calibration_Flow] k_type=2
7485 17:16:38.681467
7486 17:16:38.681564 ==DQ 0 ==
7487 17:16:38.684601 Final DQ duty delay cell = -4
7488 17:16:38.688055 [-4] MAX Duty = 4969%(X100), DQS PI = 32
7489 17:16:38.690781 [-4] MIN Duty = 4813%(X100), DQS PI = 36
7490 17:16:38.694089 [-4] AVG Duty = 4891%(X100)
7491 17:16:38.694178
7492 17:16:38.694252 ==DQ 1 ==
7493 17:16:38.697691 Final DQ duty delay cell = 0
7494 17:16:38.701076 [0] MAX Duty = 5062%(X100), DQS PI = 32
7495 17:16:38.704449 [0] MIN Duty = 4844%(X100), DQS PI = 58
7496 17:16:38.707286 [0] AVG Duty = 4953%(X100)
7497 17:16:38.707376
7498 17:16:38.710651 CH1 DQ 0 Duty spec in!! Max-Min= 156%
7499 17:16:38.710734
7500 17:16:38.713992 CH1 DQ 1 Duty spec in!! Max-Min= 218%
7501 17:16:38.717171 [DutyScan_Calibration_Flow] ====Done====
7502 17:16:38.720483 nWR fixed to 30
7503 17:16:38.723804 [ModeRegInit_LP4] CH0 RK0
7504 17:16:38.723886 [ModeRegInit_LP4] CH0 RK1
7505 17:16:38.727006 [ModeRegInit_LP4] CH1 RK0
7506 17:16:38.730373 [ModeRegInit_LP4] CH1 RK1
7507 17:16:38.730453 match AC timing 5
7508 17:16:38.736988 dramType 5, freq 1600, readDBI 0, DivMode 1, cbtMode 1
7509 17:16:38.740318 SET_CKE_2_RANK_INDEPENDENT_RUN_TIME: ON
7510 17:16:38.743851 [WriteLatency GET] Version:0-MR_RL_field_value:5-WL:14
7511 17:16:38.749845 [TX_path_calculate] data rate=3200, WL=14, DQS_TotalUI=29
7512 17:16:38.753313 [TX_path_calculate] DQS = (3,5) DQS_OE = (3,2)
7513 17:16:38.756474 [MiockJmeterHQA]
7514 17:16:38.756558
7515 17:16:38.759895 [DramcMiockJmeter] u1RxGatingPI = 0
7516 17:16:38.759976 0 : 4363, 4137
7517 17:16:38.760057 4 : 4255, 4029
7518 17:16:38.763502 8 : 4252, 4027
7519 17:16:38.763583 12 : 4252, 4027
7520 17:16:38.766866 16 : 4252, 4027
7521 17:16:38.766962 20 : 4363, 4137
7522 17:16:38.769560 24 : 4361, 4137
7523 17:16:38.769643 28 : 4253, 4026
7524 17:16:38.773051 32 : 4252, 4027
7525 17:16:38.773133 36 : 4250, 4027
7526 17:16:38.773211 40 : 4252, 4027
7527 17:16:38.776566 44 : 4250, 4027
7528 17:16:38.776648 48 : 4363, 4140
7529 17:16:38.779855 52 : 4252, 4027
7530 17:16:38.779945 56 : 4250, 4027
7531 17:16:38.783293 60 : 4250, 4027
7532 17:16:38.783382 64 : 4250, 4027
7533 17:16:38.786133 68 : 4250, 4026
7534 17:16:38.786214 72 : 4360, 4138
7535 17:16:38.786293 76 : 4360, 4137
7536 17:16:38.789527 80 : 4250, 4027
7537 17:16:38.789607 84 : 4250, 4027
7538 17:16:38.792875 88 : 4250, 4027
7539 17:16:38.792957 92 : 4250, 4027
7540 17:16:38.796310 96 : 4250, 3326
7541 17:16:38.796409 100 : 4361, 0
7542 17:16:38.796480 104 : 4250, 0
7543 17:16:38.799649 108 : 4360, 0
7544 17:16:38.799731 112 : 4250, 0
7545 17:16:38.802394 116 : 4250, 0
7546 17:16:38.802472 120 : 4250, 0
7547 17:16:38.802538 124 : 4250, 0
7548 17:16:38.805835 128 : 4250, 0
7549 17:16:38.805918 132 : 4252, 0
7550 17:16:38.808988 136 : 4250, 0
7551 17:16:38.809084 140 : 4250, 0
7552 17:16:38.809154 144 : 4250, 0
7553 17:16:38.812245 148 : 4360, 0
7554 17:16:38.812328 152 : 4361, 0
7555 17:16:38.815568 156 : 4360, 0
7556 17:16:38.815649 160 : 4250, 0
7557 17:16:38.815719 164 : 4250, 0
7558 17:16:38.818898 168 : 4363, 0
7559 17:16:38.819007 172 : 4250, 0
7560 17:16:38.822128 176 : 4250, 0
7561 17:16:38.822238 180 : 4250, 0
7562 17:16:38.822325 184 : 4250, 0
7563 17:16:38.825869 188 : 4250, 0
7564 17:16:38.825948 192 : 4250, 0
7565 17:16:38.829037 196 : 4250, 0
7566 17:16:38.829118 200 : 4360, 0
7567 17:16:38.829189 204 : 4361, 0
7568 17:16:38.832059 208 : 4360, 0
7569 17:16:38.832140 212 : 4249, 0
7570 17:16:38.832209 216 : 4250, 0
7571 17:16:38.835434
7572 17:16:38.835514 220 : 4250, 606
7573 17:16:38.835579 224 : 4250, 4004
7574 17:16:38.838536 228 : 4250, 4027
7575 17:16:38.838630 232 : 4252, 4029
7576 17:16:38.842446 236 : 4250, 4026
7577 17:16:38.842531 240 : 4250, 4027
7578 17:16:38.845171 244 : 4361, 4137
7579 17:16:38.845279 248 : 4250, 4027
7580 17:16:38.848467 252 : 4250, 4026
7581 17:16:38.848573 256 : 4361, 4137
7582 17:16:38.851867 260 : 4250, 4027
7583 17:16:38.851947 264 : 4250, 4027
7584 17:16:38.855236 268 : 4363, 4140
7585 17:16:38.855326 272 : 4250, 4027
7586 17:16:38.858628 276 : 4250, 4027
7587 17:16:38.858710 280 : 4249, 4027
7588 17:16:38.858785 284 : 4250, 4027
7589 17:16:38.861885
7590 17:16:38.861963 288 : 4250, 4026
7591 17:16:38.862033 292 : 4250, 4027
7592 17:16:38.864722 296 : 4360, 4138
7593 17:16:38.864802 300 : 4250, 4026
7594 17:16:38.867948 304 : 4250, 4027
7595 17:16:38.868029 308 : 4361, 4137
7596 17:16:38.871441 312 : 4250, 4027
7597 17:16:38.871524 316 : 4250, 4027
7598 17:16:38.874892 320 : 4360, 4137
7599 17:16:38.874979 324 : 4250, 4026
7600 17:16:38.878291 328 : 4250, 4027
7601 17:16:38.878373 332 : 4250, 4025
7602 17:16:38.881529 336 : 4252, 1998
7603 17:16:38.881608
7604 17:16:38.881685 MIOCK jitter meter ch=0
7605 17:16:38.881748
7606 17:16:38.884977 1T = (336-100) = 236 dly cells
7607 17:16:38.891119 Clock freq = 1534 MHz, period = 651 ps, 1 dly cell = 275/100 ps
7608 17:16:38.891202 ==
7609 17:16:38.894378 Dram Type= 6, Freq= 0, CH_0, rank 0
7610 17:16:38.897760 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7611 17:16:38.897842 ==
7612 17:16:38.904212 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7613 17:16:38.907574 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7614 17:16:38.914406 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7615 17:16:38.917096 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7616 17:16:38.927772 [CA 0] Center 43 (13~73) winsize 61
7617 17:16:38.930794 [CA 1] Center 42 (12~73) winsize 62
7618 17:16:38.934835 [CA 2] Center 37 (8~67) winsize 60
7619 17:16:38.937879 [CA 3] Center 37 (8~67) winsize 60
7620 17:16:38.941218 [CA 4] Center 36 (6~66) winsize 61
7621 17:16:38.944493 [CA 5] Center 35 (5~66) winsize 62
7622 17:16:38.944591
7623 17:16:38.947694 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7624 17:16:38.947777
7625 17:16:38.951049 [CATrainingPosCal] consider 1 rank data
7626 17:16:38.953796
7627 17:16:38.953877 u2DelayCellTimex100 = 275/100 ps
7628 17:16:38.960428 CA0 delay=43 (13~73),Diff = 8 PI (28 cell)
7629 17:16:38.964275 CA1 delay=42 (12~73),Diff = 7 PI (24 cell)
7630 17:16:38.966925 CA2 delay=37 (8~67),Diff = 2 PI (7 cell)
7631 17:16:38.970389 CA3 delay=37 (8~67),Diff = 2 PI (7 cell)
7632 17:16:38.973716 CA4 delay=36 (6~66),Diff = 1 PI (3 cell)
7633 17:16:38.977155 CA5 delay=35 (5~66),Diff = 0 PI (0 cell)
7634 17:16:38.977240
7635 17:16:38.980081 CA PerBit enable=1, Macro0, CA PI delay=35
7636 17:16:38.980172
7637 17:16:38.983477 [CBTSetCACLKResult] CA Dly = 35
7638 17:16:38.986806 CS Dly: 10 (0~41)
7639 17:16:38.990339 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7640 17:16:38.993094 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7641 17:16:38.993179 ==
7642 17:16:38.996369 Dram Type= 6, Freq= 0, CH_0, rank 1
7643 17:16:39.003154 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7644 17:16:39.003245 ==
7645 17:16:39.006444 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
7646 17:16:39.013212 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=1
7647 17:16:39.016842 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=1
7648 17:16:39.022866 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
7649 17:16:39.031105 [CA 0] Center 43 (13~74) winsize 62
7650 17:16:39.034473 [CA 1] Center 43 (13~73) winsize 61
7651 17:16:39.038055 [CA 2] Center 38 (9~68) winsize 60
7652 17:16:39.041354 [CA 3] Center 38 (9~68) winsize 60
7653 17:16:39.044538 [CA 4] Center 36 (6~67) winsize 62
7654 17:16:39.047294 [CA 5] Center 36 (6~66) winsize 61
7655 17:16:39.047378
7656 17:16:39.050873 [CmdBusTrainingLP45] Vref(ca) range 0: 32
7657 17:16:39.050965
7658 17:16:39.057325 [CATrainingPosCal] consider 2 rank data
7659 17:16:39.057410 u2DelayCellTimex100 = 275/100 ps
7660 17:16:39.064094 CA0 delay=43 (13~73),Diff = 7 PI (24 cell)
7661 17:16:39.067304 CA1 delay=43 (13~73),Diff = 7 PI (24 cell)
7662 17:16:39.070747 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
7663 17:16:39.073476 CA3 delay=38 (9~67),Diff = 2 PI (7 cell)
7664 17:16:39.077124 CA4 delay=36 (6~66),Diff = 0 PI (0 cell)
7665 17:16:39.080494 CA5 delay=36 (6~66),Diff = 0 PI (0 cell)
7666 17:16:39.080576
7667 17:16:39.083310 CA PerBit enable=1, Macro0, CA PI delay=36
7668 17:16:39.083389
7669 17:16:39.086812 [CBTSetCACLKResult] CA Dly = 36
7670 17:16:39.090364 CS Dly: 11 (0~44)
7671 17:16:39.093813 [DramcModeRegInit_CATerm] CH0 RK0 bWorkAround=0
7672 17:16:39.096448 [DramcModeRegInit_CATerm] CH0 RK1 bWorkAround=0
7673 17:16:39.096527
7674 17:16:39.099956 ----->DramcWriteLeveling(PI) begin...
7675 17:16:39.103111 ==
7676 17:16:39.106566 Dram Type= 6, Freq= 0, CH_0, rank 0
7677 17:16:39.110091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7678 17:16:39.110178 ==
7679 17:16:39.113302 Write leveling (Byte 0): 33 => 33
7680 17:16:39.116940 Write leveling (Byte 1): 26 => 26
7681 17:16:39.119832 DramcWriteLeveling(PI) end<-----
7682 17:16:39.119915
7683 17:16:39.120002 ==
7684 17:16:39.123109 Dram Type= 6, Freq= 0, CH_0, rank 0
7685 17:16:39.126437 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7686 17:16:39.126518 ==
7687 17:16:39.129619 [Gating] SW mode calibration
7688 17:16:39.135986 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
7689 17:16:39.142478 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
7690 17:16:39.145814 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7691 17:16:39.149153 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7692 17:16:39.156319 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7693 17:16:39.159426 1 4 12 | B1->B0 | 2323 3131 | 0 1 | (0 0) (1 1)
7694 17:16:39.162648 1 4 16 | B1->B0 | 2424 3434 | 0 1 | (0 0) (1 1)
7695 17:16:39.168980 1 4 20 | B1->B0 | 2c2c 3434 | 0 1 | (0 0) (1 1)
7696 17:16:39.172435 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7697 17:16:39.175780 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7698 17:16:39.182071 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7699 17:16:39.185405 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
7700 17:16:39.189177 1 5 8 | B1->B0 | 3434 3333 | 1 1 | (1 1) (1 0)
7701 17:16:39.194947 1 5 12 | B1->B0 | 3434 2929 | 1 0 | (1 1) (0 0)
7702 17:16:39.198309 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 1) (0 0)
7703 17:16:39.201661 1 5 20 | B1->B0 | 2f2f 2323 | 1 0 | (1 0) (0 0)
7704 17:16:39.208200 1 5 24 | B1->B0 | 2525 2323 | 0 0 | (0 0) (0 0)
7705 17:16:39.211481 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7706 17:16:39.214932 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7707 17:16:39.221654 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
7708 17:16:39.224306 1 6 8 | B1->B0 | 2323 2b2b | 0 0 | (0 0) (0 0)
7709 17:16:39.228221 1 6 12 | B1->B0 | 2323 4444 | 0 0 | (0 0) (0 0)
7710 17:16:39.234674 1 6 16 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
7711 17:16:39.237549 1 6 20 | B1->B0 | 3737 4646 | 1 0 | (0 0) (0 0)
7712 17:16:39.241059 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7713 17:16:39.247696 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7714 17:16:39.250805 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7715 17:16:39.253966 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7716 17:16:39.257383
7717 17:16:39.260481 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7718 17:16:39.263791 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
7719 17:16:39.270779 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
7720 17:16:39.273981 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7721 17:16:39.276646 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
7722 17:16:39.283299 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7723 17:16:39.286644 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7724 17:16:39.289944 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7725 17:16:39.296719 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7726 17:16:39.300118 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7727 17:16:39.303246 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7728 17:16:39.309904 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7729 17:16:39.313169 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7730 17:16:39.316744 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7731 17:16:39.322821 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7732 17:16:39.325933 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
7733 17:16:39.329387 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7734 17:16:39.335984 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
7735 17:16:39.339350 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
7736 17:16:39.342627 Total UI for P1: 0, mck2ui 16
7737 17:16:39.345952 best dqsien dly found for B0: ( 1, 9, 10)
7738 17:16:39.349376 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
7739 17:16:39.355615 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
7740 17:16:39.355726 Total UI for P1: 0, mck2ui 16
7741 17:16:39.362495 best dqsien dly found for B1: ( 1, 9, 20)
7742 17:16:39.365623 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
7743 17:16:39.368864 best DQS1 dly(MCK, UI, PI) = (1, 9, 20)
7744 17:16:39.368943
7745 17:16:39.372071 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
7746 17:16:39.375186 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 20)
7747 17:16:39.378734 [Gating] SW calibration Done
7748 17:16:39.378813 ==
7749 17:16:39.382052 Dram Type= 6, Freq= 0, CH_0, rank 0
7750 17:16:39.385449 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7751 17:16:39.385527 ==
7752 17:16:39.388775 RX Vref Scan: 0
7753 17:16:39.388851
7754 17:16:39.392035 RX Vref 0 -> 0, step: 1
7755 17:16:39.392117
7756 17:16:39.392187 RX Delay 0 -> 252, step: 8
7757 17:16:39.398536 iDelay=192, Bit 0, Center 131 (80 ~ 183) 104
7758 17:16:39.402056 iDelay=192, Bit 1, Center 135 (80 ~ 191) 112
7759 17:16:39.405356 iDelay=192, Bit 2, Center 127 (72 ~ 183) 112
7760 17:16:39.408519 iDelay=192, Bit 3, Center 131 (80 ~ 183) 104
7761 17:16:39.411982 iDelay=192, Bit 4, Center 135 (80 ~ 191) 112
7762 17:16:39.417957 iDelay=192, Bit 5, Center 119 (64 ~ 175) 112
7763 17:16:39.421244 iDelay=192, Bit 6, Center 139 (88 ~ 191) 104
7764 17:16:39.424603 iDelay=192, Bit 7, Center 139 (88 ~ 191) 104
7765 17:16:39.427879 iDelay=192, Bit 8, Center 119 (64 ~ 175) 112
7766 17:16:39.431278 iDelay=192, Bit 9, Center 115 (64 ~ 167) 104
7767 17:16:39.437895 iDelay=192, Bit 10, Center 127 (80 ~ 175) 96
7768 17:16:39.441099 iDelay=192, Bit 11, Center 123 (72 ~ 175) 104
7769 17:16:39.444238 iDelay=192, Bit 12, Center 135 (80 ~ 191) 112
7770 17:16:39.447520 iDelay=192, Bit 13, Center 131 (80 ~ 183) 104
7771 17:16:39.454309 iDelay=192, Bit 14, Center 135 (80 ~ 191) 112
7772 17:16:39.457409 iDelay=192, Bit 15, Center 131 (80 ~ 183) 104
7773 17:16:39.457504 ==
7774 17:16:39.460618 Dram Type= 6, Freq= 0, CH_0, rank 0
7775 17:16:39.463918 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7776 17:16:39.464004 ==
7777 17:16:39.467705 DQS Delay:
7778 17:16:39.467795 DQS0 = 0, DQS1 = 0
7779 17:16:39.467860 DQM Delay:
7780 17:16:39.470803 DQM0 = 132, DQM1 = 127
7781 17:16:39.470900 DQ Delay:
7782 17:16:39.473908 DQ0 =131, DQ1 =135, DQ2 =127, DQ3 =131
7783 17:16:39.477050 DQ4 =135, DQ5 =119, DQ6 =139, DQ7 =139
7784 17:16:39.484199 DQ8 =119, DQ9 =115, DQ10 =127, DQ11 =123
7785 17:16:39.486801 DQ12 =135, DQ13 =131, DQ14 =135, DQ15 =131
7786 17:16:39.486885
7787 17:16:39.486972
7788 17:16:39.487035 ==
7789 17:16:39.490168 Dram Type= 6, Freq= 0, CH_0, rank 0
7790 17:16:39.493541 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7791 17:16:39.493665 ==
7792 17:16:39.493732
7793 17:16:39.493798
7794 17:16:39.496716 TX Vref Scan disable
7795 17:16:39.499947 == TX Byte 0 ==
7796 17:16:39.503261 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
7797 17:16:39.506436 Update DQM dly =989 (3 ,6, 29) DQM OEN =(3 ,3)
7798 17:16:39.509864 == TX Byte 1 ==
7799 17:16:39.513030 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
7800 17:16:39.516480 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7801 17:16:39.516636 ==
7802 17:16:39.519807 Dram Type= 6, Freq= 0, CH_0, rank 0
7803 17:16:39.526129 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7804 17:16:39.526211 ==
7805 17:16:39.539330
7806 17:16:39.542594 TX Vref early break, caculate TX vref
7807 17:16:39.545963 TX Vref=16, minBit 7, minWin=22, winSum=369
7808 17:16:39.549199 TX Vref=18, minBit 1, minWin=23, winSum=379
7809 17:16:39.552571 TX Vref=20, minBit 12, minWin=23, winSum=389
7810 17:16:39.555920 TX Vref=22, minBit 8, minWin=23, winSum=402
7811 17:16:39.559275 TX Vref=24, minBit 1, minWin=24, winSum=408
7812 17:16:39.565582 TX Vref=26, minBit 8, minWin=25, winSum=420
7813 17:16:39.569397 TX Vref=28, minBit 4, minWin=25, winSum=420
7814 17:16:39.572744 TX Vref=30, minBit 0, minWin=25, winSum=417
7815 17:16:39.575876 TX Vref=32, minBit 2, minWin=24, winSum=410
7816 17:16:39.579220 TX Vref=34, minBit 1, minWin=23, winSum=399
7817 17:16:39.585511 TX Vref=36, minBit 2, minWin=23, winSum=388
7818 17:16:39.588914 [TxChooseVref] Worse bit 8, Min win 25, Win sum 420, Final Vref 26
7819 17:16:39.588995
7820 17:16:39.592392 Final TX Range 0 Vref 26
7821 17:16:39.592473
7822 17:16:39.592545 ==
7823 17:16:39.595080 Dram Type= 6, Freq= 0, CH_0, rank 0
7824 17:16:39.599031 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7825 17:16:39.602103 ==
7826 17:16:39.602182
7827 17:16:39.602248
7828 17:16:39.602316 TX Vref Scan disable
7829 17:16:39.608557 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
7830 17:16:39.608644 == TX Byte 0 ==
7831 17:16:39.611879 u2DelayCellOfst[0]=14 cells (4 PI)
7832 17:16:39.615937 u2DelayCellOfst[1]=17 cells (5 PI)
7833 17:16:39.618590 u2DelayCellOfst[2]=10 cells (3 PI)
7834 17:16:39.621867 u2DelayCellOfst[3]=10 cells (3 PI)
7835 17:16:39.625254 u2DelayCellOfst[4]=10 cells (3 PI)
7836 17:16:39.628532 u2DelayCellOfst[5]=0 cells (0 PI)
7837 17:16:39.631670 u2DelayCellOfst[6]=17 cells (5 PI)
7838 17:16:39.634995 u2DelayCellOfst[7]=17 cells (5 PI)
7839 17:16:39.638178 Update DQ dly =986 (3 ,6, 26) DQ OEN =(3 ,3)
7840 17:16:39.644945 Update DQM dly =988 (3 ,6, 28) DQM OEN =(3 ,3)
7841 17:16:39.645026 == TX Byte 1 ==
7842 17:16:39.648142 u2DelayCellOfst[8]=0 cells (0 PI)
7843 17:16:39.651448 u2DelayCellOfst[9]=0 cells (0 PI)
7844 17:16:39.654818 u2DelayCellOfst[10]=7 cells (2 PI)
7845 17:16:39.658185 u2DelayCellOfst[11]=0 cells (0 PI)
7846 17:16:39.661407 u2DelayCellOfst[12]=7 cells (2 PI)
7847 17:16:39.664565 u2DelayCellOfst[13]=10 cells (3 PI)
7848 17:16:39.667710 u2DelayCellOfst[14]=14 cells (4 PI)
7849 17:16:39.670956 u2DelayCellOfst[15]=7 cells (2 PI)
7850 17:16:39.673985 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
7851 17:16:39.677492 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
7852 17:16:39.681367 DramC Write-DBI on
7853 17:16:39.681445 ==
7854 17:16:39.683979 Dram Type= 6, Freq= 0, CH_0, rank 0
7855 17:16:39.687243 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7856 17:16:39.687322 ==
7857 17:16:39.687387
7858 17:16:39.687452
7859 17:16:39.690570 TX Vref Scan disable
7860 17:16:39.693936 == TX Byte 0 ==
7861 17:16:39.697261 Update DQM dly =732 (2 ,6, 28) DQM OEN =(3 ,3)
7862 17:16:39.697367 == TX Byte 1 ==
7863 17:16:39.703448 Update DQM dly =723 (2 ,6, 19) DQM OEN =(3 ,3)
7864 17:16:39.703528 DramC Write-DBI off
7865 17:16:39.703594
7866 17:16:39.707013 [DATLAT]
7867 17:16:39.707085 Freq=1600, CH0 RK0
7868 17:16:39.707148
7869 17:16:39.710175 DATLAT Default: 0xf
7870 17:16:39.710253 0, 0xFFFF, sum = 0
7871 17:16:39.713439 1, 0xFFFF, sum = 0
7872 17:16:39.713514 2, 0xFFFF, sum = 0
7873 17:16:39.717449 3, 0xFFFF, sum = 0
7874 17:16:39.717526 4, 0xFFFF, sum = 0
7875 17:16:39.719912 5, 0xFFFF, sum = 0
7876 17:16:39.719988 6, 0xFFFF, sum = 0
7877 17:16:39.723295 7, 0xFFFF, sum = 0
7878 17:16:39.723372 8, 0xFFFF, sum = 0
7879 17:16:39.726595 9, 0xFFFF, sum = 0
7880 17:16:39.726673 10, 0xFFFF, sum = 0
7881 17:16:39.729907 11, 0xFFFF, sum = 0
7882 17:16:39.733276 12, 0xFFFF, sum = 0
7883 17:16:39.733353 13, 0xFFFF, sum = 0
7884 17:16:39.736615 14, 0x0, sum = 1
7885 17:16:39.736693 15, 0x0, sum = 2
7886 17:16:39.739856 16, 0x0, sum = 3
7887 17:16:39.739935 17, 0x0, sum = 4
7888 17:16:39.739999 best_step = 15
7889 17:16:39.740074
7890 17:16:39.743192
7891 17:16:39.743283 ==
7892 17:16:39.746465 Dram Type= 6, Freq= 0, CH_0, rank 0
7893 17:16:39.749923 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
7894 17:16:39.750000 ==
7895 17:16:39.750065 RX Vref Scan: 1
7896 17:16:39.750126
7897 17:16:39.753196 Set Vref Range= 24 -> 127
7898 17:16:39.753272
7899 17:16:39.755917 RX Vref 24 -> 127, step: 1
7900 17:16:39.756008
7901 17:16:39.759907 RX Delay 19 -> 252, step: 4
7902 17:16:39.759985
7903 17:16:39.763243 Set Vref, RX VrefLevel [Byte0]: 24
7904 17:16:39.765871 [Byte1]: 24
7905 17:16:39.766018
7906 17:16:39.769650 Set Vref, RX VrefLevel [Byte0]: 25
7907 17:16:39.772797 [Byte1]: 25
7908 17:16:39.772894
7909 17:16:39.776057 Set Vref, RX VrefLevel [Byte0]: 26
7910 17:16:39.779259 [Byte1]: 26
7911 17:16:39.783079
7912 17:16:39.783157 Set Vref, RX VrefLevel [Byte0]: 27
7913 17:16:39.786415 [Byte1]: 27
7914 17:16:39.790833
7915 17:16:39.790934 Set Vref, RX VrefLevel [Byte0]: 28
7916 17:16:39.794377 [Byte1]: 28
7917 17:16:39.798359
7918 17:16:39.798436 Set Vref, RX VrefLevel [Byte0]: 29
7919 17:16:39.801615 [Byte1]: 29
7920 17:16:39.805731
7921 17:16:39.805838 Set Vref, RX VrefLevel [Byte0]: 30
7922 17:16:39.809014 [Byte1]: 30
7923 17:16:39.813643
7924 17:16:39.813721 Set Vref, RX VrefLevel [Byte0]: 31
7925 17:16:39.816885 [Byte1]: 31
7926 17:16:39.820890
7927 17:16:39.820973 Set Vref, RX VrefLevel [Byte0]: 32
7928 17:16:39.824104 [Byte1]: 32
7929 17:16:39.828631
7930 17:16:39.828720 Set Vref, RX VrefLevel [Byte0]: 33
7931 17:16:39.832143 [Byte1]: 33
7932 17:16:39.836139
7933 17:16:39.836226 Set Vref, RX VrefLevel [Byte0]: 34
7934 17:16:39.839344 [Byte1]: 34
7935 17:16:39.843957
7936 17:16:39.844037 Set Vref, RX VrefLevel [Byte0]: 35
7937 17:16:39.847460 [Byte1]: 35
7938 17:16:39.851307
7939 17:16:39.851387 Set Vref, RX VrefLevel [Byte0]: 36
7940 17:16:39.854718 [Byte1]: 36
7941 17:16:39.859261
7942 17:16:39.859375 Set Vref, RX VrefLevel [Byte0]: 37
7943 17:16:39.861790 [Byte1]: 37
7944 17:16:39.866556
7945 17:16:39.866636 Set Vref, RX VrefLevel [Byte0]: 38
7946 17:16:39.869618 [Byte1]: 38
7947 17:16:39.873904
7948 17:16:39.873994 Set Vref, RX VrefLevel [Byte0]: 39
7949 17:16:39.877189 [Byte1]: 39
7950 17:16:39.881503
7951 17:16:39.881581 Set Vref, RX VrefLevel [Byte0]: 40
7952 17:16:39.884897 [Byte1]: 40
7953 17:16:39.889160
7954 17:16:39.889240 Set Vref, RX VrefLevel [Byte0]: 41
7955 17:16:39.892407 [Byte1]: 41
7956 17:16:39.896517
7957 17:16:39.896597 Set Vref, RX VrefLevel [Byte0]: 42
7958 17:16:39.899926 [Byte1]: 42
7959 17:16:39.904575
7960 17:16:39.904655 Set Vref, RX VrefLevel [Byte0]: 43
7961 17:16:39.907903 [Byte1]: 43
7962 17:16:39.911792
7963 17:16:39.911876 Set Vref, RX VrefLevel [Byte0]: 44
7964 17:16:39.915301 [Byte1]: 44
7965 17:16:39.919787
7966 17:16:39.919867 Set Vref, RX VrefLevel [Byte0]: 45
7967 17:16:39.923097 [Byte1]: 45
7968 17:16:39.926892
7969 17:16:39.926974 Set Vref, RX VrefLevel [Byte0]: 46
7970 17:16:39.930338 [Byte1]: 46
7971 17:16:39.934458
7972 17:16:39.934545 Set Vref, RX VrefLevel [Byte0]: 47
7973 17:16:39.937711 [Byte1]: 47
7974 17:16:39.942239
7975 17:16:39.942324 Set Vref, RX VrefLevel [Byte0]: 48
7976 17:16:39.945659 [Byte1]: 48
7977 17:16:39.949763
7978 17:16:39.949849 Set Vref, RX VrefLevel [Byte0]: 49
7979 17:16:39.952993 [Byte1]: 49
7980 17:16:39.957484
7981 17:16:39.957568 Set Vref, RX VrefLevel [Byte0]: 50
7982 17:16:39.960407 [Byte1]: 50
7983 17:16:39.964898
7984 17:16:39.964989 Set Vref, RX VrefLevel [Byte0]: 51
7985 17:16:39.968301 [Byte1]: 51
7986 17:16:39.972845
7987 17:16:39.972927 Set Vref, RX VrefLevel [Byte0]: 52
7988 17:16:39.975824 [Byte1]: 52
7989 17:16:39.980043
7990 17:16:39.980121 Set Vref, RX VrefLevel [Byte0]: 53
7991 17:16:39.983419 [Byte1]: 53
7992 17:16:39.987407
7993 17:16:39.987495 Set Vref, RX VrefLevel [Byte0]: 54
7994 17:16:39.991275 [Byte1]: 54
7995 17:16:39.995118
7996 17:16:39.995205 Set Vref, RX VrefLevel [Byte0]: 55
7997 17:16:39.998484 [Byte1]: 55
7998 17:16:40.002509
7999 17:16:40.002589 Set Vref, RX VrefLevel [Byte0]: 56
8000 17:16:40.005926 [Byte1]: 56
8001 17:16:40.010504
8002 17:16:40.010595 Set Vref, RX VrefLevel [Byte0]: 57
8003 17:16:40.013756 [Byte1]: 57
8004 17:16:40.017734
8005 17:16:40.017823 Set Vref, RX VrefLevel [Byte0]: 58
8006 17:16:40.020978 [Byte1]: 58
8007 17:16:40.025672
8008 17:16:40.025757 Set Vref, RX VrefLevel [Byte0]: 59
8009 17:16:40.029026 [Byte1]: 59
8010 17:16:40.033053
8011 17:16:40.033139 Set Vref, RX VrefLevel [Byte0]: 60
8012 17:16:40.036484 [Byte1]: 60
8013 17:16:40.040451
8014 17:16:40.040537 Set Vref, RX VrefLevel [Byte0]: 61
8015 17:16:40.043654 [Byte1]: 61
8016 17:16:40.048362
8017 17:16:40.048448 Set Vref, RX VrefLevel [Byte0]: 62
8018 17:16:40.051601 [Byte1]: 62
8019 17:16:40.055688
8020 17:16:40.055774 Set Vref, RX VrefLevel [Byte0]: 63
8021 17:16:40.058964 [Byte1]: 63
8022 17:16:40.063590
8023 17:16:40.063679 Set Vref, RX VrefLevel [Byte0]: 64
8024 17:16:40.066835 [Byte1]: 64
8025 17:16:40.071207
8026 17:16:40.071296 Set Vref, RX VrefLevel [Byte0]: 65
8027 17:16:40.074540 [Byte1]: 65
8028 17:16:40.078273
8029 17:16:40.078363 Set Vref, RX VrefLevel [Byte0]: 66
8030 17:16:40.081525 [Byte1]: 66
8031 17:16:40.085978
8032 17:16:40.086059 Set Vref, RX VrefLevel [Byte0]: 67
8033 17:16:40.089280 [Byte1]: 67
8034 17:16:40.093563
8035 17:16:40.093644 Set Vref, RX VrefLevel [Byte0]: 68
8036 17:16:40.096945 [Byte1]: 68
8037 17:16:40.100966
8038 17:16:40.101054 Set Vref, RX VrefLevel [Byte0]: 69
8039 17:16:40.104191 [Byte1]: 69
8040 17:16:40.108828
8041 17:16:40.108914 Set Vref, RX VrefLevel [Byte0]: 70
8042 17:16:40.112204 [Byte1]: 70
8043 17:16:40.116222
8044 17:16:40.116318 Set Vref, RX VrefLevel [Byte0]: 71
8045 17:16:40.119402 [Byte1]: 71
8046 17:16:40.123932
8047 17:16:40.124027 Set Vref, RX VrefLevel [Byte0]: 72
8048 17:16:40.127339 [Byte1]: 72
8049 17:16:40.131303
8050 17:16:40.131384 Set Vref, RX VrefLevel [Byte0]: 73
8051 17:16:40.134553 [Byte1]: 73
8052 17:16:40.139235
8053 17:16:40.139326 Set Vref, RX VrefLevel [Byte0]: 74
8054 17:16:40.142432 [Byte1]: 74
8055 17:16:40.147105
8056 17:16:40.147191 Final RX Vref Byte 0 = 55 to rank0
8057 17:16:40.149803 Final RX Vref Byte 1 = 60 to rank0
8058 17:16:40.153251 Final RX Vref Byte 0 = 55 to rank1
8059 17:16:40.156618 Final RX Vref Byte 1 = 60 to rank1==
8060 17:16:40.159834 Dram Type= 6, Freq= 0, CH_0, rank 0
8061 17:16:40.166503 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8062 17:16:40.166594 ==
8063 17:16:40.166663 DQS Delay:
8064 17:16:40.169705 DQS0 = 0, DQS1 = 0
8065 17:16:40.169791 DQM Delay:
8066 17:16:40.169859 DQM0 = 129, DQM1 = 123
8067 17:16:40.173110 DQ Delay:
8068 17:16:40.176463 DQ0 =130, DQ1 =130, DQ2 =128, DQ3 =124
8069 17:16:40.179526 DQ4 =130, DQ5 =120, DQ6 =136, DQ7 =134
8070 17:16:40.182544 DQ8 =112, DQ9 =112, DQ10 =124, DQ11 =120
8071 17:16:40.185815 DQ12 =130, DQ13 =128, DQ14 =132, DQ15 =130
8072 17:16:40.185901
8073 17:16:40.185969
8074 17:16:40.186033
8075 17:16:40.189288 [DramC_TX_OE_Calibration] TA2
8076 17:16:40.192436 Original DQ_B0 (3 6) =30, OEN = 27
8077 17:16:40.195509 Original DQ_B1 (3 6) =30, OEN = 27
8078 17:16:40.198830 24, 0x0, End_B0=24 End_B1=24
8079 17:16:40.202272 25, 0x0, End_B0=25 End_B1=25
8080 17:16:40.202354 26, 0x0, End_B0=26 End_B1=26
8081 17:16:40.205503 27, 0x0, End_B0=27 End_B1=27
8082 17:16:40.209058 28, 0x0, End_B0=28 End_B1=28
8083 17:16:40.211992 29, 0x0, End_B0=29 End_B1=29
8084 17:16:40.215305 30, 0x0, End_B0=30 End_B1=30
8085 17:16:40.215395 31, 0x4141, End_B0=30 End_B1=30
8086 17:16:40.218579 Byte0 end_step=30 best_step=27
8087 17:16:40.221978 Byte1 end_step=30 best_step=27
8088 17:16:40.225286 Byte0 TX OE(2T, 0.5T) = (3, 3)
8089 17:16:40.228503 Byte1 TX OE(2T, 0.5T) = (3, 3)
8090 17:16:40.228585
8091 17:16:40.228701
8092 17:16:40.235108 [DQSOSCAuto] RK0, (LSB)MR18= 0x1815, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 397 ps
8093 17:16:40.238503 CH0 RK0: MR19=303, MR18=1815
8094 17:16:40.245224 CH0_RK0: MR19=0x303, MR18=0x1815, DQSOSC=397, MR23=63, INC=23, DEC=15
8095 17:16:40.245323
8096 17:16:40.248550 ----->DramcWriteLeveling(PI) begin...
8097 17:16:40.248629 ==
8098 17:16:40.251932 Dram Type= 6, Freq= 0, CH_0, rank 1
8099 17:16:40.255170 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8100 17:16:40.258566 ==
8101 17:16:40.258644 Write leveling (Byte 0): 35 => 35
8102 17:16:40.261742 Write leveling (Byte 1): 28 => 28
8103 17:16:40.265240 DramcWriteLeveling(PI) end<-----
8104 17:16:40.265320
8105 17:16:40.265404 ==
8106 17:16:40.267860 Dram Type= 6, Freq= 0, CH_0, rank 1
8107 17:16:40.274597 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8108 17:16:40.274681 ==
8109 17:16:40.277663 [Gating] SW mode calibration
8110 17:16:40.284500 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8111 17:16:40.287922 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8112 17:16:40.294386 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8113 17:16:40.297740 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8114 17:16:40.301047 1 4 8 | B1->B0 | 2323 2a2a | 0 0 | (0 0) (0 0)
8115 17:16:40.307692 1 4 12 | B1->B0 | 2323 3232 | 0 0 | (0 0) (0 0)
8116 17:16:40.311095 1 4 16 | B1->B0 | 2322 3434 | 1 1 | (0 0) (1 1)
8117 17:16:40.314273 1 4 20 | B1->B0 | 3333 3434 | 1 1 | (1 1) (1 1)
8118 17:16:40.320288 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8119 17:16:40.323636 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8120 17:16:40.326851 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8121 17:16:40.333514 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8122 17:16:40.336887 1 5 8 | B1->B0 | 3434 2f2f | 1 1 | (1 1) (1 0)
8123 17:16:40.340259 1 5 12 | B1->B0 | 3434 2626 | 1 0 | (1 1) (0 0)
8124 17:16:40.346705 1 5 16 | B1->B0 | 3434 2323 | 1 0 | (1 0) (0 0)
8125 17:16:40.350048 1 5 20 | B1->B0 | 2a2a 2323 | 0 0 | (1 0) (0 0)
8126 17:16:40.353309 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (1 0) (0 0)
8127 17:16:40.360018 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8128 17:16:40.363144 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8129 17:16:40.366579 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8130 17:16:40.372759 1 6 8 | B1->B0 | 2323 3d3d | 0 1 | (0 0) (0 0)
8131 17:16:40.376473 1 6 12 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8132 17:16:40.379632 1 6 16 | B1->B0 | 2626 4646 | 0 0 | (0 0) (0 0)
8133 17:16:40.386094 1 6 20 | B1->B0 | 4242 4646 | 0 0 | (0 0) (0 0)
8134 17:16:40.389301 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8135 17:16:40.392577 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8136 17:16:40.399033 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8137 17:16:40.402313 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8138 17:16:40.405883 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8139 17:16:40.409129
8140 17:16:40.412434 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (1 1)
8141 17:16:40.415624 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8142 17:16:40.422349 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8143 17:16:40.425514 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8144 17:16:40.428883 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8145 17:16:40.435487 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8146 17:16:40.438652 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8147 17:16:40.442025 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8148 17:16:40.447990 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8149 17:16:40.451950 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8150 17:16:40.454733 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8151 17:16:40.461294 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8152 17:16:40.464705 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8153 17:16:40.468016 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8154 17:16:40.474447 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8155 17:16:40.477677 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8156 17:16:40.481102 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8157 17:16:40.484254 Total UI for P1: 0, mck2ui 16
8158 17:16:40.487999 best dqsien dly found for B0: ( 1, 9, 6)
8159 17:16:40.494391 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (0 0)
8160 17:16:40.497648 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8161 17:16:40.500881 1 9 24 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8162 17:16:40.507289 1 9 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8163 17:16:40.507371 Total UI for P1: 0, mck2ui 16
8164 17:16:40.513709 best dqsien dly found for B1: ( 1, 9, 22)
8165 17:16:40.516956 best DQS0 dly(MCK, UI, PI) = (1, 9, 6)
8166 17:16:40.520226 best DQS1 dly(MCK, UI, PI) = (1, 9, 22)
8167 17:16:40.520311
8168 17:16:40.523868 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 6)
8169 17:16:40.527202 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 22)
8170 17:16:40.530508 [Gating] SW calibration Done
8171 17:16:40.530592 ==
8172 17:16:40.533561 Dram Type= 6, Freq= 0, CH_0, rank 1
8173 17:16:40.537034 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8174 17:16:40.537116 ==
8175 17:16:40.540294 RX Vref Scan: 0
8176 17:16:40.540376
8177 17:16:40.540445 RX Vref 0 -> 0, step: 1
8178 17:16:40.543528
8179 17:16:40.543628 RX Delay 0 -> 252, step: 8
8180 17:16:40.550092 iDelay=200, Bit 0, Center 131 (80 ~ 183) 104
8181 17:16:40.553252 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8182 17:16:40.556540 iDelay=200, Bit 2, Center 131 (80 ~ 183) 104
8183 17:16:40.559617 iDelay=200, Bit 3, Center 127 (72 ~ 183) 112
8184 17:16:40.562912 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8185 17:16:40.569449 iDelay=200, Bit 5, Center 119 (64 ~ 175) 112
8186 17:16:40.572715 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8187 17:16:40.576620 iDelay=200, Bit 7, Center 139 (80 ~ 199) 120
8188 17:16:40.579695 iDelay=200, Bit 8, Center 115 (56 ~ 175) 120
8189 17:16:40.582808 iDelay=200, Bit 9, Center 111 (56 ~ 167) 112
8190 17:16:40.589598 iDelay=200, Bit 10, Center 127 (64 ~ 191) 128
8191 17:16:40.592599 iDelay=200, Bit 11, Center 115 (56 ~ 175) 120
8192 17:16:40.596107 iDelay=200, Bit 12, Center 127 (72 ~ 183) 112
8193 17:16:40.599120 iDelay=200, Bit 13, Center 131 (72 ~ 191) 120
8194 17:16:40.606109 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8195 17:16:40.608818 iDelay=200, Bit 15, Center 131 (72 ~ 191) 120
8196 17:16:40.608928 ==
8197 17:16:40.612014 Dram Type= 6, Freq= 0, CH_0, rank 1
8198 17:16:40.615425 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8199 17:16:40.615554 ==
8200 17:16:40.618654 DQS Delay:
8201 17:16:40.618741 DQS0 = 0, DQS1 = 0
8202 17:16:40.618826 DQM Delay:
8203 17:16:40.621812 DQM0 = 132, DQM1 = 124
8204 17:16:40.621900 DQ Delay:
8205 17:16:40.625590 DQ0 =131, DQ1 =135, DQ2 =131, DQ3 =127
8206 17:16:40.628856 DQ4 =135, DQ5 =119, DQ6 =143, DQ7 =139
8207 17:16:40.632064 DQ8 =115, DQ9 =111, DQ10 =127, DQ11 =115
8208 17:16:40.635383
8209 17:16:40.638620 DQ12 =127, DQ13 =131, DQ14 =135, DQ15 =131
8210 17:16:40.638707
8211 17:16:40.638777
8212 17:16:40.638845 ==
8213 17:16:40.641815 Dram Type= 6, Freq= 0, CH_0, rank 1
8214 17:16:40.645188 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8215 17:16:40.645278 ==
8216 17:16:40.645351
8217 17:16:40.645416
8218 17:16:40.648299 TX Vref Scan disable
8219 17:16:40.651659 == TX Byte 0 ==
8220 17:16:40.654899 Update DQ dly =991 (3 ,6, 31) DQ OEN =(3 ,3)
8221 17:16:40.658128 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8222 17:16:40.661976 == TX Byte 1 ==
8223 17:16:40.665286 Update DQ dly =984 (3 ,6, 24) DQ OEN =(3 ,3)
8224 17:16:40.667980 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8225 17:16:40.668065 ==
8226 17:16:40.671232 Dram Type= 6, Freq= 0, CH_0, rank 1
8227 17:16:40.674402 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8228 17:16:40.677641
8229 17:16:40.677730 ==
8230 17:16:40.690156
8231 17:16:40.693215 TX Vref early break, caculate TX vref
8232 17:16:40.696475 TX Vref=16, minBit 0, minWin=23, winSum=376
8233 17:16:40.699661 TX Vref=18, minBit 8, minWin=23, winSum=391
8234 17:16:40.702823 TX Vref=20, minBit 2, minWin=24, winSum=398
8235 17:16:40.706045 TX Vref=22, minBit 1, minWin=25, winSum=409
8236 17:16:40.709719 TX Vref=24, minBit 1, minWin=25, winSum=416
8237 17:16:40.716301 TX Vref=26, minBit 3, minWin=25, winSum=422
8238 17:16:40.719430 TX Vref=28, minBit 1, minWin=25, winSum=419
8239 17:16:40.722401 TX Vref=30, minBit 1, minWin=25, winSum=417
8240 17:16:40.725702 TX Vref=32, minBit 0, minWin=25, winSum=413
8241 17:16:40.728979 TX Vref=34, minBit 0, minWin=24, winSum=399
8242 17:16:40.735496 [TxChooseVref] Worse bit 3, Min win 25, Win sum 422, Final Vref 26
8243 17:16:40.735583
8244 17:16:40.738854 Final TX Range 0 Vref 26
8245 17:16:40.738939
8246 17:16:40.739006 ==
8247 17:16:40.742582 Dram Type= 6, Freq= 0, CH_0, rank 1
8248 17:16:40.745248 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8249 17:16:40.745326 ==
8250 17:16:40.745396
8251 17:16:40.749105
8252 17:16:40.749182 TX Vref Scan disable
8253 17:16:40.755601 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8254 17:16:40.755681 == TX Byte 0 ==
8255 17:16:40.758852 u2DelayCellOfst[0]=10 cells (3 PI)
8256 17:16:40.762139 u2DelayCellOfst[1]=14 cells (4 PI)
8257 17:16:40.765387 u2DelayCellOfst[2]=7 cells (2 PI)
8258 17:16:40.768570 u2DelayCellOfst[3]=10 cells (3 PI)
8259 17:16:40.771923 u2DelayCellOfst[4]=7 cells (2 PI)
8260 17:16:40.775088 u2DelayCellOfst[5]=0 cells (0 PI)
8261 17:16:40.778217 u2DelayCellOfst[6]=14 cells (4 PI)
8262 17:16:40.781373 u2DelayCellOfst[7]=14 cells (4 PI)
8263 17:16:40.784645 Update DQ dly =989 (3 ,6, 29) DQ OEN =(3 ,3)
8264 17:16:40.788327 Update DQM dly =991 (3 ,6, 31) DQM OEN =(3 ,3)
8265 17:16:40.791320 == TX Byte 1 ==
8266 17:16:40.795034 u2DelayCellOfst[8]=0 cells (0 PI)
8267 17:16:40.797932 u2DelayCellOfst[9]=0 cells (0 PI)
8268 17:16:40.801223 u2DelayCellOfst[10]=3 cells (1 PI)
8269 17:16:40.804376 u2DelayCellOfst[11]=3 cells (1 PI)
8270 17:16:40.808224 u2DelayCellOfst[12]=10 cells (3 PI)
8271 17:16:40.811429 u2DelayCellOfst[13]=10 cells (3 PI)
8272 17:16:40.814231 u2DelayCellOfst[14]=14 cells (4 PI)
8273 17:16:40.814335 u2DelayCellOfst[15]=10 cells (3 PI)
8274 17:16:40.817990
8275 17:16:40.821403 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8276 17:16:40.824473 Update DQM dly =984 (3 ,6, 24) DQM OEN =(3 ,3)
8277 17:16:40.827642 DramC Write-DBI on
8278 17:16:40.827725 ==
8279 17:16:40.830873 Dram Type= 6, Freq= 0, CH_0, rank 1
8280 17:16:40.834091 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8281 17:16:40.834180 ==
8282 17:16:40.834246
8283 17:16:40.834312
8284 17:16:40.837413 TX Vref Scan disable
8285 17:16:40.841224 == TX Byte 0 ==
8286 17:16:40.844029 Update DQM dly =734 (2 ,6, 30) DQM OEN =(3 ,3)
8287 17:16:40.844109 == TX Byte 1 ==
8288 17:16:40.850558 Update DQM dly =725 (2 ,6, 21) DQM OEN =(3 ,3)
8289 17:16:40.850646 DramC Write-DBI off
8290 17:16:40.850714
8291 17:16:40.850774 [DATLAT]
8292 17:16:40.853781 Freq=1600, CH0 RK1
8293 17:16:40.853884
8294 17:16:40.856990 DATLAT Default: 0xf
8295 17:16:40.857069 0, 0xFFFF, sum = 0
8296 17:16:40.860351 1, 0xFFFF, sum = 0
8297 17:16:40.860448 2, 0xFFFF, sum = 0
8298 17:16:40.863497 3, 0xFFFF, sum = 0
8299 17:16:40.863589 4, 0xFFFF, sum = 0
8300 17:16:40.866639 5, 0xFFFF, sum = 0
8301 17:16:40.866732 6, 0xFFFF, sum = 0
8302 17:16:40.869913 7, 0xFFFF, sum = 0
8303 17:16:40.870001 8, 0xFFFF, sum = 0
8304 17:16:40.873841 9, 0xFFFF, sum = 0
8305 17:16:40.873942 10, 0xFFFF, sum = 0
8306 17:16:40.876872 11, 0xFFFF, sum = 0
8307 17:16:40.876961 12, 0xFFFF, sum = 0
8308 17:16:40.880151
8309 17:16:40.880237 13, 0xFFFF, sum = 0
8310 17:16:40.883320 14, 0x0, sum = 1
8311 17:16:40.883410 15, 0x0, sum = 2
8312 17:16:40.883477 16, 0x0, sum = 3
8313 17:16:40.886584 17, 0x0, sum = 4
8314 17:16:40.886667 best_step = 15
8315 17:16:40.886731
8316 17:16:40.889623 ==
8317 17:16:40.889708 Dram Type= 6, Freq= 0, CH_0, rank 1
8318 17:16:40.893278
8319 17:16:40.896529 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8320 17:16:40.896608 ==
8321 17:16:40.896682 RX Vref Scan: 0
8322 17:16:40.896745
8323 17:16:40.899795 RX Vref 0 -> 0, step: 1
8324 17:16:40.899875
8325 17:16:40.902877 RX Delay 11 -> 252, step: 4
8326 17:16:40.906175 iDelay=191, Bit 0, Center 128 (79 ~ 178) 100
8327 17:16:40.912292 iDelay=191, Bit 1, Center 132 (79 ~ 186) 108
8328 17:16:40.916352 iDelay=191, Bit 2, Center 124 (71 ~ 178) 108
8329 17:16:40.919114 iDelay=191, Bit 3, Center 126 (75 ~ 178) 104
8330 17:16:40.922456 iDelay=191, Bit 4, Center 132 (83 ~ 182) 100
8331 17:16:40.925657 iDelay=191, Bit 5, Center 120 (67 ~ 174) 108
8332 17:16:40.932584 iDelay=191, Bit 6, Center 138 (87 ~ 190) 104
8333 17:16:40.935935 iDelay=191, Bit 7, Center 134 (83 ~ 186) 104
8334 17:16:40.938999 iDelay=191, Bit 8, Center 114 (63 ~ 166) 104
8335 17:16:40.941611 iDelay=191, Bit 9, Center 110 (59 ~ 162) 104
8336 17:16:40.944914 iDelay=191, Bit 10, Center 128 (75 ~ 182) 108
8337 17:16:40.948881
8338 17:16:40.952091 iDelay=191, Bit 11, Center 118 (67 ~ 170) 104
8339 17:16:40.955231 iDelay=191, Bit 12, Center 126 (75 ~ 178) 104
8340 17:16:40.958557 iDelay=191, Bit 13, Center 130 (79 ~ 182) 104
8341 17:16:40.961545 iDelay=191, Bit 14, Center 134 (83 ~ 186) 104
8342 17:16:40.968150 iDelay=191, Bit 15, Center 132 (79 ~ 186) 108
8343 17:16:40.968241 ==
8344 17:16:40.971425 Dram Type= 6, Freq= 0, CH_0, rank 1
8345 17:16:40.974549 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8346 17:16:40.974637 ==
8347 17:16:40.974701 DQS Delay:
8348 17:16:40.977877 DQS0 = 0, DQS1 = 0
8349 17:16:40.977954 DQM Delay:
8350 17:16:40.981085 DQM0 = 129, DQM1 = 124
8351 17:16:40.981165 DQ Delay:
8352 17:16:40.984420 DQ0 =128, DQ1 =132, DQ2 =124, DQ3 =126
8353 17:16:40.987603 DQ4 =132, DQ5 =120, DQ6 =138, DQ7 =134
8354 17:16:40.990669 DQ8 =114, DQ9 =110, DQ10 =128, DQ11 =118
8355 17:16:40.997566 DQ12 =126, DQ13 =130, DQ14 =134, DQ15 =132
8356 17:16:40.997659
8357 17:16:40.997726
8358 17:16:40.997785
8359 17:16:41.001045 [DramC_TX_OE_Calibration] TA2
8360 17:16:41.001121 Original DQ_B0 (3 6) =30, OEN = 27
8361 17:16:41.004321
8362 17:16:41.004400 Original DQ_B1 (3 6) =30, OEN = 27
8363 17:16:41.007598 24, 0x0, End_B0=24 End_B1=24
8364 17:16:41.010674 25, 0x0, End_B0=25 End_B1=25
8365 17:16:41.013859 26, 0x0, End_B0=26 End_B1=26
8366 17:16:41.016995 27, 0x0, End_B0=27 End_B1=27
8367 17:16:41.017089 28, 0x0, End_B0=28 End_B1=28
8368 17:16:41.020289 29, 0x0, End_B0=29 End_B1=29
8369 17:16:41.023573 30, 0x0, End_B0=30 End_B1=30
8370 17:16:41.026773 31, 0x4141, End_B0=30 End_B1=30
8371 17:16:41.030584 Byte0 end_step=30 best_step=27
8372 17:16:41.033858 Byte1 end_step=30 best_step=27
8373 17:16:41.033935 Byte0 TX OE(2T, 0.5T) = (3, 3)
8374 17:16:41.037116 Byte1 TX OE(2T, 0.5T) = (3, 3)
8375 17:16:41.037192
8376 17:16:41.037254
8377 17:16:41.046707 [DQSOSCAuto] RK1, (LSB)MR18= 0x1311, (MSB)MR19= 0x303, tDQSOscB0 = 401 ps tDQSOscB1 = 400 ps
8378 17:16:41.049991 CH0 RK1: MR19=303, MR18=1311
8379 17:16:41.053388 CH0_RK1: MR19=0x303, MR18=0x1311, DQSOSC=400, MR23=63, INC=23, DEC=15
8380 17:16:41.056475 [RxdqsGatingPostProcess] freq 1600
8381 17:16:41.063079 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
8382 17:16:41.066373 best DQS0 dly(2T, 0.5T) = (1, 1)
8383 17:16:41.069544 best DQS1 dly(2T, 0.5T) = (1, 1)
8384 17:16:41.072668 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8385 17:16:41.076036 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8386 17:16:41.079294 best DQS0 dly(2T, 0.5T) = (1, 1)
8387 17:16:41.082531 best DQS1 dly(2T, 0.5T) = (1, 1)
8388 17:16:41.086131 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
8389 17:16:41.089413 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
8390 17:16:41.092517 Pre-setting of DQS Precalculation
8391 17:16:41.095778 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
8392 17:16:41.095874 ==
8393 17:16:41.099402 Dram Type= 6, Freq= 0, CH_1, rank 0
8394 17:16:41.102336 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8395 17:16:41.102429 ==
8396 17:16:41.108770 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8397 17:16:41.112599 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8398 17:16:41.119069 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8399 17:16:41.122347 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8400 17:16:41.132394 [CA 0] Center 42 (12~72) winsize 61
8401 17:16:41.135679 [CA 1] Center 42 (12~73) winsize 62
8402 17:16:41.138809 [CA 2] Center 38 (9~68) winsize 60
8403 17:16:41.142768 [CA 3] Center 37 (8~67) winsize 60
8404 17:16:41.145415 [CA 4] Center 38 (8~68) winsize 61
8405 17:16:41.149075 [CA 5] Center 37 (7~67) winsize 61
8406 17:16:41.149238
8407 17:16:41.152400 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8408 17:16:41.152551
8409 17:16:41.155614 [CATrainingPosCal] consider 1 rank data
8410 17:16:41.158661 u2DelayCellTimex100 = 275/100 ps
8411 17:16:41.165316 CA0 delay=42 (12~72),Diff = 5 PI (17 cell)
8412 17:16:41.168528 CA1 delay=42 (12~73),Diff = 5 PI (17 cell)
8413 17:16:41.172324 CA2 delay=38 (9~68),Diff = 1 PI (3 cell)
8414 17:16:41.175521 CA3 delay=37 (8~67),Diff = 0 PI (0 cell)
8415 17:16:41.178747 CA4 delay=38 (8~68),Diff = 1 PI (3 cell)
8416 17:16:41.182087 CA5 delay=37 (7~67),Diff = 0 PI (0 cell)
8417 17:16:41.182214
8418 17:16:41.185370 CA PerBit enable=1, Macro0, CA PI delay=37
8419 17:16:41.185489
8420 17:16:41.188766 [CBTSetCACLKResult] CA Dly = 37
8421 17:16:41.191983 CS Dly: 7 (0~38)
8422 17:16:41.195042 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8423 17:16:41.198160 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8424 17:16:41.198276 ==
8425 17:16:41.201441 Dram Type= 6, Freq= 0, CH_1, rank 1
8426 17:16:41.207811 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8427 17:16:41.207939 ==
8428 17:16:41.211132 pi_start=-16, pi_end=95, pi_step=1, new_cbt_mode=1, autok=0
8429 17:16:41.217996 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=1
8430 17:16:41.221237 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=1
8431 17:16:41.227874 u1VRangeStart=0, u1VRangeEnd=0, u1VrefScanStart=22, u1VrefScanEnd=32
8432 17:16:41.235396 [CA 0] Center 41 (11~71) winsize 61
8433 17:16:41.238786 [CA 1] Center 41 (12~71) winsize 60
8434 17:16:41.242013 [CA 2] Center 37 (8~67) winsize 60
8435 17:16:41.245277 [CA 3] Center 36 (7~66) winsize 60
8436 17:16:41.248899 [CA 4] Center 37 (7~67) winsize 61
8437 17:16:41.252274 [CA 5] Center 36 (6~66) winsize 61
8438 17:16:41.252360
8439 17:16:41.255404 [CmdBusTrainingLP45] Vref(ca) range 0: 32
8440 17:16:41.255498
8441 17:16:41.262097 [CATrainingPosCal] consider 2 rank data
8442 17:16:41.262197 u2DelayCellTimex100 = 275/100 ps
8443 17:16:41.268612 CA0 delay=41 (12~71),Diff = 5 PI (17 cell)
8444 17:16:41.271289 CA1 delay=41 (12~71),Diff = 5 PI (17 cell)
8445 17:16:41.274999 CA2 delay=38 (9~67),Diff = 2 PI (7 cell)
8446 17:16:41.278383 CA3 delay=37 (8~66),Diff = 1 PI (3 cell)
8447 17:16:41.281522 CA4 delay=37 (8~67),Diff = 1 PI (3 cell)
8448 17:16:41.284968 CA5 delay=36 (7~66),Diff = 0 PI (0 cell)
8449 17:16:41.285049
8450 17:16:41.288236 CA PerBit enable=1, Macro0, CA PI delay=36
8451 17:16:41.288317
8452 17:16:41.291470 [CBTSetCACLKResult] CA Dly = 36
8453 17:16:41.294666 CS Dly: 9 (0~42)
8454 17:16:41.297648 [DramcModeRegInit_CATerm] CH1 RK0 bWorkAround=0
8455 17:16:41.300967 [DramcModeRegInit_CATerm] CH1 RK1 bWorkAround=0
8456 17:16:41.301047
8457 17:16:41.304070 ----->DramcWriteLeveling(PI) begin...
8458 17:16:41.307717 ==
8459 17:16:41.310727 Dram Type= 6, Freq= 0, CH_1, rank 0
8460 17:16:41.313963 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8461 17:16:41.314053 ==
8462 17:16:41.317096 Write leveling (Byte 0): 24 => 24
8463 17:16:41.320379 Write leveling (Byte 1): 27 => 27
8464 17:16:41.323690 DramcWriteLeveling(PI) end<-----
8465 17:16:41.323766
8466 17:16:41.323830 ==
8467 17:16:41.327472 Dram Type= 6, Freq= 0, CH_1, rank 0
8468 17:16:41.330494 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8469 17:16:41.330572 ==
8470 17:16:41.333676 [Gating] SW mode calibration
8471 17:16:41.340006 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8472 17:16:41.346527 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8473 17:16:41.349754 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8474 17:16:41.352891 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8475 17:16:41.359738 1 4 8 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8476 17:16:41.363055 1 4 12 | B1->B0 | 2a2a 3434 | 0 0 | (0 0) (0 0)
8477 17:16:41.366401 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8478 17:16:41.372916 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8479 17:16:41.376053 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8480 17:16:41.379364 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8481 17:16:41.382591
8482 17:16:41.385869 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8483 17:16:41.389076 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8484 17:16:41.395622 1 5 8 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8485 17:16:41.398782 1 5 12 | B1->B0 | 3333 2727 | 1 0 | (1 0) (1 0)
8486 17:16:41.402453 1 5 16 | B1->B0 | 2424 2323 | 0 0 | (1 0) (0 0)
8487 17:16:41.408994 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8488 17:16:41.412279 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8489 17:16:41.415402 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8490 17:16:41.422417 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8491 17:16:41.425593 1 6 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8492 17:16:41.428776 1 6 8 | B1->B0 | 2323 2626 | 0 0 | (0 0) (0 0)
8493 17:16:41.435393 1 6 12 | B1->B0 | 3030 4646 | 0 0 | (0 0) (0 0)
8494 17:16:41.438587 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8495 17:16:41.441815 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8496 17:16:41.448452 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8497 17:16:41.451514 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8498 17:16:41.454647 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8499 17:16:41.461667 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8500 17:16:41.464745 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8501 17:16:41.467980 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8502 17:16:41.474586 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8503 17:16:41.477664 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8504 17:16:41.480948 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8505 17:16:41.487624 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8506 17:16:41.490949 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8507 17:16:41.494053 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8508 17:16:41.500551 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8509 17:16:41.503745 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8510 17:16:41.507534 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8511 17:16:41.513897 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8512 17:16:41.516971 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8513 17:16:41.520181 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8514 17:16:41.527297 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8515 17:16:41.530555 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8516 17:16:41.533932 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8517 17:16:41.540186 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (1 0)
8518 17:16:41.543447 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8519 17:16:41.546643 Total UI for P1: 0, mck2ui 16
8520 17:16:41.550009 best dqsien dly found for B0: ( 1, 9, 10)
8521 17:16:41.553284 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8522 17:16:41.556303 Total UI for P1: 0, mck2ui 16
8523 17:16:41.559466 best dqsien dly found for B1: ( 1, 9, 14)
8524 17:16:41.563436 best DQS0 dly(MCK, UI, PI) = (1, 9, 10)
8525 17:16:41.566013 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8526 17:16:41.569812
8527 17:16:41.569890
8528 17:16:41.573075 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 10)
8529 17:16:41.576402 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8530 17:16:41.579612 [Gating] SW calibration Done
8531 17:16:41.579686 ==
8532 17:16:41.582850 Dram Type= 6, Freq= 0, CH_1, rank 0
8533 17:16:41.585962 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8534 17:16:41.586039 ==
8535 17:16:41.589418 RX Vref Scan: 0
8536 17:16:41.589496
8537 17:16:41.589560 RX Vref 0 -> 0, step: 1
8538 17:16:41.589633
8539 17:16:41.592640 RX Delay 0 -> 252, step: 8
8540 17:16:41.595795 iDelay=200, Bit 0, Center 139 (88 ~ 191) 104
8541 17:16:41.602173 iDelay=200, Bit 1, Center 131 (80 ~ 183) 104
8542 17:16:41.605718 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8543 17:16:41.609017 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8544 17:16:41.612517 iDelay=200, Bit 4, Center 131 (80 ~ 183) 104
8545 17:16:41.615763 iDelay=200, Bit 5, Center 143 (88 ~ 199) 112
8546 17:16:41.621957 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8547 17:16:41.625087 iDelay=200, Bit 7, Center 131 (80 ~ 183) 104
8548 17:16:41.628373 iDelay=200, Bit 8, Center 115 (64 ~ 167) 104
8549 17:16:41.631695 iDelay=200, Bit 9, Center 119 (64 ~ 175) 112
8550 17:16:41.634864 iDelay=200, Bit 10, Center 131 (80 ~ 183) 104
8551 17:16:41.641880 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8552 17:16:41.645164 iDelay=200, Bit 12, Center 139 (88 ~ 191) 104
8553 17:16:41.648195 iDelay=200, Bit 13, Center 143 (88 ~ 199) 112
8554 17:16:41.651600 iDelay=200, Bit 14, Center 139 (88 ~ 191) 104
8555 17:16:41.658115 iDelay=200, Bit 15, Center 139 (88 ~ 191) 104
8556 17:16:41.658196 ==
8557 17:16:41.661679 Dram Type= 6, Freq= 0, CH_1, rank 0
8558 17:16:41.664979 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8559 17:16:41.665060 ==
8560 17:16:41.665129 DQS Delay:
8561 17:16:41.668087 DQS0 = 0, DQS1 = 0
8562 17:16:41.668202 DQM Delay:
8563 17:16:41.671305 DQM0 = 134, DQM1 = 131
8564 17:16:41.671384 DQ Delay:
8565 17:16:41.674638 DQ0 =139, DQ1 =131, DQ2 =123, DQ3 =135
8566 17:16:41.677879 DQ4 =131, DQ5 =143, DQ6 =143, DQ7 =131
8567 17:16:41.681095 DQ8 =115, DQ9 =119, DQ10 =131, DQ11 =127
8568 17:16:41.684201 DQ12 =139, DQ13 =143, DQ14 =139, DQ15 =139
8569 17:16:41.687498
8570 17:16:41.687578
8571 17:16:41.687644
8572 17:16:41.687708 ==
8573 17:16:41.690693 Dram Type= 6, Freq= 0, CH_1, rank 0
8574 17:16:41.694064 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8575 17:16:41.694149 ==
8576 17:16:41.694229
8577 17:16:41.694340
8578 17:16:41.697312 TX Vref Scan disable
8579 17:16:41.697390 == TX Byte 0 ==
8580 17:16:41.704297 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8581 17:16:41.707428 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8582 17:16:41.707506 == TX Byte 1 ==
8583 17:16:41.713702 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8584 17:16:41.716969 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8585 17:16:41.717082 ==
8586 17:16:41.720686 Dram Type= 6, Freq= 0, CH_1, rank 0
8587 17:16:41.724025 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8588 17:16:41.724105 ==
8589 17:16:41.738010
8590 17:16:41.741254 TX Vref early break, caculate TX vref
8591 17:16:41.744433 TX Vref=16, minBit 9, minWin=21, winSum=367
8592 17:16:41.747581 TX Vref=18, minBit 8, minWin=22, winSum=377
8593 17:16:41.750844 TX Vref=20, minBit 8, minWin=23, winSum=388
8594 17:16:41.754397 TX Vref=22, minBit 8, minWin=23, winSum=396
8595 17:16:41.757440 TX Vref=24, minBit 8, minWin=24, winSum=404
8596 17:16:41.763873 TX Vref=26, minBit 6, minWin=25, winSum=412
8597 17:16:41.767084 TX Vref=28, minBit 8, minWin=25, winSum=419
8598 17:16:41.770306 TX Vref=30, minBit 0, minWin=25, winSum=414
8599 17:16:41.773483 TX Vref=32, minBit 0, minWin=24, winSum=405
8600 17:16:41.777371 TX Vref=34, minBit 9, minWin=23, winSum=396
8601 17:16:41.783721 [TxChooseVref] Worse bit 8, Min win 25, Win sum 419, Final Vref 28
8602 17:16:41.783803
8603 17:16:41.787236 Final TX Range 0 Vref 28
8604 17:16:41.787317
8605 17:16:41.787386 ==
8606 17:16:41.790222 Dram Type= 6, Freq= 0, CH_1, rank 0
8607 17:16:41.793550 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8608 17:16:41.793642 ==
8609 17:16:41.793710
8610 17:16:41.793777
8611 17:16:41.796836
8612 17:16:41.796919 TX Vref Scan disable
8613 17:16:41.803320 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
8614 17:16:41.803401 == TX Byte 0 ==
8615 17:16:41.806411 u2DelayCellOfst[0]=17 cells (5 PI)
8616 17:16:41.810108 u2DelayCellOfst[1]=10 cells (3 PI)
8617 17:16:41.813184 u2DelayCellOfst[2]=0 cells (0 PI)
8618 17:16:41.816337 u2DelayCellOfst[3]=7 cells (2 PI)
8619 17:16:41.819396 u2DelayCellOfst[4]=10 cells (3 PI)
8620 17:16:41.823082 u2DelayCellOfst[5]=17 cells (5 PI)
8621 17:16:41.826155 u2DelayCellOfst[6]=17 cells (5 PI)
8622 17:16:41.829504 u2DelayCellOfst[7]=7 cells (2 PI)
8623 17:16:41.832615 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
8624 17:16:41.835888 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
8625 17:16:41.839317 == TX Byte 1 ==
8626 17:16:41.842464 u2DelayCellOfst[8]=0 cells (0 PI)
8627 17:16:41.845909 u2DelayCellOfst[9]=7 cells (2 PI)
8628 17:16:41.849051 u2DelayCellOfst[10]=14 cells (4 PI)
8629 17:16:41.852391 u2DelayCellOfst[11]=7 cells (2 PI)
8630 17:16:41.855516 u2DelayCellOfst[12]=14 cells (4 PI)
8631 17:16:41.858867 u2DelayCellOfst[13]=14 cells (4 PI)
8632 17:16:41.862011 u2DelayCellOfst[14]=17 cells (5 PI)
8633 17:16:41.865346 u2DelayCellOfst[15]=17 cells (5 PI)
8634 17:16:41.869142 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
8635 17:16:41.871777 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8636 17:16:41.875117 DramC Write-DBI on
8637 17:16:41.875200 ==
8638 17:16:41.878374 Dram Type= 6, Freq= 0, CH_1, rank 0
8639 17:16:41.881608 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8640 17:16:41.881701 ==
8641 17:16:41.881767
8642 17:16:41.881828
8643 17:16:41.885302 TX Vref Scan disable
8644 17:16:41.888741 == TX Byte 0 ==
8645 17:16:41.891994 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
8646 17:16:41.892079 == TX Byte 1 ==
8647 17:16:41.898376 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
8648 17:16:41.898460 DramC Write-DBI off
8649 17:16:41.898525
8650 17:16:41.898586 [DATLAT]
8651 17:16:41.901626 Freq=1600, CH1 RK0
8652 17:16:41.901711
8653 17:16:41.904711 DATLAT Default: 0xf
8654 17:16:41.904794 0, 0xFFFF, sum = 0
8655 17:16:41.907939 1, 0xFFFF, sum = 0
8656 17:16:41.908040 2, 0xFFFF, sum = 0
8657 17:16:41.911672 3, 0xFFFF, sum = 0
8658 17:16:41.911761 4, 0xFFFF, sum = 0
8659 17:16:41.914825 5, 0xFFFF, sum = 0
8660 17:16:41.914935 6, 0xFFFF, sum = 0
8661 17:16:41.917865 7, 0xFFFF, sum = 0
8662 17:16:41.917951 8, 0xFFFF, sum = 0
8663 17:16:41.921805 9, 0xFFFF, sum = 0
8664 17:16:41.921890 10, 0xFFFF, sum = 0
8665 17:16:41.924342 11, 0xFFFF, sum = 0
8666 17:16:41.924474 12, 0xFFFF, sum = 0
8667 17:16:41.928013 13, 0xFFFF, sum = 0
8668 17:16:41.928097 14, 0x0, sum = 1
8669 17:16:41.931192
8670 17:16:41.931274 15, 0x0, sum = 2
8671 17:16:41.931341 16, 0x0, sum = 3
8672 17:16:41.934202 17, 0x0, sum = 4
8673 17:16:41.934283 best_step = 15
8674 17:16:41.934347
8675 17:16:41.934407 ==
8676 17:16:41.937500
8677 17:16:41.937610 Dram Type= 6, Freq= 0, CH_1, rank 0
8678 17:16:41.944126 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8679 17:16:41.944207 ==
8680 17:16:41.944274 RX Vref Scan: 1
8681 17:16:41.944339
8682 17:16:41.947414 Set Vref Range= 24 -> 127
8683 17:16:41.947491
8684 17:16:41.950502 RX Vref 24 -> 127, step: 1
8685 17:16:41.950578
8686 17:16:41.954391 RX Delay 19 -> 252, step: 4
8687 17:16:41.954468
8688 17:16:41.957124 Set Vref, RX VrefLevel [Byte0]: 24
8689 17:16:41.960851 [Byte1]: 24
8690 17:16:41.960935
8691 17:16:41.964031 Set Vref, RX VrefLevel [Byte0]: 25
8692 17:16:41.967355 [Byte1]: 25
8693 17:16:41.967434
8694 17:16:41.970693 Set Vref, RX VrefLevel [Byte0]: 26
8695 17:16:41.973853 [Byte1]: 26
8696 17:16:41.977318
8697 17:16:41.977399 Set Vref, RX VrefLevel [Byte0]: 27
8698 17:16:41.980647 [Byte1]: 27
8699 17:16:41.984643
8700 17:16:41.984720 Set Vref, RX VrefLevel [Byte0]: 28
8701 17:16:41.987934 [Byte1]: 28
8702 17:16:41.992449
8703 17:16:41.992526 Set Vref, RX VrefLevel [Byte0]: 29
8704 17:16:41.995822 [Byte1]: 29
8705 17:16:41.999761
8706 17:16:41.999841 Set Vref, RX VrefLevel [Byte0]: 30
8707 17:16:42.003595 [Byte1]: 30
8708 17:16:42.007360
8709 17:16:42.007455 Set Vref, RX VrefLevel [Byte0]: 31
8710 17:16:42.011108 [Byte1]: 31
8711 17:16:42.015412
8712 17:16:42.015492 Set Vref, RX VrefLevel [Byte0]: 32
8713 17:16:42.018416 [Byte1]: 32
8714 17:16:42.022668
8715 17:16:42.022748 Set Vref, RX VrefLevel [Byte0]: 33
8716 17:16:42.025917 [Byte1]: 33
8717 17:16:42.030403
8718 17:16:42.030482 Set Vref, RX VrefLevel [Byte0]: 34
8719 17:16:42.033500 [Byte1]: 34
8720 17:16:42.038083
8721 17:16:42.038163 Set Vref, RX VrefLevel [Byte0]: 35
8722 17:16:42.041290 [Byte1]: 35
8723 17:16:42.045171
8724 17:16:42.045261 Set Vref, RX VrefLevel [Byte0]: 36
8725 17:16:42.048372 [Byte1]: 36
8726 17:16:42.052882
8727 17:16:42.052976 Set Vref, RX VrefLevel [Byte0]: 37
8728 17:16:42.056167 [Byte1]: 37
8729 17:16:42.060665
8730 17:16:42.060755 Set Vref, RX VrefLevel [Byte0]: 38
8731 17:16:42.063910 [Byte1]: 38
8732 17:16:42.068458
8733 17:16:42.068537 Set Vref, RX VrefLevel [Byte0]: 39
8734 17:16:42.071726 [Byte1]: 39
8735 17:16:42.075440
8736 17:16:42.075533 Set Vref, RX VrefLevel [Byte0]: 40
8737 17:16:42.078665 [Byte1]: 40
8738 17:16:42.083303
8739 17:16:42.083396 Set Vref, RX VrefLevel [Byte0]: 41
8740 17:16:42.086570 [Byte1]: 41
8741 17:16:42.091044
8742 17:16:42.091123 Set Vref, RX VrefLevel [Byte0]: 42
8743 17:16:42.094262 [Byte1]: 42
8744 17:16:42.098188
8745 17:16:42.098267 Set Vref, RX VrefLevel [Byte0]: 43
8746 17:16:42.102091 [Byte1]: 43
8747 17:16:42.105977
8748 17:16:42.106056 Set Vref, RX VrefLevel [Byte0]: 44
8749 17:16:42.109116 [Byte1]: 44
8750 17:16:42.113620
8751 17:16:42.113704 Set Vref, RX VrefLevel [Byte0]: 45
8752 17:16:42.116697 [Byte1]: 45
8753 17:16:42.121243
8754 17:16:42.121334 Set Vref, RX VrefLevel [Byte0]: 46
8755 17:16:42.124290 [Byte1]: 46
8756 17:16:42.128667
8757 17:16:42.128746 Set Vref, RX VrefLevel [Byte0]: 47
8758 17:16:42.131958 [Byte1]: 47
8759 17:16:42.136157
8760 17:16:42.136235 Set Vref, RX VrefLevel [Byte0]: 48
8761 17:16:42.139423 [Byte1]: 48
8762 17:16:42.143934
8763 17:16:42.144013 Set Vref, RX VrefLevel [Byte0]: 49
8764 17:16:42.147103 [Byte1]: 49
8765 17:16:42.151495
8766 17:16:42.151571 Set Vref, RX VrefLevel [Byte0]: 50
8767 17:16:42.154701 [Byte1]: 50
8768 17:16:42.158704
8769 17:16:42.158780 Set Vref, RX VrefLevel [Byte0]: 51
8770 17:16:42.162596 [Byte1]: 51
8771 17:16:42.166607
8772 17:16:42.166684 Set Vref, RX VrefLevel [Byte0]: 52
8773 17:16:42.169918 [Byte1]: 52
8774 17:16:42.174328
8775 17:16:42.174413 Set Vref, RX VrefLevel [Byte0]: 53
8776 17:16:42.177542 [Byte1]: 53
8777 17:16:42.181399
8778 17:16:42.181478 Set Vref, RX VrefLevel [Byte0]: 54
8779 17:16:42.184865 [Byte1]: 54
8780 17:16:42.189224
8781 17:16:42.189324 Set Vref, RX VrefLevel [Byte0]: 55
8782 17:16:42.192511
8783 17:16:42.192588 [Byte1]: 55
8784 17:16:42.197047
8785 17:16:42.197126 Set Vref, RX VrefLevel [Byte0]: 56
8786 17:16:42.200336 [Byte1]: 56
8787 17:16:42.204427
8788 17:16:42.204523 Set Vref, RX VrefLevel [Byte0]: 57
8789 17:16:42.207568 [Byte1]: 57
8790 17:16:42.211974
8791 17:16:42.212064 Set Vref, RX VrefLevel [Byte0]: 58
8792 17:16:42.215128 [Byte1]: 58
8793 17:16:42.219404
8794 17:16:42.219519 Set Vref, RX VrefLevel [Byte0]: 59
8795 17:16:42.222515 [Byte1]: 59
8796 17:16:42.227128
8797 17:16:42.227213 Set Vref, RX VrefLevel [Byte0]: 60
8798 17:16:42.230299 [Byte1]: 60
8799 17:16:42.234750
8800 17:16:42.234837 Set Vref, RX VrefLevel [Byte0]: 61
8801 17:16:42.237797 [Byte1]: 61
8802 17:16:42.242129
8803 17:16:42.242221 Set Vref, RX VrefLevel [Byte0]: 62
8804 17:16:42.246094 [Byte1]: 62
8805 17:16:42.249926
8806 17:16:42.250011 Set Vref, RX VrefLevel [Byte0]: 63
8807 17:16:42.253271 [Byte1]: 63
8808 17:16:42.257604
8809 17:16:42.257688 Set Vref, RX VrefLevel [Byte0]: 64
8810 17:16:42.260749 [Byte1]: 64
8811 17:16:42.265220
8812 17:16:42.265342 Set Vref, RX VrefLevel [Byte0]: 65
8813 17:16:42.268597 [Byte1]: 65
8814 17:16:42.272427
8815 17:16:42.272512 Set Vref, RX VrefLevel [Byte0]: 66
8816 17:16:42.276246 [Byte1]: 66
8817 17:16:42.280185
8818 17:16:42.280269 Set Vref, RX VrefLevel [Byte0]: 67
8819 17:16:42.283461 [Byte1]: 67
8820 17:16:42.287405
8821 17:16:42.291212 Set Vref, RX VrefLevel [Byte0]: 68
8822 17:16:42.294313 [Byte1]: 68
8823 17:16:42.294396
8824 17:16:42.297691 Set Vref, RX VrefLevel [Byte0]: 69
8825 17:16:42.300409 [Byte1]: 69
8826 17:16:42.300487
8827 17:16:42.304174 Final RX Vref Byte 0 = 56 to rank0
8828 17:16:42.307338 Final RX Vref Byte 1 = 60 to rank0
8829 17:16:42.310567 Final RX Vref Byte 0 = 56 to rank1
8830 17:16:42.314196 Final RX Vref Byte 1 = 60 to rank1==
8831 17:16:42.317251 Dram Type= 6, Freq= 0, CH_1, rank 0
8832 17:16:42.320422 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8833 17:16:42.320508 ==
8834 17:16:42.323445 DQS Delay:
8835 17:16:42.323565 DQS0 = 0, DQS1 = 0
8836 17:16:42.327230 DQM Delay:
8837 17:16:42.327354 DQM0 = 133, DQM1 = 130
8838 17:16:42.327445 DQ Delay:
8839 17:16:42.330407 DQ0 =142, DQ1 =130, DQ2 =118, DQ3 =132
8840 17:16:42.333458
8841 17:16:42.336663 DQ4 =130, DQ5 =142, DQ6 =146, DQ7 =126
8842 17:16:42.340354 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =122
8843 17:16:42.343506 DQ12 =142, DQ13 =140, DQ14 =136, DQ15 =138
8844 17:16:42.343620
8845 17:16:42.343690
8846 17:16:42.343755
8847 17:16:42.346680 [DramC_TX_OE_Calibration] TA2
8848 17:16:42.349899 Original DQ_B0 (3 6) =30, OEN = 27
8849 17:16:42.353248 Original DQ_B1 (3 6) =30, OEN = 27
8850 17:16:42.353326 24, 0x0, End_B0=24 End_B1=24
8851 17:16:42.356487
8852 17:16:42.356561 25, 0x0, End_B0=25 End_B1=25
8853 17:16:42.359634 26, 0x0, End_B0=26 End_B1=26
8854 17:16:42.362826 27, 0x0, End_B0=27 End_B1=27
8855 17:16:42.365973 28, 0x0, End_B0=28 End_B1=28
8856 17:16:42.366082 29, 0x0, End_B0=29 End_B1=29
8857 17:16:42.369877 30, 0x0, End_B0=30 End_B1=30
8858 17:16:42.372806 31, 0x4141, End_B0=30 End_B1=30
8859 17:16:42.376303 Byte0 end_step=30 best_step=27
8860 17:16:42.379362 Byte1 end_step=30 best_step=27
8861 17:16:42.382663 Byte0 TX OE(2T, 0.5T) = (3, 3)
8862 17:16:42.382739 Byte1 TX OE(2T, 0.5T) = (3, 3)
8863 17:16:42.385862
8864 17:16:42.385936
8865 17:16:42.392576 [DQSOSCAuto] RK0, (LSB)MR18= 0xa14, (MSB)MR19= 0x303, tDQSOscB0 = 399 ps tDQSOscB1 = 404 ps
8866 17:16:42.395963 CH1 RK0: MR19=303, MR18=A14
8867 17:16:42.402436 CH1_RK0: MR19=0x303, MR18=0xA14, DQSOSC=399, MR23=63, INC=23, DEC=15
8868 17:16:42.402516
8869 17:16:42.405808 ----->DramcWriteLeveling(PI) begin...
8870 17:16:42.405885 ==
8871 17:16:42.409083 Dram Type= 6, Freq= 0, CH_1, rank 1
8872 17:16:42.412221 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8873 17:16:42.412312 ==
8874 17:16:42.415394 Write leveling (Byte 0): 23 => 23
8875 17:16:42.418578 Write leveling (Byte 1): 27 => 27
8876 17:16:42.422317 DramcWriteLeveling(PI) end<-----
8877 17:16:42.422393
8878 17:16:42.422459 ==
8879 17:16:42.425363 Dram Type= 6, Freq= 0, CH_1, rank 1
8880 17:16:42.429110 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8881 17:16:42.429190 ==
8882 17:16:42.432399 [Gating] SW mode calibration
8883 17:16:42.438636 [GatingStartPos] MR0_LatencyMode 1, u1RealRL 32 , u4TDQSCK_UI_min 4, 1:4ExtraMCK 0
8884 17:16:42.445092 RX_Path_delay_UI(60) -3 - DQSINCTL_UI(40) = u1StartUI(20)
8885 17:16:42.448397 1 4 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8886 17:16:42.455385 1 4 4 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8887 17:16:42.458519 1 4 8 | B1->B0 | 2323 3434 | 0 0 | (0 0) (0 0)
8888 17:16:42.461595 1 4 12 | B1->B0 | 2d2d 3434 | 0 1 | (0 0) (1 1)
8889 17:16:42.468118 1 4 16 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8890 17:16:42.471435 1 4 20 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8891 17:16:42.474569 1 4 24 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8892 17:16:42.481097 1 4 28 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8893 17:16:42.484611 1 5 0 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 1)
8894 17:16:42.487550 1 5 4 | B1->B0 | 3434 3434 | 1 1 | (1 1) (1 0)
8895 17:16:42.494308 1 5 8 | B1->B0 | 3434 2424 | 1 0 | (1 1) (1 0)
8896 17:16:42.497491 1 5 12 | B1->B0 | 3333 2323 | 1 0 | (1 0) (0 0)
8897 17:16:42.500732 1 5 16 | B1->B0 | 2525 2323 | 1 0 | (1 0) (0 0)
8898 17:16:42.507287 1 5 20 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8899 17:16:42.510732 1 5 24 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8900 17:16:42.513933 1 5 28 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8901 17:16:42.520364 1 6 0 | B1->B0 | 2323 2323 | 0 0 | (0 0) (0 0)
8902 17:16:42.523494 1 6 4 | B1->B0 | 2323 2525 | 0 0 | (0 0) (1 1)
8903 17:16:42.527252 1 6 8 | B1->B0 | 2323 4646 | 0 0 | (0 0) (0 0)
8904 17:16:42.533474 1 6 12 | B1->B0 | 3131 4646 | 1 0 | (0 0) (0 0)
8905 17:16:42.536920 1 6 16 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8906 17:16:42.540120 1 6 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8907 17:16:42.546901 1 6 24 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8908 17:16:42.550406 1 6 28 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8909 17:16:42.553484 1 7 0 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8910 17:16:42.559989 1 7 4 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8911 17:16:42.563170 1 7 8 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 1)
8912 17:16:42.566267 1 7 12 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8913 17:16:42.572744 1 7 16 | B1->B0 | 4646 4646 | 0 0 | (0 1) (1 1)
8914 17:16:42.575944 1 7 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8915 17:16:42.579272 1 7 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8916 17:16:42.585826 1 7 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8917 17:16:42.589517 1 8 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8918 17:16:42.592894 1 8 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8919 17:16:42.599487 1 8 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8920 17:16:42.602552 1 8 12 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8921 17:16:42.605946 1 8 16 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8922 17:16:42.612560 1 8 20 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8923 17:16:42.615710 1 8 24 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8924 17:16:42.618972 1 8 28 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8925 17:16:42.625430 1 9 0 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8926 17:16:42.629076 1 9 4 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 1)
8927 17:16:42.632122 1 9 8 | B1->B0 | 4646 4646 | 0 0 | (1 1) (1 0)
8928 17:16:42.635037
8929 17:16:42.638306 1 9 12 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8930 17:16:42.642257 Total UI for P1: 0, mck2ui 16
8931 17:16:42.644867 best dqsien dly found for B0: ( 1, 9, 8)
8932 17:16:42.648137 1 9 16 | B1->B0 | 4646 4646 | 0 0 | (1 0) (0 0)
8933 17:16:42.651819 1 9 20 | B1->B0 | 4646 4646 | 0 0 | (0 0) (0 0)
8934 17:16:42.655185
8935 17:16:42.655279 Total UI for P1: 0, mck2ui 16
8936 17:16:42.658467 best dqsien dly found for B1: ( 1, 9, 14)
8937 17:16:42.664849 best DQS0 dly(MCK, UI, PI) = (1, 9, 8)
8938 17:16:42.667989 best DQS1 dly(MCK, UI, PI) = (1, 9, 14)
8939 17:16:42.668078
8940 17:16:42.671212 best DQS0 P1 dly(MCK, UI, PI) = (1, 13, 8)
8941 17:16:42.674440 best DQS1 P1 dly(MCK, UI, PI) = (1, 13, 14)
8942 17:16:42.678436 [Gating] SW calibration Done
8943 17:16:42.678521 ==
8944 17:16:42.681421 Dram Type= 6, Freq= 0, CH_1, rank 1
8945 17:16:42.684733 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8946 17:16:42.684830 ==
8947 17:16:42.688016 RX Vref Scan: 0
8948 17:16:42.688100
8949 17:16:42.688167 RX Vref 0 -> 0, step: 1
8950 17:16:42.688230
8951 17:16:42.691192 RX Delay 0 -> 252, step: 8
8952 17:16:42.694287 iDelay=200, Bit 0, Center 143 (88 ~ 199) 112
8953 17:16:42.700980 iDelay=200, Bit 1, Center 135 (80 ~ 191) 112
8954 17:16:42.703995 iDelay=200, Bit 2, Center 123 (64 ~ 183) 120
8955 17:16:42.707403 iDelay=200, Bit 3, Center 135 (80 ~ 191) 112
8956 17:16:42.710673 iDelay=200, Bit 4, Center 135 (80 ~ 191) 112
8957 17:16:42.713864 iDelay=200, Bit 5, Center 147 (96 ~ 199) 104
8958 17:16:42.720434 iDelay=200, Bit 6, Center 143 (88 ~ 199) 112
8959 17:16:42.723700 iDelay=200, Bit 7, Center 135 (80 ~ 191) 112
8960 17:16:42.726868 iDelay=200, Bit 8, Center 119 (64 ~ 175) 112
8961 17:16:42.730665 iDelay=200, Bit 9, Center 115 (56 ~ 175) 120
8962 17:16:42.733631 iDelay=200, Bit 10, Center 131 (72 ~ 191) 120
8963 17:16:42.737243
8964 17:16:42.740306 iDelay=200, Bit 11, Center 127 (72 ~ 183) 112
8965 17:16:42.743709 iDelay=200, Bit 12, Center 139 (80 ~ 199) 120
8966 17:16:42.746765 iDelay=200, Bit 13, Center 139 (80 ~ 199) 120
8967 17:16:42.749901 iDelay=200, Bit 14, Center 135 (80 ~ 191) 112
8968 17:16:42.757068 iDelay=200, Bit 15, Center 139 (80 ~ 199) 120
8969 17:16:42.757156 ==
8970 17:16:42.759729 Dram Type= 6, Freq= 0, CH_1, rank 1
8971 17:16:42.763428 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8972 17:16:42.763512 ==
8973 17:16:42.763577 DQS Delay:
8974 17:16:42.766589 DQS0 = 0, DQS1 = 0
8975 17:16:42.766734 DQM Delay:
8976 17:16:42.769675 DQM0 = 137, DQM1 = 130
8977 17:16:42.769758 DQ Delay:
8978 17:16:42.773072 DQ0 =143, DQ1 =135, DQ2 =123, DQ3 =135
8979 17:16:42.776052 DQ4 =135, DQ5 =147, DQ6 =143, DQ7 =135
8980 17:16:42.779478 DQ8 =119, DQ9 =115, DQ10 =131, DQ11 =127
8981 17:16:42.786349 DQ12 =139, DQ13 =139, DQ14 =135, DQ15 =139
8982 17:16:42.786447
8983 17:16:42.786513
8984 17:16:42.786587 ==
8985 17:16:42.789119 Dram Type= 6, Freq= 0, CH_1, rank 1
8986 17:16:42.792806 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
8987 17:16:42.792890 ==
8988 17:16:42.793010
8989 17:16:42.793101
8990 17:16:42.796132 TX Vref Scan disable
8991 17:16:42.796258 == TX Byte 0 ==
8992 17:16:42.802566 Update DQ dly =979 (3 ,6, 19) DQ OEN =(3 ,3)
8993 17:16:42.805770 Update DQM dly =979 (3 ,6, 19) DQM OEN =(3 ,3)
8994 17:16:42.805868 == TX Byte 1 ==
8995 17:16:42.812423 Update DQ dly =982 (3 ,6, 22) DQ OEN =(3 ,3)
8996 17:16:42.815547 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
8997 17:16:42.815633 ==
8998 17:16:42.818797 Dram Type= 6, Freq= 0, CH_1, rank 1
8999 17:16:42.822037 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9000 17:16:42.822173 ==
9001 17:16:42.837883
9002 17:16:42.841060 TX Vref early break, caculate TX vref
9003 17:16:42.844401 TX Vref=16, minBit 9, minWin=22, winSum=378
9004 17:16:42.847610 TX Vref=18, minBit 9, minWin=22, winSum=384
9005 17:16:42.850814 TX Vref=20, minBit 9, minWin=22, winSum=393
9006 17:16:42.854055 TX Vref=22, minBit 9, minWin=22, winSum=398
9007 17:16:42.857330 TX Vref=24, minBit 9, minWin=23, winSum=407
9008 17:16:42.864463 TX Vref=26, minBit 9, minWin=25, winSum=415
9009 17:16:42.866999 TX Vref=28, minBit 9, minWin=25, winSum=422
9010 17:16:42.870846 TX Vref=30, minBit 9, minWin=25, winSum=416
9011 17:16:42.874065 TX Vref=32, minBit 8, minWin=24, winSum=408
9012 17:16:42.877287 TX Vref=34, minBit 0, minWin=24, winSum=400
9013 17:16:42.883861 TX Vref=36, minBit 9, minWin=23, winSum=399
9014 17:16:42.886950 [TxChooseVref] Worse bit 9, Min win 25, Win sum 422, Final Vref 28
9015 17:16:42.887036
9016 17:16:42.890387 Final TX Range 0 Vref 28
9017 17:16:42.890472
9018 17:16:42.890540 ==
9019 17:16:42.893497 Dram Type= 6, Freq= 0, CH_1, rank 1
9020 17:16:42.897022 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9021 17:16:42.900296
9022 17:16:42.900394 ==
9023 17:16:42.900461
9024 17:16:42.900525
9025 17:16:42.900585 TX Vref Scan disable
9026 17:16:42.907187 [TX_PER_BIT_DELAY_CELL] DelayCellTimex100 =275/100 ps
9027 17:16:42.907273 == TX Byte 0 ==
9028 17:16:42.910495 u2DelayCellOfst[0]=10 cells (3 PI)
9029 17:16:42.913669 u2DelayCellOfst[1]=7 cells (2 PI)
9030 17:16:42.917054 u2DelayCellOfst[2]=0 cells (0 PI)
9031 17:16:42.920124 u2DelayCellOfst[3]=3 cells (1 PI)
9032 17:16:42.923424 u2DelayCellOfst[4]=3 cells (1 PI)
9033 17:16:42.926689 u2DelayCellOfst[5]=14 cells (4 PI)
9034 17:16:42.930025 u2DelayCellOfst[6]=10 cells (3 PI)
9035 17:16:42.933096 u2DelayCellOfst[7]=3 cells (1 PI)
9036 17:16:42.936750 Update DQ dly =978 (3 ,6, 18) DQ OEN =(3 ,3)
9037 17:16:42.939829 Update DQM dly =980 (3 ,6, 20) DQM OEN =(3 ,3)
9038 17:16:42.942908 == TX Byte 1 ==
9039 17:16:42.946207 u2DelayCellOfst[8]=0 cells (0 PI)
9040 17:16:42.949380 u2DelayCellOfst[9]=3 cells (1 PI)
9041 17:16:42.952536 u2DelayCellOfst[10]=10 cells (3 PI)
9042 17:16:42.956154 u2DelayCellOfst[11]=3 cells (1 PI)
9043 17:16:42.959505 u2DelayCellOfst[12]=14 cells (4 PI)
9044 17:16:42.962612 u2DelayCellOfst[13]=14 cells (4 PI)
9045 17:16:42.965895 u2DelayCellOfst[14]=17 cells (5 PI)
9046 17:16:42.969695 u2DelayCellOfst[15]=17 cells (5 PI)
9047 17:16:42.972935 Update DQ dly =980 (3 ,6, 20) DQ OEN =(3 ,3)
9048 17:16:42.976007 Update DQM dly =982 (3 ,6, 22) DQM OEN =(3 ,3)
9049 17:16:42.979433 DramC Write-DBI on
9050 17:16:42.979514 ==
9051 17:16:42.982440 Dram Type= 6, Freq= 0, CH_1, rank 1
9052 17:16:42.985741 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9053 17:16:42.985831 ==
9054 17:16:42.985897
9055 17:16:42.985958
9056 17:16:42.988891 TX Vref Scan disable
9057 17:16:42.988967 == TX Byte 0 ==
9058 17:16:42.995544 Update DQM dly =722 (2 ,6, 18) DQM OEN =(3 ,3)
9059 17:16:42.995645 == TX Byte 1 ==
9060 17:16:43.002187 Update DQM dly =724 (2 ,6, 20) DQM OEN =(3 ,3)
9061 17:16:43.002296 DramC Write-DBI off
9062 17:16:43.002396
9063 17:16:43.002459 [DATLAT]
9064 17:16:43.005407 Freq=1600, CH1 RK1
9065 17:16:43.005499
9066 17:16:43.008691 DATLAT Default: 0xf
9067 17:16:43.008783 0, 0xFFFF, sum = 0
9068 17:16:43.011866 1, 0xFFFF, sum = 0
9069 17:16:43.011963 2, 0xFFFF, sum = 0
9070 17:16:43.015234 3, 0xFFFF, sum = 0
9071 17:16:43.015316 4, 0xFFFF, sum = 0
9072 17:16:43.018562 5, 0xFFFF, sum = 0
9073 17:16:43.018654 6, 0xFFFF, sum = 0
9074 17:16:43.021717 7, 0xFFFF, sum = 0
9075 17:16:43.021814 8, 0xFFFF, sum = 0
9076 17:16:43.024837 9, 0xFFFF, sum = 0
9077 17:16:43.024928 10, 0xFFFF, sum = 0
9078 17:16:43.028057 11, 0xFFFF, sum = 0
9079 17:16:43.028149 12, 0xFFFF, sum = 0
9080 17:16:43.031285 13, 0xFFFF, sum = 0
9081 17:16:43.031366 14, 0x0, sum = 1
9082 17:16:43.034865 15, 0x0, sum = 2
9083 17:16:43.034968 16, 0x0, sum = 3
9084 17:16:43.038181 17, 0x0, sum = 4
9085 17:16:43.038259 best_step = 15
9086 17:16:43.038331
9087 17:16:43.038392 ==
9088 17:16:43.041174 Dram Type= 6, Freq= 0, CH_1, rank 1
9089 17:16:43.048074 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9090 17:16:43.048177 ==
9091 17:16:43.048257 RX Vref Scan: 0
9092 17:16:43.048319
9093 17:16:43.051207 RX Vref 0 -> 0, step: 1
9094 17:16:43.051284
9095 17:16:43.054368 RX Delay 11 -> 252, step: 4
9096 17:16:43.057367 iDelay=195, Bit 0, Center 136 (87 ~ 186) 100
9097 17:16:43.060834 iDelay=195, Bit 1, Center 132 (83 ~ 182) 100
9098 17:16:43.063951
9099 17:16:43.067825 iDelay=195, Bit 2, Center 122 (71 ~ 174) 104
9100 17:16:43.070386 iDelay=195, Bit 3, Center 130 (79 ~ 182) 104
9101 17:16:43.074072 iDelay=195, Bit 4, Center 132 (79 ~ 186) 108
9102 17:16:43.077185 iDelay=195, Bit 5, Center 142 (91 ~ 194) 104
9103 17:16:43.083579 iDelay=195, Bit 6, Center 142 (91 ~ 194) 104
9104 17:16:43.086797 iDelay=195, Bit 7, Center 130 (79 ~ 182) 104
9105 17:16:43.090117 iDelay=195, Bit 8, Center 116 (63 ~ 170) 108
9106 17:16:43.093380 iDelay=195, Bit 9, Center 118 (67 ~ 170) 104
9107 17:16:43.096575 iDelay=195, Bit 10, Center 130 (75 ~ 186) 112
9108 17:16:43.103205 iDelay=195, Bit 11, Center 120 (67 ~ 174) 108
9109 17:16:43.106505 iDelay=195, Bit 12, Center 136 (83 ~ 190) 108
9110 17:16:43.109707 iDelay=195, Bit 13, Center 136 (83 ~ 190) 108
9111 17:16:43.112899 iDelay=195, Bit 14, Center 132 (79 ~ 186) 108
9112 17:16:43.119905 iDelay=195, Bit 15, Center 136 (83 ~ 190) 108
9113 17:16:43.119986 ==
9114 17:16:43.123215 Dram Type= 6, Freq= 0, CH_1, rank 1
9115 17:16:43.126509 fsp= 1, odt_onoff= 1, Byte mode= 1, DivMode= 1
9116 17:16:43.126590 ==
9117 17:16:43.126657 DQS Delay:
9118 17:16:43.129616 DQS0 = 0, DQS1 = 0
9119 17:16:43.129701 DQM Delay:
9120 17:16:43.132885 DQM0 = 133, DQM1 = 128
9121 17:16:43.132964 DQ Delay:
9122 17:16:43.135981 DQ0 =136, DQ1 =132, DQ2 =122, DQ3 =130
9123 17:16:43.139868 DQ4 =132, DQ5 =142, DQ6 =142, DQ7 =130
9124 17:16:43.142841 DQ8 =116, DQ9 =118, DQ10 =130, DQ11 =120
9125 17:16:43.146096 DQ12 =136, DQ13 =136, DQ14 =132, DQ15 =136
9126 17:16:43.149314
9127 17:16:43.149391
9128 17:16:43.149470
9129 17:16:43.149533
9130 17:16:43.149593 [DramC_TX_OE_Calibration] TA2
9131 17:16:43.152370 Original DQ_B0 (3 6) =30, OEN = 27
9132 17:16:43.155536 Original DQ_B1 (3 6) =30, OEN = 27
9133 17:16:43.158788 24, 0x0, End_B0=24 End_B1=24
9134 17:16:43.162565 25, 0x0, End_B0=25 End_B1=25
9135 17:16:43.165894 26, 0x0, End_B0=26 End_B1=26
9136 17:16:43.169112 27, 0x0, End_B0=27 End_B1=27
9137 17:16:43.169199 28, 0x0, End_B0=28 End_B1=28
9138 17:16:43.172241 29, 0x0, End_B0=29 End_B1=29
9139 17:16:43.175518 30, 0x0, End_B0=30 End_B1=30
9140 17:16:43.178598 31, 0x4141, End_B0=30 End_B1=30
9141 17:16:43.181966 Byte0 end_step=30 best_step=27
9142 17:16:43.182052 Byte1 end_step=30 best_step=27
9143 17:16:43.185251
9144 17:16:43.185337 Byte0 TX OE(2T, 0.5T) = (3, 3)
9145 17:16:43.188372 Byte1 TX OE(2T, 0.5T) = (3, 3)
9146 17:16:43.188458
9147 17:16:43.188525
9148 17:16:43.198345 [DQSOSCAuto] RK1, (LSB)MR18= 0xd1a, (MSB)MR19= 0x303, tDQSOscB0 = 396 ps tDQSOscB1 = 403 ps
9149 17:16:43.198432 CH1 RK1: MR19=303, MR18=D1A
9150 17:16:43.201451
9151 17:16:43.205338 CH1_RK1: MR19=0x303, MR18=0xD1A, DQSOSC=396, MR23=63, INC=23, DEC=15
9152 17:16:43.208070 [RxdqsGatingPostProcess] freq 1600
9153 17:16:43.215066 ChangeDQSINCTL -1, reg_TX_dly_DQSgated_min 2, u1TXDLY_Cal_min 3
9154 17:16:43.218333 best DQS0 dly(2T, 0.5T) = (1, 1)
9155 17:16:43.221605 best DQS1 dly(2T, 0.5T) = (1, 1)
9156 17:16:43.224936 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9157 17:16:43.228303 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9158 17:16:43.231566 best DQS0 dly(2T, 0.5T) = (1, 1)
9159 17:16:43.231655 best DQS1 dly(2T, 0.5T) = (1, 1)
9160 17:16:43.234852
9161 17:16:43.234973 best DQS0 P1 dly(2T, 0.5T) = (1, 5)
9162 17:16:43.237773 best DQS1 P1 dly(2T, 0.5T) = (1, 5)
9163 17:16:43.240846 Pre-setting of DQS Precalculation
9164 17:16:43.247613 [DualRankRxdatlatCal] RK0: 15, RK1: 15, Final_Datlat 15
9165 17:16:43.253963 sync_frequency_calibration_params sync calibration params of frequency 1600 to shu:0
9166 17:16:43.260985 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9167 17:16:43.261070
9168 17:16:43.261137
9169 17:16:43.264301 [Calibration Summary] 3200 Mbps
9170 17:16:43.267562 CH 0, Rank 0
9171 17:16:43.267646 SW Impedance : PASS
9172 17:16:43.270841 DUTY Scan : NO K
9173 17:16:43.273951 ZQ Calibration : PASS
9174 17:16:43.274035 Jitter Meter : NO K
9175 17:16:43.277042 CBT Training : PASS
9176 17:16:43.280257 Write leveling : PASS
9177 17:16:43.280341 RX DQS gating : PASS
9178 17:16:43.283670 RX DQ/DQS(RDDQC) : PASS
9179 17:16:43.287001 TX DQ/DQS : PASS
9180 17:16:43.287085 RX DATLAT : PASS
9181 17:16:43.290086 RX DQ/DQS(Engine): PASS
9182 17:16:43.290169 TX OE : PASS
9183 17:16:43.293331
9184 17:16:43.293415 All Pass.
9185 17:16:43.293480
9186 17:16:43.293541 CH 0, Rank 1
9187 17:16:43.296600 SW Impedance : PASS
9188 17:16:43.299848 DUTY Scan : NO K
9189 17:16:43.299931 ZQ Calibration : PASS
9190 17:16:43.303201 Jitter Meter : NO K
9191 17:16:43.303284 CBT Training : PASS
9192 17:16:43.307012
9193 17:16:43.307096 Write leveling : PASS
9194 17:16:43.310342 RX DQS gating : PASS
9195 17:16:43.310426 RX DQ/DQS(RDDQC) : PASS
9196 17:16:43.313510 TX DQ/DQS : PASS
9197 17:16:43.316661 RX DATLAT : PASS
9198 17:16:43.316760 RX DQ/DQS(Engine): PASS
9199 17:16:43.320135 TX OE : PASS
9200 17:16:43.320219 All Pass.
9201 17:16:43.320286
9202 17:16:43.323202 CH 1, Rank 0
9203 17:16:43.323287 SW Impedance : PASS
9204 17:16:43.326457 DUTY Scan : NO K
9205 17:16:43.329659 ZQ Calibration : PASS
9206 17:16:43.329743 Jitter Meter : NO K
9207 17:16:43.332829 CBT Training : PASS
9208 17:16:43.336079 Write leveling : PASS
9209 17:16:43.336162 RX DQS gating : PASS
9210 17:16:43.339394 RX DQ/DQS(RDDQC) : PASS
9211 17:16:43.343035 TX DQ/DQS : PASS
9212 17:16:43.343120 RX DATLAT : PASS
9213 17:16:43.346321 RX DQ/DQS(Engine): PASS
9214 17:16:43.349457 TX OE : PASS
9215 17:16:43.349555 All Pass.
9216 17:16:43.349620
9217 17:16:43.349697 CH 1, Rank 1
9218 17:16:43.352555 SW Impedance : PASS
9219 17:16:43.355889 DUTY Scan : NO K
9220 17:16:43.355972 ZQ Calibration : PASS
9221 17:16:43.359568 Jitter Meter : NO K
9222 17:16:43.362664 CBT Training : PASS
9223 17:16:43.362770 Write leveling : PASS
9224 17:16:43.365985 RX DQS gating : PASS
9225 17:16:43.369212 RX DQ/DQS(RDDQC) : PASS
9226 17:16:43.369310 TX DQ/DQS : PASS
9227 17:16:43.372419 RX DATLAT : PASS
9228 17:16:43.375527 RX DQ/DQS(Engine): PASS
9229 17:16:43.375606 TX OE : PASS
9230 17:16:43.378791 All Pass.
9231 17:16:43.378869
9232 17:16:43.378975 DramC Write-DBI on
9233 17:16:43.382630 PER_BANK_REFRESH: Hybrid Mode
9234 17:16:43.382708 TX_TRACKING: ON
9235 17:16:43.392382 [ACTimingOptimize]Density (MR8 OP[5:2]) 4, TRFC 100, TRFC_05T 0, TXREFCNT 115, TRFCpb 44, TRFCpb_05T 0
9236 17:16:43.402249 sync_frequency_calibration_params_to_shu sync calibration params of frequency 1600 to shu:1
9237 17:16:43.408659 calibartion params size is 464, SAVE_TIME_FOR_CALIBRATION_T:464, sdram_params:464
9238 17:16:43.411955 [FAST_K] Save calibration result to emmc
9239 17:16:43.415143 sync common calibartion params.
9240 17:16:43.415227 sync cbt_mode0:1, 1:1
9241 17:16:43.418328 dram_init: ddr_geometry: 2
9242 17:16:43.421556 dram_init: ddr_geometry: 2
9243 17:16:43.421680 dram_init: ddr_geometry: 2
9244 17:16:43.425539
9245 17:16:43.425621 0:dram_rank_size:100000000
9246 17:16:43.428117 1:dram_rank_size:100000000
9247 17:16:43.435248 sync rank num:2, rank0_size:0x100000000, rank1_size:0x100000000
9248 17:16:43.435331 DFS_SHUFFLE_HW_MODE: ON
9249 17:16:43.438480 dramc_set_vcore_voltage set vcore to 725000
9250 17:16:43.441569
9251 17:16:43.441646 Read voltage for 1600, 0
9252 17:16:43.441712 Vio18 = 0
9253 17:16:43.444587 Vcore = 725000
9254 17:16:43.444667 Vdram = 0
9255 17:16:43.444731 Vddq = 0
9256 17:16:43.447824 Vmddr = 0
9257 17:16:43.447898 switch to 3200 Mbps bootup
9258 17:16:43.451170 [DramcRunTimeConfig]
9259 17:16:43.451245 PHYPLL
9260 17:16:43.454452 DPM_CONTROL_AFTERK: ON
9261 17:16:43.454528 PER_BANK_REFRESH: ON
9262 17:16:43.457625 REFRESH_OVERHEAD_REDUCTION: ON
9263 17:16:43.461389 CMD_PICG_NEW_MODE: OFF
9264 17:16:43.461464 XRTWTW_NEW_MODE: ON
9265 17:16:43.464401 XRTRTR_NEW_MODE: ON
9266 17:16:43.464476 TX_TRACKING: ON
9267 17:16:43.467713 RDSEL_TRACKING: OFF
9268 17:16:43.470975 DQS Precalculation for DVFS: ON
9269 17:16:43.471050 RX_TRACKING: OFF
9270 17:16:43.474168 HW_GATING DBG: ON
9271 17:16:43.474252 ZQCS_ENABLE_LP4: ON
9272 17:16:43.477530 RX_PICG_NEW_MODE: ON
9273 17:16:43.481254 TX_PICG_NEW_MODE: ON
9274 17:16:43.481334 ENABLE_RX_DCM_DPHY: ON
9275 17:16:43.484422 LOWPOWER_GOLDEN_SETTINGS(DCM): ON
9276 17:16:43.487639 DUMMY_READ_FOR_TRACKING: OFF
9277 17:16:43.490779 !!! SPM_CONTROL_AFTERK: OFF
9278 17:16:43.494072 !!! SPM could not control APHY
9279 17:16:43.494149 IMPEDANCE_TRACKING: ON
9280 17:16:43.497292 TEMP_SENSOR: ON
9281 17:16:43.497371 HW_SAVE_FOR_SR: OFF
9282 17:16:43.500518 CLK_FREE_FUN_FOR_DRAMC_PSEL: OFF
9283 17:16:43.503686 PA_IMPROVEMENT_FOR_DRAMC_ACTIVE_POWER: OFF
9284 17:16:43.506942 Read ODT Tracking: ON
9285 17:16:43.510344 Refresh Rate DeBounce: ON
9286 17:16:43.510420 DFS_NO_QUEUE_FLUSH: ON
9287 17:16:43.513479 DFS_NO_QUEUE_FLUSH_LATENCY_CNT: OFF
9288 17:16:43.516676 ENABLE_DFS_RUNTIME_MRW: OFF
9289 17:16:43.519849 DDR_RESERVE_NEW_MODE: ON
9290 17:16:43.519929 MR_CBT_SWITCH_FREQ: ON
9291 17:16:43.523677 =========================
9292 17:16:43.541890 [MEM] 1st complex R/W mem test pass (start addr:0x4c400000)
9293 17:16:43.544928 dram_init: ddr_geometry: 2
9294 17:16:43.563604 [MEM] 2nd complex R/W mem test pass (start addr:0x80000000, 0x0 @Rank1)
9295 17:16:43.566798 dram_init: dram init end (result: 0)
9296 17:16:43.573204 DRAM-K: Full calibration passed in 24416 msecs
9297 17:16:43.576476 MRC: failed to locate region type 0.
9298 17:16:43.576579 DRAM rank0 size:0x100000000,
9299 17:16:43.580301 DRAM rank1 size=0x100000000
9300 17:16:43.590106 Mapping address range [0x40000000:0x240000000) as cacheable | read-write | non-secure | normal
9301 17:16:43.596469 Mapping address range [0x40000000:0x40100000) as non-cacheable | read-write | non-secure | normal
9302 17:16:43.606310 Backing address range [0x40000000:0x80000000) with new page table @0x00112000
9303 17:16:43.612668 Backing address range [0x40000000:0x40200000) with new page table @0x00113000
9304 17:16:43.612752 DRAM rank0 size:0x100000000,
9305 17:16:43.616052 DRAM rank1 size=0x100000000
9306 17:16:43.616133 CBMEM:
9307 17:16:43.619336 IMD: root @ 0xfffff000 254 entries.
9308 17:16:43.622519 IMD: root @ 0xffffec00 62 entries.
9309 17:16:43.629124 FMAP: area RO_VPD found @ 3f8000 (32768 bytes)
9310 17:16:43.632320 WARNING: RO_VPD is uninitialized or empty.
9311 17:16:43.635727 FMAP: area RW_VPD found @ 577000 (16384 bytes)
9312 17:16:43.638826 WARNING: RW_VPD is uninitialized or empty.
9313 17:16:43.647184 CBFS: Found 'fallback/ramstage' @0x21840 size 0xe01e in mcache @0x00107c80
9314 17:16:43.660450 read SPI 0x42894 0xe01e: 6224 us, 9218 KB/s, 73.744 Mbps
9315 17:16:43.671480 BS: romstage times (exec / console): total (unknown) / 23954 ms
9316 17:16:43.671570
9317 17:16:43.671638
9318 17:16:43.681116 coreboot-v1.9308_26_0.0.22-20932-gb2c84cc22f Sat Sep 11 09:59:37 UTC 2021 ramstage starting (log level: 8)...
9319 17:16:43.684741 ARM64: Exception handlers installed.
9320 17:16:43.688084 ARM64: Testing exception
9321 17:16:43.691372 ARM64: Done test exception
9322 17:16:43.691449 Enumerating buses...
9323 17:16:43.694476 Show all devs... Before device enumeration.
9324 17:16:43.697511 Root Device: enabled 1
9325 17:16:43.700712 CPU_CLUSTER: 0: enabled 1
9326 17:16:43.700794 CPU: 00: enabled 1
9327 17:16:43.704661 Compare with tree...
9328 17:16:43.704738 Root Device: enabled 1
9329 17:16:43.707937 CPU_CLUSTER: 0: enabled 1
9330 17:16:43.710888 CPU: 00: enabled 1
9331 17:16:43.710968 Root Device scanning...
9332 17:16:43.714281 scan_static_bus for Root Device
9333 17:16:43.717685 CPU_CLUSTER: 0 enabled
9334 17:16:43.720981 scan_static_bus for Root Device done
9335 17:16:43.724193 scan_bus: bus Root Device finished in 8 msecs
9336 17:16:43.724269 done
9337 17:16:43.730563 BS: BS_DEV_ENUMERATE run times (exec / console): 0 / 35 ms
9338 17:16:43.733763 FMAP: area RW_MRC_CACHE found @ 57d000 (8192 bytes)
9339 17:16:43.740201 SF: Detected 00 0000 with sector size 0x1000, total 0x800000
9340 17:16:43.746651 BS: BS_DEV_ENUMERATE exit times (exec / console): 0 / 10 ms
9341 17:16:43.746729 Allocating resources...
9342 17:16:43.750310 Reading resources...
9343 17:16:43.753543 Root Device read_resources bus 0 link: 0
9344 17:16:43.756477 DRAM rank0 size:0x100000000,
9345 17:16:43.756562 DRAM rank1 size=0x100000000
9346 17:16:43.759712
9347 17:16:43.763074 CPU_CLUSTER: 0 read_resources bus 0 link: 0
9348 17:16:43.766832 CPU: 00 missing read_resources
9349 17:16:43.769961 CPU_CLUSTER: 0 read_resources bus 0 link: 0 done
9350 17:16:43.773261 Root Device read_resources bus 0 link: 0 done
9351 17:16:43.776581 Done reading resources.
9352 17:16:43.779902 Show resources in subtree (Root Device)...After reading.
9353 17:16:43.782889 Root Device child on link 0 CPU_CLUSTER: 0
9354 17:16:43.789878 CPU_CLUSTER: 0 child on link 0 CPU: 00
9355 17:16:43.796033 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9356 17:16:43.799210 CPU: 00
9357 17:16:43.803076 Root Device assign_resources, bus 0 link: 0
9358 17:16:43.805782 CPU_CLUSTER: 0 missing set_resources
9359 17:16:43.809617 Root Device assign_resources, bus 0 link: 0 done
9360 17:16:43.812668 Done setting resources.
9361 17:16:43.816088 Show resources in subtree (Root Device)...After assigning values.
9362 17:16:43.822608 Root Device child on link 0 CPU_CLUSTER: 0
9363 17:16:43.825626 CPU_CLUSTER: 0 child on link 0 CPU: 00
9364 17:16:43.832220 CPU_CLUSTER: 0 resource base 40000000 size 200000000 align 0 gran 0 limit 0 flags e0004200 index 0
9365 17:16:43.835309 CPU: 00
9366 17:16:43.835395 Done allocating resources.
9367 17:16:43.841754 BS: BS_DEV_RESOURCES run times (exec / console): 0 / 91 ms
9368 17:16:43.845160 Enabling resources...
9369 17:16:43.845256 done.
9370 17:16:43.848286 BS: BS_DEV_ENABLE run times (exec / console): 0 / 3 ms
9371 17:16:43.851427 Initializing devices...
9372 17:16:43.851506 Root Device init
9373 17:16:43.855173 init hardware done!
9374 17:16:43.858099 0x00000018: ctrlr->caps
9375 17:16:43.858179 52.000 MHz: ctrlr->f_max
9376 17:16:43.861995 0.400 MHz: ctrlr->f_min
9377 17:16:43.865198 0x40ff8080: ctrlr->voltages
9378 17:16:43.865294 sclk: 390625
9379 17:16:43.867789 Bus Width = 1
9380 17:16:43.867876 sclk: 390625
9381 17:16:43.867942 Bus Width = 1
9382 17:16:43.871556 Early init status = 3
9383 17:16:43.874731 out: cmd=0x12e: 03 c9 2e 01 00 00 04 00 01 00 00 00
9384 17:16:43.879216 in-header: 03 fb 00 00 01 00 00 00
9385 17:16:43.882878 in-data: 01
9386 17:16:43.885694 out: cmd=0x12e: 03 ca 2e 01 00 00 04 00 00 00 00 00
9387 17:16:43.890810 in-header: 03 fb 00 00 01 00 00 00
9388 17:16:43.894030 in-data: 01
9389 17:16:43.897327 [SSUSB] Setting up USB HOST controller...
9390 17:16:43.900348 [SSUSB] u3phy_ports_enable u2p:1, u3p:1
9391 17:16:43.904141 [SSUSB] phy power-on done.
9392 17:16:43.906900 FMAP: area COREBOOT found @ 21000 (4014080 bytes)
9393 17:16:43.913410 CBFS: Found 'dpm.dm' @0x2fe00 size 0x20 in mcache @0xffffc13c
9394 17:16:43.917296 mtk_init_mcu: Loaded (and reset) dpm.dm in 9 msecs (40 bytes)
9395 17:16:43.923208 CBFS: Found 'dpm.pm' @0x2fe80 size 0x2ad3 in mcache @0xffffc16c
9396 17:16:43.930195 read SPI 0x50eb0 0x2ad3: 1175 us, 9330 KB/s, 74.640 Mbps
9397 17:16:43.936518 mtk_init_mcu: Loaded (and reset) dpm.pm in 13 msecs (14004 bytes)
9398 17:16:43.943765 CBFS: Found 'spm_firmware.bin' @0x4f580 size 0x1f6a in mcache @0xffffc204
9399 17:16:43.950204 read SPI 0x705bc 0x1f6a: 924 us, 8703 KB/s, 69.624 Mbps
9400 17:16:43.953203 SPM: binary array size = 0x9dc
9401 17:16:43.959621 SPM: spmfw (version pcm_suspend_v1.45_20201028_mtcmosapi_align16)
9402 17:16:43.962716 spm_kick_im_to_fetch: ptr = 0x80000010, pmem/dmem words = 0x9c4/0x18
9403 17:16:43.972703 mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 27 msecs (10173 bytes)
9404 17:16:43.976486 SPM: spm_init done in 34 msecs, spm pc = 0x3f4
9405 17:16:43.979850 configure_display: Starting display init
9406 17:16:44.014760 anx7625_power_on_init: Init interface.
9407 17:16:44.017393 anx7625_disable_pd_protocol: Disabled PD feature.
9408 17:16:44.020743 anx7625_power_on_init: Firmware: ver 0x13, rev 0x0.
9409 17:16:44.048442 anx7625_start_dp_work: Secure OCM version=00
9410 17:16:44.052103 anx7625_hpd_change_detect: HPD received 0x7e:0x45=0x91
9411 17:16:44.066550 sp_tx_get_edid_block: EDID Block = 1
9412 17:16:44.169572 Extracted contents:
9413 17:16:44.172787 header: 00 ff ff ff ff ff ff 00
9414 17:16:44.175978 serial number: 26 cf 7d 05 00 00 00 00 00 1e
9415 17:16:44.179235 version: 01 04
9416 17:16:44.182379 basic params: 95 1f 11 78 0a
9417 17:16:44.185710 chroma info: 76 90 94 55 54 90 27 21 50 54
9418 17:16:44.189058 established: 00 00 00
9419 17:16:44.195494 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01
9420 17:16:44.199284 descriptor 1: 38 36 80 a0 70 38 20 40 18 30 3c 00 35 ae 10 00 00 19
9421 17:16:44.202634
9422 17:16:44.205752 descriptor 2: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9423 17:16:44.212083 descriptor 3: 00 00 00 fe 00 49 6e 66 6f 56 69 73 69 6f 6e 0a 20 20
9424 17:16:44.218719 descriptor 4: 00 00 00 fe 00 52 31 34 30 4e 57 46 35 20 52 48 20 0a
9425 17:16:44.221889 extensions: 00
9426 17:16:44.221976 checksum: fb
9427 17:16:44.222043
9428 17:16:44.225141 Manufacturer: IVO Model 57d Serial Number 0
9429 17:16:44.228401
9430 17:16:44.228497 Made week 0 of 2020
9431 17:16:44.232268 EDID version: 1.4
9432 17:16:44.232347 Digital display
9433 17:16:44.235413 6 bits per primary color channel
9434 17:16:44.235496 DisplayPort interface
9435 17:16:44.238520
9436 17:16:44.238599 Maximum image size: 31 cm x 17 cm
9437 17:16:44.241888 Gamma: 220%
9438 17:16:44.241970 Check DPMS levels
9439 17:16:44.248328 Supported color formats: RGB 4:4:4, YCrCb 4:2:2
9440 17:16:44.251523 First detailed timing is preferred timing
9441 17:16:44.251608 Established timings supported:
9442 17:16:44.254790
9443 17:16:44.254874 Standard timings supported:
9444 17:16:44.258646 Detailed timings
9445 17:16:44.261555 Hex of detail: 383680a07038204018303c0035ae10000019
9446 17:16:44.267997 Detailed mode (IN HEX): Clock 138800 KHz, 135 mm x ae mm
9447 17:16:44.271281 0780 0798 07c8 0820 hborder 0
9448 17:16:44.274969 0438 043b 0447 0458 vborder 0
9449 17:16:44.278066 -hsync -vsync
9450 17:16:44.278145 Did detailed timing
9451 17:16:44.284372 Hex of detail: 000000000000000000000000000000000000
9452 17:16:44.287643 Manufacturer-specified data, tag 0
9453 17:16:44.290846 Hex of detail: 000000fe00496e666f566973696f6e0a2020
9454 17:16:44.294236 ASCII string: InfoVision
9455 17:16:44.297382 Hex of detail: 000000fe00523134304e574635205248200a
9456 17:16:44.301144 ASCII string: R140NWF5 RH
9457 17:16:44.301223 Checksum
9458 17:16:44.304401 Checksum: 0xfb (valid)
9459 17:16:44.307761 configure_display: 'IVO R140NWF5 RH ' 1920x1080@0Hz
9460 17:16:44.310808 DSI data_rate: 832800000 bps
9461 17:16:44.317463 anx7625_parse_edid: detected IVO panel, use k value 0x3b
9462 17:16:44.320570 anx7625_parse_edid: pixelclock(138800).
9463 17:16:44.323934 hactive(1920), hsync(48), hfp(24), hbp(88)
9464 17:16:44.327252 vactive(1080), vsync(12), vfp(3), vbp(17)
9465 17:16:44.330431 anx7625_dsi_config: config dsi.
9466 17:16:44.337095 anx7625_dsi_video_config: compute M(11370496), N(552960), divider(4).
9467 17:16:44.351242 anx7625_dsi_config: success to config DSI
9468 17:16:44.354472 anx7625_dp_start: MIPI phy setup OK.
9469 17:16:44.358293 mtk_ddp_mode_set display resolution: 1920x1080@0 bpp 4
9470 17:16:44.360802 mtk_ddp_mode_set invalid vrefresh 60
9471 17:16:44.364079 main_disp_path_setup
9472 17:16:44.364170 ovl_layer_smi_id_en
9473 17:16:44.367813 ovl_layer_smi_id_en
9474 17:16:44.367898 ccorr_config
9475 17:16:44.367964 aal_config
9476 17:16:44.370870 gamma_config
9477 17:16:44.370983 postmask_config
9478 17:16:44.374177 dither_config
9479 17:16:44.377273 framebuffer_info: bytes_per_line: 7680, bits_per_pixel: 32
9480 17:16:44.383810 x_res x y_res: 1920 x 1080, size: 8294400 at 0x0
9481 17:16:44.387105 Root Device init finished in 531 msecs
9482 17:16:44.391077 CPU_CLUSTER: 0 init
9483 17:16:44.397461 Mapping address range [0x00200000:0x00300000) as cacheable | read-write | secure | device
9484 17:16:44.403700 INFRA2APU_SRAM_PROT_EN 0x10001e98 = 0x3fffffff
9485 17:16:44.403795 APU_MBOX 0x190000b0 = 0x10001
9486 17:16:44.406850 APU_MBOX 0x190001b0 = 0x10001
9487 17:16:44.410283 APU_MBOX 0x190005b0 = 0x10001
9488 17:16:44.413421 APU_MBOX 0x190006b0 = 0x10001
9489 17:16:44.420613 CBFS: Found 'mcupm.bin' @0x329c0 size 0xe237 in mcache @0xffffc19c
9490 17:16:44.430380 read SPI 0x539f4 0xe237: 6248 us, 9268 KB/s, 74.144 Mbps
9491 17:16:44.442599 mtk_init_mcu: Loaded (and reset) mcupm.bin in 24 msecs (117884 bytes)
9492 17:16:44.449181 CBFS: Found 'sspm.bin' @0x40c40 size 0xe8ef in mcache @0xffffc1d0
9493 17:16:44.460713 read SPI 0x61c74 0xe8ef: 6409 us, 9304 KB/s, 74.432 Mbps
9494 17:16:44.470076 mtk_init_mcu: Loaded (and reset) sspm.bin in 21 msecs (137228 bytes)
9495 17:16:44.473202 CPU_CLUSTER: 0 init finished in 81 msecs
9496 17:16:44.476512 Devices initialized
9497 17:16:44.480220 Show all devs... After init.
9498 17:16:44.480317 Root Device: enabled 1
9499 17:16:44.483436 CPU_CLUSTER: 0: enabled 1
9500 17:16:44.486690 CPU: 00: enabled 1
9501 17:16:44.489946 BS: BS_DEV_INIT run times (exec / console): 208 / 428 ms
9502 17:16:44.493319 FMAP: area RW_ELOG found @ 57f000 (4096 bytes)
9503 17:16:44.496456 ELOG: NV offset 0x57f000 size 0x1000
9504 17:16:44.503384 read SPI 0x57f000 0x1000: 488 us, 8393 KB/s, 67.144 Mbps
9505 17:16:44.509825 ELOG: area is 4096 bytes, full threshold 3842, shrink size 1024
9506 17:16:44.513022 ELOG: Event(17) added with size 13 at 2022-11-22 17:16:44 UTC
9507 17:16:44.519460 out: cmd=0x121: 03 db 21 01 00 00 00 00
9508 17:16:44.522726 in-header: 03 44 00 00 2c 00 00 00
9509 17:16:44.535811 in-data: 1b 68 00 00 00 00 00 00 0a 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
9510 17:16:44.539119 ELOG: Event(A1) added with size 10 at 2022-11-22 17:16:44 UTC
9511 17:16:44.545715 elog_add_boot_reason: Logged recovery mode boot (Dev-switch on), reason: 0x1b
9512 17:16:44.552699 ELOG: Event(A0) added with size 9 at 2022-11-22 17:16:44 UTC
9513 17:16:44.555947 elog_add_boot_reason: Logged dev mode boot
9514 17:16:44.562858 BS: BS_POST_DEVICE entry times (exec / console): 2 / 64 ms
9515 17:16:44.562975 Finalize devices...
9516 17:16:44.565319 Devices finalized
9517 17:16:44.568942 BS: BS_POST_DEVICE run times (exec / console): 0 / 3 ms
9518 17:16:44.572226 Writing coreboot table at 0xffe64000
9519 17:16:44.578618 0. 000000000010a000-0000000000113fff: RAMSTAGE
9520 17:16:44.581889 1. 0000000040000000-00000000400fffff: RAM
9521 17:16:44.585152 2. 0000000040100000-000000004032afff: RAMSTAGE
9522 17:16:44.588172 3. 000000004032b000-00000000545fffff: RAM
9523 17:16:44.592128 4. 0000000054600000-000000005465ffff: BL31
9524 17:16:44.595175 5. 0000000054660000-00000000ffe63fff: RAM
9525 17:16:44.601797 6. 00000000ffe64000-00000000ffffffff: CONFIGURATION TABLES
9526 17:16:44.604950 7. 0000000100000000-000000023fffffff: RAM
9527 17:16:44.608072 Passing 5 GPIOs to payload:
9528 17:16:44.611321 NAME | PORT | POLARITY | VALUE
9529 17:16:44.617812 EC in RW | 0x000000aa | low | undefined
9530 17:16:44.621028 EC interrupt | 0x00000005 | low | undefined
9531 17:16:44.628078 TPM interrupt | 0x000000ab | high | undefined
9532 17:16:44.631268 SD card detect | 0x00000011 | high | undefined
9533 17:16:44.634525 speaker enable | 0x00000093 | high | undefined
9534 17:16:44.641066 out: cmd=0x6: 03 f7 06 00 00 00 00 00
9535 17:16:44.644383 in-header: 03 f9 00 00 02 00 00 00
9536 17:16:44.644460 in-data: 02 00
9537 17:16:44.647636 ADC[4]: Raw value=902586 ID=7
9538 17:16:44.650815 ADC[3]: Raw value=213916 ID=1
9539 17:16:44.650929 RAM Code: 0x71
9540 17:16:44.654021 ADC[6]: Raw value=74630 ID=0
9541 17:16:44.657170 ADC[5]: Raw value=213546 ID=1
9542 17:16:44.657245 SKU Code: 0x1
9543 17:16:44.663747 Wrote coreboot table at: 0xffe64000, 0x384 bytes, checksum c6c8
9544 17:16:44.667460 coreboot table: 924 bytes.
9545 17:16:44.670681 IMD ROOT 0. 0xfffff000 0x00001000
9546 17:16:44.673668 IMD SMALL 1. 0xffffe000 0x00001000
9547 17:16:44.676869 RO MCACHE 2. 0xffffc000 0x00001104
9548 17:16:44.680544 CONSOLE 3. 0xfff7c000 0x00080000
9549 17:16:44.683862 FMAP 4. 0xfff7b000 0x00000452
9550 17:16:44.686971 TIME STAMP 5. 0xfff7a000 0x00000910
9551 17:16:44.690021 VBOOT WORK 6. 0xfff66000 0x00014000
9552 17:16:44.693466 RAMOOPS 7. 0xffe66000 0x00100000
9553 17:16:44.696643 COREBOOT 8. 0xffe64000 0x00002000
9554 17:16:44.696721 IMD small region:
9555 17:16:44.699827 IMD ROOT 0. 0xffffec00 0x00000400
9556 17:16:44.703147 MMC STATUS 1. 0xffffebe0 0x00000004
9557 17:16:44.710051 BS: BS_WRITE_TABLES run times (exec / console): 0 / 134 ms
9558 17:16:44.710133 Probing TPM: done!
9559 17:16:44.716351 Connected to device vid:did:rid of 1ae0:0028:00
9560 17:16:44.726221 Firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f77dec8
9561 17:16:44.730084 Initialized TPM device CR50 revision 0
9562 17:16:44.730165 Checking cr50 for pending updates
9563 17:16:44.733179
9564 17:16:44.736390 Reading cr50 TPM mode
9565 17:16:44.744931 BS: BS_PAYLOAD_LOAD entry times (exec / console): 9 / 22 ms
9566 17:16:44.751286 CBFS: Found 'fallback/payload' @0x3780c0 size 0x4f1b0 in mcache @0xffffd098
9567 17:16:44.791678 read SPI 0x3990ec 0x4f1b0: 34850 us, 9297 KB/s, 74.376 Mbps
9568 17:16:44.795052 Checking segment from ROM address 0x40100000
9569 17:16:44.801548 Checking segment from ROM address 0x4010001c
9570 17:16:44.804849 Loading segment from ROM address 0x40100000
9571 17:16:44.804929 code (compression=0)
9572 17:16:44.815073 New segment dstaddr 0x80000000 memsize 0x21a7280 srcaddr 0x40100038 filesize 0x4f178
9573 17:16:44.820986 Loading Segment: addr: 0x80000000 memsz: 0x00000000021a7280 filesz: 0x000000000004f178
9574 17:16:44.821070 it's not compressed!
9575 17:16:44.824319
9576 17:16:44.828070 [ 0x80000000, 8004f178, 0x821a7280) <- 40100038
9577 17:16:44.834486 Clearing Segment: addr: 0x000000008004f178 memsz: 0x0000000002158108
9578 17:16:44.853406 Loading segment from ROM address 0x4010001c
9579 17:16:44.853495 Entry Point 0x80000000
9580 17:16:44.856894 Loaded segments
9581 17:16:44.859784 BS: BS_PAYLOAD_LOAD run times (exec / console): 49 / 61 ms
9582 17:16:44.866438 Jumping to boot code at 0x80000000(0xffe64000)
9583 17:16:44.872761 CPU0: stack: 0x0010a000 - 0x0010d000, lowest used address 0x0010c500, stack used: 2816 bytes
9584 17:16:44.879770 CBFS: Found 'fallback/bl31' @0x6db40 size 0x74a8 in mcache @0xffffc290
9585 17:16:44.887794 read SPI 0x8eb68 0x74a8: 3224 us, 9263 KB/s, 74.104 Mbps
9586 17:16:44.891119 Checking segment from ROM address 0x40100000
9587 17:16:44.894198 Checking segment from ROM address 0x4010001c
9588 17:16:44.900591 Loading segment from ROM address 0x40100000
9589 17:16:44.900674 code (compression=1)
9590 17:16:44.907347 New segment dstaddr 0x54600000 memsize 0x2e000 srcaddr 0x40100038 filesize 0x7470
9591 17:16:44.917644 Loading Segment: addr: 0x54600000 memsz: 0x000000000002e000 filesz: 0x0000000000007470
9592 17:16:44.917733 using LZMA
9593 17:16:44.926064 [ 0x54600000, 54614abc, 0x5462e000) <- 40100038
9594 17:16:44.932464 Clearing Segment: addr: 0x0000000054614abc memsz: 0x0000000000019544
9595 17:16:44.935693 Loading segment from ROM address 0x4010001c
9596 17:16:44.935776 Entry Point 0x54601000
9597 17:16:44.938972
9598 17:16:44.939050 Loaded segments
9599 17:16:44.942196 NOTICE: MT8192 bl31_setup
9600 17:16:44.949383 NOTICE: BL31: v2.4(debug):v2.4-448-gce3ebc861
9601 17:16:44.953211 NOTICE: BL31: Built : Sat Sep 11 09:59:37 UTC 2021
9602 17:16:44.956493 WARNING: region 0:
9603 17:16:44.959682 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9604 17:16:44.959764 WARNING: region 1:
9605 17:16:44.966275 WARNING: sa:0x8000, ea:0x83ff, apc0: 0x80b6db40 apc1: 0xb6db6d
9606 17:16:44.969366 WARNING: region 2:
9607 17:16:44.972614 WARNING: sa:0x1000, ea:0x113f, apc0: 0x80b6d168 apc1: 0xb6db6d
9608 17:16:44.976198 WARNING: region 3:
9609 17:16:44.979586 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9610 17:16:44.982467 WARNING: region 4:
9611 17:16:44.989494 WARNING: sa:0x0, ea:0x1bfff, apc0: 0x80b6db68 apc1: 0xb6db6d
9612 17:16:44.989581 WARNING: region 5:
9613 17:16:44.992591 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9614 17:16:44.995644 WARNING: region 6:
9615 17:16:44.998984 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9616 17:16:45.002297 WARNING: region 7:
9617 17:16:45.005639 WARNING: sa:0x0, ea:0x0, apc0: 0x0 apc1: 0x0
9618 17:16:45.012195 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_0: 0x14000000
9619 17:16:45.016098 INFO: [DEVAPC] (INFRA_AO_SYS0)D0_APC_1: 0x0
9620 17:16:45.019109 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_0: 0xffffffff
9621 17:16:45.022495
9622 17:16:45.025871 INFO: [DEVAPC] (INFRA_AO_SYS0)D1_APC_1: 0xfff
9623 17:16:45.028979 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_0: 0xffffffff
9624 17:16:45.035307 INFO: [DEVAPC] (INFRA_AO_SYS0)D2_APC_1: 0x3f00
9625 17:16:45.038496 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_0: 0xffffffff
9626 17:16:45.041978 INFO: [DEVAPC] (INFRA_AO_SYS0)D3_APC_1: 0x3fff
9627 17:16:45.048984 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_0: 0xffffffff
9628 17:16:45.052132 INFO: [DEVAPC] (INFRA_AO_SYS0)D4_APC_1: 0x3fff
9629 17:16:45.058668 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_0: 0xffffffff
9630 17:16:45.061971 INFO: [DEVAPC] (INFRA_AO_SYS0)D5_APC_1: 0x3fff
9631 17:16:45.065235 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_0: 0xffffffff
9632 17:16:45.072341 INFO: [DEVAPC] (INFRA_AO_SYS0)D6_APC_1: 0x3fff
9633 17:16:45.074939 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_0: 0xffffffff
9634 17:16:45.078459 INFO: [DEVAPC] (INFRA_AO_SYS0)D7_APC_1: 0x3fff
9635 17:16:45.084900 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_0: 0xffffffff
9636 17:16:45.088260 INFO: [DEVAPC] (INFRA_AO_SYS0)D8_APC_1: 0x3fff
9637 17:16:45.094817 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_0: 0xffffffff
9638 17:16:45.098160 INFO: [DEVAPC] (INFRA_AO_SYS0)D9_APC_1: 0x3fff
9639 17:16:45.101493 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_0: 0xffffffff
9640 17:16:45.107958 INFO: [DEVAPC] (INFRA_AO_SYS0)D10_APC_1: 0x3fff
9641 17:16:45.111216 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_0: 0xffffffff
9642 17:16:45.118161 INFO: [DEVAPC] (INFRA_AO_SYS0)D11_APC_1: 0x3fff
9643 17:16:45.121529 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_0: 0xffffffff
9644 17:16:45.124853 INFO: [DEVAPC] (INFRA_AO_SYS0)D12_APC_1: 0x3fff
9645 17:16:45.130900 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_0: 0xffffffff
9646 17:16:45.134240 INFO: [DEVAPC] (INFRA_AO_SYS0)D13_APC_1: 0x3fff
9647 17:16:45.141430 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_0: 0xffffffff
9648 17:16:45.144735 INFO: [DEVAPC] (INFRA_AO_SYS0)D14_APC_1: 0x3fff
9649 17:16:45.151227 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_0: 0xffffffff
9650 17:16:45.154558 INFO: [DEVAPC] (INFRA_AO_SYS0)D15_APC_1: 0x3fff
9651 17:16:45.157727 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_0: 0x0
9652 17:16:45.161006 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_1: 0x0
9653 17:16:45.168168 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_2: 0x0
9654 17:16:45.170678 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_3: 0x0
9655 17:16:45.174567 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_4: 0x0
9656 17:16:45.177726 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_5: 0x0
9657 17:16:45.184091 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_6: 0x0
9658 17:16:45.187104 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_7: 0x0
9659 17:16:45.190292 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_8: 0x0
9660 17:16:45.194295 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_9: 0x0
9661 17:16:45.200369 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_10: 0x0
9662 17:16:45.203555 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_11: 0x0
9663 17:16:45.206856 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_12: 0x0
9664 17:16:45.210625 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_13: 0x0
9665 17:16:45.217046 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_14: 0x0
9666 17:16:45.220401 INFO: [DEVAPC] (INFRA_AO_SYS1)D0_APC_15: 0x0
9667 17:16:45.223551 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_0: 0xffffffff
9668 17:16:45.230539 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_1: 0xffffffff
9669 17:16:45.233912 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_2: 0xffffffff
9670 17:16:45.240399 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_3: 0xffffffff
9671 17:16:45.243623 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_4: 0xffffffff
9672 17:16:45.250072 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_5: 0xffffffff
9673 17:16:45.253248 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_6: 0xffffffff
9674 17:16:45.259708 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_7: 0xffffffff
9675 17:16:45.263162 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_8: 0xffffffff
9676 17:16:45.267034 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_9: 0xffffffff
9677 17:16:45.273522 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_10: 0xffffffff
9678 17:16:45.276700 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_11: 0xffffffff
9679 17:16:45.282858 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_12: 0xffffffff
9680 17:16:45.286523 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_13: 0xffffffff
9681 17:16:45.293167 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_14: 0xffffffff
9682 17:16:45.296338 INFO: [DEVAPC] (INFRA_AO_SYS1)D1_APC_15: 0xffffffff
9683 17:16:45.303076 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_0: 0xffffffff
9684 17:16:45.306323 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_1: 0xffffffff
9685 17:16:45.309639 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_2: 0xffffffff
9686 17:16:45.316173 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_3: 0xffffffff
9687 17:16:45.319262 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_4: 0xffffffff
9688 17:16:45.326327 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_5: 0xffffffff
9689 17:16:45.329440 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_6: 0xffffffff
9690 17:16:45.335778 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_7: 0xffffffff
9691 17:16:45.339099 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_8: 0xffffffff
9692 17:16:45.345608 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_9: 0xffffffff
9693 17:16:45.348988 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_10: 0xffffffff
9694 17:16:45.352376 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_11: 0xffffffff
9695 17:16:45.359395 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_12: 0xffffffff
9696 17:16:45.362804 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_13: 0xffffffff
9697 17:16:45.369239 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_14: 0xffffffff
9698 17:16:45.372516 INFO: [DEVAPC] (INFRA_AO_SYS1)D2_APC_15: 0xffffffff
9699 17:16:45.378798 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_0: 0xffffffff
9700 17:16:45.382605 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_1: 0xffffffff
9701 17:16:45.388950 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_2: 0xffffffff
9702 17:16:45.391978 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_3: 0xffffffff
9703 17:16:45.395393 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_4: 0xffffffff
9704 17:16:45.402079 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_5: 0xcfff30ff
9705 17:16:45.405234 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_6: 0xffffffff
9706 17:16:45.411969 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_7: 0xffffffff
9707 17:16:45.415251 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_8: 0xffffffff
9708 17:16:45.422216 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_9: 0xffffffff
9709 17:16:45.425541 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_10: 0xffffffff
9710 17:16:45.431815 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_11: 0xffffffff
9711 17:16:45.435228 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_12: 0xffffffff
9712 17:16:45.438944 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_13: 0xffffffff
9713 17:16:45.444829 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_14: 0xffffffff
9714 17:16:45.448583 INFO: [DEVAPC] (INFRA_AO_SYS1)D3_APC_15: 0xffffffff
9715 17:16:45.455158 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_0: 0x0
9716 17:16:45.458420 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_1: 0x0
9717 17:16:45.461564 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_2: 0x0
9718 17:16:45.464855 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_3: 0x0
9719 17:16:45.471336 INFO: [DEVAPC] (INFRA_AO_SYS2)D0_APC_4: 0x0
9720 17:16:45.474686 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_0: 0xffffffff
9721 17:16:45.478044 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_1: 0xffffffff
9722 17:16:45.481410
9723 17:16:45.485103 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_2: 0xffffffff
9724 17:16:45.488295 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_3: 0xffffffff
9725 17:16:45.494596 INFO: [DEVAPC] (INFRA_AO_SYS2)D1_APC_4: 0xfff
9726 17:16:45.497823 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_0: 0xffffffff
9727 17:16:45.504149 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_1: 0xffffffff
9728 17:16:45.507822 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_2: 0xffffffff
9729 17:16:45.511223 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_3: 0xffffffff
9730 17:16:45.517203 INFO: [DEVAPC] (INFRA_AO_SYS2)D2_APC_4: 0xfff
9731 17:16:45.520365 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_0: 0xffffffff
9732 17:16:45.527038 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_1: 0xffffffff
9733 17:16:45.530321 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_2: 0xffffffff
9734 17:16:45.537429 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_3: 0xffffffff
9735 17:16:45.540377 INFO: [DEVAPC] (INFRA_AO_SYS2)D3_APC_4: 0xfff
9736 17:16:45.543536 INFO: [DEVAPC] (INFRA_AO)MAS_SEC_0: 0x18
9737 17:16:45.546946 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_0: 0x10000000
9738 17:16:45.553484 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_1: 0x1000004
9739 17:16:45.557433 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_2: 0x0
9740 17:16:45.560069 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_3: 0x0
9741 17:16:45.563873 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_4: 0x0
9742 17:16:45.567213
9743 17:16:45.570336 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_5: 0x0
9744 17:16:45.573598 INFO: [DEVAPC] (PERI_AO_SYS0)D0_APC_6: 0x10000
9745 17:16:45.576957 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_0: 0xffffffff
9746 17:16:45.583318 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_1: 0xffffffff
9747 17:16:45.586555 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_2: 0xffffffff
9748 17:16:45.593413 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_3: 0x3fffffff
9749 17:16:45.596742 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_4: 0xffffffff
9750 17:16:45.603487 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_5: 0xffffffff
9751 17:16:45.606745 INFO: [DEVAPC] (PERI_AO_SYS0)D1_APC_6: 0x3ffff
9752 17:16:45.609822 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_0: 0xfffc03fc
9753 17:16:45.616327 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_1: 0xfff3ffff
9754 17:16:45.619518 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_2: 0xfffcfccf
9755 17:16:45.622835 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_3: 0xff3fffff
9756 17:16:45.626606
9757 17:16:45.629351 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_4: 0xffff3ffc
9758 17:16:45.633198 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_5: 0xffffffff
9759 17:16:45.639531 INFO: [DEVAPC] (PERI_AO_SYS0)D2_APC_6: 0x3ffff
9760 17:16:45.642620 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_0: 0xff3f33ff
9761 17:16:45.645908 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_1: 0xffffffff
9762 17:16:45.652947 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_2: 0xffffffff
9763 17:16:45.656242 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_3: 0xffffffff
9764 17:16:45.662522 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_4: 0xffffffff
9765 17:16:45.665880 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_5: 0xffffffff
9766 17:16:45.669046 INFO: [DEVAPC] (PERI_AO_SYS0)D3_APC_6: 0x3ffff
9767 17:16:45.675669 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_0: 0xffffffff
9768 17:16:45.678949 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_1: 0xffffffff
9769 17:16:45.685961 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_2: 0xffffffff
9770 17:16:45.689177 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_3: 0xffffffff
9771 17:16:45.692282 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_4: 0xffffffff
9772 17:16:45.698624 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_5: 0xffffffff
9773 17:16:45.702337 INFO: [DEVAPC] (PERI_AO_SYS0)D4_APC_6: 0x3ffff
9774 17:16:45.708770 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_0: 0xffffffff
9775 17:16:45.711969 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_1: 0xffffffff
9776 17:16:45.715190 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_2: 0xffffffff
9777 17:16:45.722268 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_3: 0xffffffff
9778 17:16:45.725448 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_4: 0xffffffff
9779 17:16:45.731982 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_5: 0xffffffff
9780 17:16:45.735274 INFO: [DEVAPC] (PERI_AO_SYS0)D5_APC_6: 0x3ffff
9781 17:16:45.738526 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_0: 0xffffffff
9782 17:16:45.744843 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_1: 0xffffffff
9783 17:16:45.748111 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_2: 0xffffffff
9784 17:16:45.754664 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_3: 0xffffffff
9785 17:16:45.757899 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_4: 0xffffffff
9786 17:16:45.764413 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_5: 0xffffffff
9787 17:16:45.768348 INFO: [DEVAPC] (PERI_AO_SYS0)D6_APC_6: 0x3ffff
9788 17:16:45.771594 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_0: 0xffffffff
9789 17:16:45.777989 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_1: 0xffffffff
9790 17:16:45.781192 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_2: 0xffffffff
9791 17:16:45.787672 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_3: 0xffffffff
9792 17:16:45.790820 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_4: 0xffffffff
9793 17:16:45.794418 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_5: 0xffffffff
9794 17:16:45.800627 INFO: [DEVAPC] (PERI_AO_SYS0)D7_APC_6: 0x3ffff
9795 17:16:45.804043 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_0: 0xfffff3ff
9796 17:16:45.810870 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_1: 0xffffffff
9797 17:16:45.813899 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_2: 0xffffffff
9798 17:16:45.817215 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_3: 0xffffffff
9799 17:16:45.824219 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_4: 0xffffffff
9800 17:16:45.827324 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_5: 0xffffffff
9801 17:16:45.833804 INFO: [DEVAPC] (PERI_AO_SYS0)D8_APC_6: 0x3ffff
9802 17:16:45.837172 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_0: 0xffffffff
9803 17:16:45.840489 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_1: 0xffffffff
9804 17:16:45.846855 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_2: 0xffffffff
9805 17:16:45.850077 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_3: 0xffffffff
9806 17:16:45.856563 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_4: 0xffffffff
9807 17:16:45.859895 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_5: 0xffffffff
9808 17:16:45.863213 INFO: [DEVAPC] (PERI_AO_SYS0)D9_APC_6: 0x3ffff
9809 17:16:45.870173 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_0: 0xffffffff
9810 17:16:45.873503 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_1: 0xffffffff
9811 17:16:45.879436 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_2: 0xffffffff
9812 17:16:45.883437 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_3: 0xffffffff
9813 17:16:45.889665 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_4: 0xffffffff
9814 17:16:45.892928 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_5: 0xffffffff
9815 17:16:45.896565 INFO: [DEVAPC] (PERI_AO_SYS0)D10_APC_6: 0x3ffff
9816 17:16:45.902582 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_0: 0xffffffff
9817 17:16:45.905806 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_1: 0xffffffff
9818 17:16:45.912806 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_2: 0xffffffff
9819 17:16:45.915965 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_3: 0xffffffff
9820 17:16:45.922444 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_4: 0xffffffff
9821 17:16:45.925583 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_5: 0xffffffff
9822 17:16:45.928634 INFO: [DEVAPC] (PERI_AO_SYS0)D11_APC_6: 0x3ffff
9823 17:16:45.935687 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_0: 0xffffffff
9824 17:16:45.938930 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_1: 0xffffffff
9825 17:16:45.945482 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_2: 0xffffffff
9826 17:16:45.948621 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_3: 0xffffffff
9827 17:16:45.955079 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_4: 0xffffffff
9828 17:16:45.958463 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_5: 0xffffffff
9829 17:16:45.961794 INFO: [DEVAPC] (PERI_AO_SYS0)D12_APC_6: 0x3ffff
9830 17:16:45.968780 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_0: 0xffffffff
9831 17:16:45.971950 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_1: 0xffffffff
9832 17:16:45.978651 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_2: 0xffffffff
9833 17:16:45.981788 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_3: 0xffffffff
9834 17:16:45.988037 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_4: 0xffffffff
9835 17:16:45.991339 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_5: 0xffffffff
9836 17:16:45.994432 INFO: [DEVAPC] (PERI_AO_SYS0)D13_APC_6: 0x3ffff
9837 17:16:46.001200 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_0: 0xffffffff
9838 17:16:46.004239 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_1: 0xffffffff
9839 17:16:46.011402 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_2: 0xffffffff
9840 17:16:46.014707 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_3: 0xffffffff
9841 17:16:46.021164 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_4: 0xffffffff
9842 17:16:46.024163 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_5: 0xffffffff
9843 17:16:46.027375 INFO: [DEVAPC] (PERI_AO_SYS0)D14_APC_6: 0x3ffff
9844 17:16:46.034534 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_0: 0xffffffff
9845 17:16:46.037768 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_1: 0xffffffff
9846 17:16:46.044092 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_2: 0xffffffff
9847 17:16:46.047485 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_3: 0xffffffff
9848 17:16:46.053726 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_4: 0xffffffff
9849 17:16:46.057127 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_5: 0xffffffff
9850 17:16:46.060463 INFO: [DEVAPC] (PERI_AO_SYS0)D15_APC_6: 0x3ffff
9851 17:16:46.067096 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_0: 0x0
9852 17:16:46.070297 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_1: 0x0
9853 17:16:46.073435 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_2: 0x0
9854 17:16:46.076770 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_3: 0x0
9855 17:16:46.083196 INFO: [DEVAPC] (PERI_AO_SYS1)D0_APC_4: 0x0
9856 17:16:46.086509 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_0: 0xffffffff
9857 17:16:46.089600 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_1: 0xffffffff
9858 17:16:46.092948
9859 17:16:46.096611 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_2: 0xffffffff
9860 17:16:46.100049 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_3: 0xffffffff
9861 17:16:46.106205 INFO: [DEVAPC] (PERI_AO_SYS1)D1_APC_4: 0xf
9862 17:16:46.109567 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_0: 0xffffffff
9863 17:16:46.112820 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_1: 0xffffffff
9864 17:16:46.119604 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_2: 0xffffffff
9865 17:16:46.122974 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_3: 0xffffffff
9866 17:16:46.126195 INFO: [DEVAPC] (PERI_AO_SYS1)D2_APC_4: 0xf
9867 17:16:46.132617 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_0: 0xffffffff
9868 17:16:46.135855 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_1: 0xffffffff
9869 17:16:46.142286 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_2: 0xffffffff
9870 17:16:46.145639 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_3: 0xffffffff
9871 17:16:46.148770 INFO: [DEVAPC] (PERI_AO_SYS1)D3_APC_4: 0xf
9872 17:16:46.155282 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_0: 0xffffffff
9873 17:16:46.158510 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_1: 0xffffffff
9874 17:16:46.165144 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_2: 0xffffffff
9875 17:16:46.169061 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_3: 0xffffffff
9876 17:16:46.172294 INFO: [DEVAPC] (PERI_AO_SYS1)D4_APC_4: 0xf
9877 17:16:46.178806 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_0: 0xffffffff
9878 17:16:46.181982 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_1: 0xffffffff
9879 17:16:46.188575 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_2: 0xffffffff
9880 17:16:46.191852 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_3: 0xffffffff
9881 17:16:46.194971 INFO: [DEVAPC] (PERI_AO_SYS1)D5_APC_4: 0xf
9882 17:16:46.201937 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_0: 0xffffffff
9883 17:16:46.204856 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_1: 0xffffffff
9884 17:16:46.208039 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_2: 0xffffffff
9885 17:16:46.214435 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_3: 0xffffffff
9886 17:16:46.218199 INFO: [DEVAPC] (PERI_AO_SYS1)D6_APC_4: 0xf
9887 17:16:46.221249 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_0: 0xffffffff
9888 17:16:46.227897 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_1: 0xffffffff
9889 17:16:46.231048 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_2: 0xffffffff
9890 17:16:46.237416 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_3: 0xffffffff
9891 17:16:46.240683 INFO: [DEVAPC] (PERI_AO_SYS1)D7_APC_4: 0xf
9892 17:16:46.243967 INFO: [DEVAPC] (PERI_AO_SYS2)D0_APC_0: 0x0
9893 17:16:46.247179 INFO: [DEVAPC] (PERI_AO_SYS2)D1_APC_0: 0x3
9894 17:16:46.253779 INFO: [DEVAPC] (PERI_AO_SYS2)D2_APC_0: 0x3
9895 17:16:46.257384 INFO: [DEVAPC] (PERI_AO_SYS2)D3_APC_0: 0x3
9896 17:16:46.260796 INFO: [DEVAPC] (PERI_AO)MAS_SEC_0: 0x0
9897 17:16:46.264015 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_0: 0x400400
9898 17:16:46.270477 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_1: 0x0
9899 17:16:46.273727 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_2: 0x0
9900 17:16:46.276948 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_3: 0x0
9901 17:16:46.280162 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_4: 0x0
9902 17:16:46.287245 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_5: 0x0
9903 17:16:46.290533 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_6: 0x140000
9904 17:16:46.293601 INFO: [DEVAPC] (PERI_AO2_SYS0)D0_APC_7: 0x0
9905 17:16:46.300140 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_0: 0xffffffff
9906 17:16:46.303158 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_1: 0xffffffff
9907 17:16:46.310110 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_2: 0xffffffff
9908 17:16:46.313398 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_3: 0xffffffff
9909 17:16:46.319600 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_4: 0xffffffff
9910 17:16:46.323184 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_5: 0xffffffff
9911 17:16:46.326391 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_6: 0xffffffff
9912 17:16:46.332931 INFO: [DEVAPC] (PERI_AO2_SYS0)D1_APC_7: 0x3f
9913 17:16:46.336077 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_0: 0xfffffff3
9914 17:16:46.343256 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_1: 0xffffefff
9915 17:16:46.346353 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_2: 0xffffffff
9916 17:16:46.349142 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_3: 0xffffffff
9917 17:16:46.353075
9918 17:16:46.356210 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_4: 0xffffffff
9919 17:16:46.359470 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_5: 0xcfffffff
9920 17:16:46.365923 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_6: 0xf3fcffff
9921 17:16:46.369227 INFO: [DEVAPC] (PERI_AO2_SYS0)D2_APC_7: 0x3f
9922 17:16:46.375743 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_0: 0xffffffff
9923 17:16:46.379090 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_1: 0xffffffff
9924 17:16:46.382203 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_2: 0xffffffff
9925 17:16:46.388927 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_3: 0xffffffff
9926 17:16:46.391961 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_4: 0xffffffff
9927 17:16:46.398703 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_5: 0xffffffff
9928 17:16:46.401905 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_6: 0xffffffff
9929 17:16:46.405587 INFO: [DEVAPC] (PERI_AO2_SYS0)D3_APC_7: 0x3f
9930 17:16:46.408850
9931 17:16:46.411922 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_0: 0xffffffff
9932 17:16:46.415111 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_1: 0xffffffff
9933 17:16:46.421422 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_2: 0xffffffff
9934 17:16:46.425346 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_3: 0xffffffff
9935 17:16:46.431810 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_4: 0xffffffff
9936 17:16:46.434891 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_5: 0xffffffff
9937 17:16:46.441301 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_6: 0xffffffff
9938 17:16:46.445136 INFO: [DEVAPC] (PERI_AO2_SYS0)D4_APC_7: 0x3f
9939 17:16:46.447755 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_0: 0xffffffff
9940 17:16:46.454762 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_1: 0xffffffff
9941 17:16:46.457946 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_2: 0xffffffff
9942 17:16:46.464546 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_3: 0xffffffff
9943 17:16:46.467774 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_4: 0xffffffff
9944 17:16:46.474347 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_5: 0xffffffff
9945 17:16:46.477478 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_6: 0xffffffff
9946 17:16:46.480809 INFO: [DEVAPC] (PERI_AO2_SYS0)D5_APC_7: 0x3f
9947 17:16:46.487500 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_0: 0xffffffff
9948 17:16:46.490809 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_1: 0xffffffff
9949 17:16:46.497249 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_2: 0xffffffff
9950 17:16:46.500425 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_3: 0xffffffff
9951 17:16:46.503692 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_4: 0xffffffff
9952 17:16:46.506827
9953 17:16:46.510555 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_5: 0xffffffff
9954 17:16:46.513753 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_6: 0xffffffff
9955 17:16:46.519961 INFO: [DEVAPC] (PERI_AO2_SYS0)D6_APC_7: 0x3f
9956 17:16:46.523814 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_0: 0xffffffff
9957 17:16:46.530218 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_1: 0xffffffff
9958 17:16:46.533520 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_2: 0xffffffff
9959 17:16:46.536610 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_3: 0xffffffff
9960 17:16:46.542982 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_4: 0xffffffff
9961 17:16:46.546340 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_5: 0xffffffff
9962 17:16:46.552770 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_6: 0xffffffff
9963 17:16:46.556048 INFO: [DEVAPC] (PERI_AO2_SYS0)D7_APC_7: 0x3f
9964 17:16:46.559408 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_0: 0xffffffff
9965 17:16:46.566526 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_1: 0xffffffff
9966 17:16:46.569124 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_2: 0xffffffff
9967 17:16:46.575587 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_3: 0xffffffff
9968 17:16:46.579503 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_4: 0xffffffff
9969 17:16:46.585944 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_5: 0xffffffff
9970 17:16:46.589302 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_6: 0xffffffff
9971 17:16:46.592361 INFO: [DEVAPC] (PERI_AO2_SYS0)D8_APC_7: 0x3f
9972 17:16:46.598956 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_0: 0xffffffff
9973 17:16:46.602184 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_1: 0xffffffff
9974 17:16:46.608431 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_2: 0xffffffff
9975 17:16:46.612117 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_3: 0xffffffff
9976 17:16:46.618239 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_4: 0xffffffff
9977 17:16:46.621619 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_5: 0xffffffff
9978 17:16:46.628557 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_6: 0xffffffff
9979 17:16:46.631624 INFO: [DEVAPC] (PERI_AO2_SYS0)D9_APC_7: 0x3f
9980 17:16:46.634921 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_0: 0xffffffff
9981 17:16:46.641389 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_1: 0xffffffff
9982 17:16:46.644615 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_2: 0xffffffff
9983 17:16:46.651737 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_3: 0xffffffff
9984 17:16:46.654322 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_4: 0xffffffff
9985 17:16:46.661320 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_5: 0xffffffff
9986 17:16:46.664758 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_6: 0xffffffff
9987 17:16:46.667959 INFO: [DEVAPC] (PERI_AO2_SYS0)D10_APC_7: 0x3f
9988 17:16:46.671231
9989 17:16:46.674569 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_0: 0xffffffff
9990 17:16:46.677816 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_1: 0xffffffff
9991 17:16:46.684322 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_2: 0xffffffff
9992 17:16:46.687625 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_3: 0xffffffff
9993 17:16:46.693664 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_4: 0xffffffff
9994 17:16:46.696923 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_5: 0xffffffff
9995 17:16:46.703416 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_6: 0xffffffff
9996 17:16:46.707035 INFO: [DEVAPC] (PERI_AO2_SYS0)D11_APC_7: 0x3f
9997 17:16:46.713678 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_0: 0xffffffff
9998 17:16:46.716890 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_1: 0xffffffff
9999 17:16:46.720123 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_2: 0xffffffff
10000 17:16:46.723270
10001 17:16:46.726524 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_3: 0xffffffff
10002 17:16:46.729740 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_4: 0xffffffff
10003 17:16:46.736570 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_5: 0xffffffff
10004 17:16:46.739790 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_6: 0xffffffff
10005 17:16:46.746315 INFO: [DEVAPC] (PERI_AO2_SYS0)D12_APC_7: 0x3f
10006 17:16:46.749471 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_0: 0xffffffff
10007 17:16:46.756148 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_1: 0xffffffff
10008 17:16:46.759348 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_2: 0xffffffff
10009 17:16:46.765930 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_3: 0xffffffff
10010 17:16:46.769218 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_4: 0xffffffff
10011 17:16:46.775617 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_5: 0xffffffff
10012 17:16:46.779058 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_6: 0xffffffff
10013 17:16:46.782211 INFO: [DEVAPC] (PERI_AO2_SYS0)D13_APC_7: 0x3f
10014 17:16:46.789248 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_0: 0xffffffff
10015 17:16:46.792468 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_1: 0xffffffff
10016 17:16:46.798899 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_2: 0xffffffff
10017 17:16:46.802293 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_3: 0xffffffff
10018 17:16:46.808827 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_4: 0xffffffff
10019 17:16:46.811958 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_5: 0xffffffff
10020 17:16:46.818205 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_6: 0xffffffff
10021 17:16:46.821930 INFO: [DEVAPC] (PERI_AO2_SYS0)D14_APC_7: 0x3f
10022 17:16:46.825188 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_0: 0xffffffff
10023 17:16:46.831443 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_1: 0xffffffff
10024 17:16:46.835252 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_2: 0xffffffff
10025 17:16:46.841176 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_3: 0xffffffff
10026 17:16:46.845012 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_4: 0xffffffff
10027 17:16:46.851597 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_5: 0xffffffff
10028 17:16:46.854821 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_6: 0xffffffff
10029 17:16:46.861627 INFO: [DEVAPC] (PERI_AO2_SYS0)D15_APC_7: 0x3f
10030 17:16:46.864231 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_0: 0x0
10031 17:16:46.867532 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D0_APC_1: 0x10000
10032 17:16:46.874500 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_0: 0xffffffff
10033 17:16:46.877816 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D1_APC_1: 0x3fffff
10034 17:16:46.884415 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_0: 0xffffcff3
10035 17:16:46.887665 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D2_APC_1: 0x3fcfff
10036 17:16:46.894147 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_0: 0xffffffff
10037 17:16:46.897286 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D3_APC_1: 0x3fffff
10038 17:16:46.903954 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_0: 0xffffffff
10039 17:16:46.907034 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D4_APC_1: 0x3fffff
10040 17:16:46.913975 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_0: 0xffffffff
10041 17:16:46.917044 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D5_APC_1: 0x3fffff
10042 17:16:46.923276 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_0: 0xffffffff
10043 17:16:46.926492 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D6_APC_1: 0x3fffff
10044 17:16:46.933439 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_0: 0xffffffff
10045 17:16:46.936661 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D7_APC_1: 0x3fffff
10046 17:16:46.943036 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_0: 0xffffffff
10047 17:16:46.946321 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D8_APC_1: 0x3fffff
10048 17:16:46.953448 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_0: 0xffffffff
10049 17:16:46.956844 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D9_APC_1: 0x3fffff
10050 17:16:46.963127 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_0: 0xffffffff
10051 17:16:46.965903 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D10_APC_1: 0x3fffff
10052 17:16:46.972992 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_0: 0xffffffff
10053 17:16:46.976221 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D11_APC_1: 0x3fffff
10054 17:16:46.982745 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_0: 0xffffffff
10055 17:16:46.986017 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D12_APC_1: 0x3fffff
10056 17:16:46.992425 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_0: 0xffffffff
10057 17:16:46.995561 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D13_APC_1: 0x3fffff
10058 17:16:47.002416 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_0: 0xffffffff
10059 17:16:47.005453 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D14_APC_1: 0x3fffff
10060 17:16:47.012016 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_0: 0xffffffff
10061 17:16:47.019033 INFO: [DEVAPC] (PERI_PAR_AO_SYS0)D15_APC_1: 0x3fffff
10062 17:16:47.021950 INFO: [DEVAPC] (PERI_PAR_AO)MAS_SEC_0: 0x0
10063 17:16:47.022049 INFO: [APUAPC] vio 0
10064 17:16:47.029601 INFO: [APUAPC] set_apusys_ao_apc - SUCCESS!
10065 17:16:47.032653 INFO: [APUAPC] set_apusys_noc_dapc - SUCCESS!
10066 17:16:47.036397 INFO: [APUAPC] D0_APC_0: 0x400510
10067 17:16:47.039559 INFO: [APUAPC] D0_APC_1: 0x0
10068 17:16:47.042899 INFO: [APUAPC] D0_APC_2: 0x1540
10069 17:16:47.046117 INFO: [APUAPC] D0_APC_3: 0x0
10070 17:16:47.049234 INFO: [APUAPC] D1_APC_0: 0xffffffff
10071 17:16:47.052605 INFO: [APUAPC] D1_APC_1: 0xffffffff
10072 17:16:47.055723 INFO: [APUAPC] D1_APC_2: 0x3fffff
10073 17:16:47.059065 INFO: [APUAPC] D1_APC_3: 0x0
10074 17:16:47.062218 INFO: [APUAPC] D2_APC_0: 0xffffffff
10075 17:16:47.065514 INFO: [APUAPC] D2_APC_1: 0xffffffff
10076 17:16:47.068585 INFO: [APUAPC] D2_APC_2: 0x3fffff
10077 17:16:47.071826 INFO: [APUAPC] D2_APC_3: 0x0
10078 17:16:47.075189 INFO: [APUAPC] D3_APC_0: 0xffffffff
10079 17:16:47.078480 INFO: [APUAPC] D3_APC_1: 0xffffffff
10080 17:16:47.081773 INFO: [APUAPC] D3_APC_2: 0x3fffff
10081 17:16:47.084916 INFO: [APUAPC] D3_APC_3: 0x0
10082 17:16:47.088212 INFO: [APUAPC] D4_APC_0: 0xffffffff
10083 17:16:47.091950 INFO: [APUAPC] D4_APC_1: 0xffffffff
10084 17:16:47.095253 INFO: [APUAPC] D4_APC_2: 0x3fffff
10085 17:16:47.098341 INFO: [APUAPC] D4_APC_3: 0x0
10086 17:16:47.101649 INFO: [APUAPC] D5_APC_0: 0xffffffff
10087 17:16:47.104935 INFO: [APUAPC] D5_APC_1: 0xffffffff
10088 17:16:47.108168 INFO: [APUAPC] D5_APC_2: 0x3fffff
10089 17:16:47.111342 INFO: [APUAPC] D5_APC_3: 0x0
10090 17:16:47.114754 INFO: [APUAPC] D6_APC_0: 0xffffffff
10091 17:16:47.117832 INFO: [APUAPC] D6_APC_1: 0xffffffff
10092 17:16:47.121588 INFO: [APUAPC] D6_APC_2: 0x3fffff
10093 17:16:47.124747 INFO: [APUAPC] D6_APC_3: 0x0
10094 17:16:47.127895 INFO: [APUAPC] D7_APC_0: 0xffffffff
10095 17:16:47.131001 INFO: [APUAPC] D7_APC_1: 0xffffffff
10096 17:16:47.134255 INFO: [APUAPC] D7_APC_2: 0x3fffff
10097 17:16:47.137369 INFO: [APUAPC] D7_APC_3: 0x0
10098 17:16:47.141095 INFO: [APUAPC] D8_APC_0: 0xffffffff
10099 17:16:47.144334 INFO: [APUAPC] D8_APC_1: 0xffffffff
10100 17:16:47.147449 INFO: [APUAPC] D8_APC_2: 0x3fffff
10101 17:16:47.150749 INFO: [APUAPC] D8_APC_3: 0x0
10102 17:16:47.153907 INFO: [APUAPC] D9_APC_0: 0xffffffff
10103 17:16:47.157120 INFO: [APUAPC] D9_APC_1: 0xffffffff
10104 17:16:47.160301 INFO: [APUAPC] D9_APC_2: 0x3fffff
10105 17:16:47.160384 INFO: [APUAPC] D9_APC_3: 0x0
10106 17:16:47.164117
10107 17:16:47.167563 INFO: [APUAPC] D10_APC_0: 0xffffffff
10108 17:16:47.170818 INFO: [APUAPC] D10_APC_1: 0xffffffff
10109 17:16:47.173493 INFO: [APUAPC] D10_APC_2: 0x3fffff
10110 17:16:47.176748 INFO: [APUAPC] D10_APC_3: 0x0
10111 17:16:47.180642 INFO: [APUAPC] D11_APC_0: 0xffffffff
10112 17:16:47.183935 INFO: [APUAPC] D11_APC_1: 0xffffffff
10113 17:16:47.187228 INFO: [APUAPC] D11_APC_2: 0x3fffff
10114 17:16:47.189791 INFO: [APUAPC] D11_APC_3: 0x0
10115 17:16:47.193847 INFO: [APUAPC] D12_APC_0: 0xffffffff
10116 17:16:47.197047 INFO: [APUAPC] D12_APC_1: 0xffffffff
10117 17:16:47.200306 INFO: [APUAPC] D12_APC_2: 0x3fffff
10118 17:16:47.203462 INFO: [APUAPC] D12_APC_3: 0x0
10119 17:16:47.206767 INFO: [APUAPC] D13_APC_0: 0xffffffff
10120 17:16:47.209962 INFO: [APUAPC] D13_APC_1: 0xffffffff
10121 17:16:47.213161 INFO: [APUAPC] D13_APC_2: 0x3fffff
10122 17:16:47.216332 INFO: [APUAPC] D13_APC_3: 0x0
10123 17:16:47.219594 INFO: [APUAPC] D14_APC_0: 0xffffffff
10124 17:16:47.223209 INFO: [APUAPC] D14_APC_1: 0xffffffff
10125 17:16:47.226355 INFO: [APUAPC] D14_APC_2: 0x3fffff
10126 17:16:47.229439 INFO: [APUAPC] D14_APC_3: 0x0
10127 17:16:47.232616 INFO: [APUAPC] D15_APC_0: 0xffffffff
10128 17:16:47.235863 INFO: [APUAPC] D15_APC_1: 0xffffffff
10129 17:16:47.239079 INFO: [APUAPC] D15_APC_2: 0x3fffff
10130 17:16:47.242658 INFO: [APUAPC] D15_APC_3: 0x0
10131 17:16:47.245760 INFO: [APUAPC] APC_CON: 0x4
10132 17:16:47.249113 INFO: [NOCDAPC] D0_APC_0: 0x0
10133 17:16:47.252447 INFO: [NOCDAPC] D0_APC_1: 0x0
10134 17:16:47.252539 INFO: [NOCDAPC] D1_APC_0: 0x0
10135 17:16:47.255609 INFO: [NOCDAPC] D1_APC_1: 0xfff
10136 17:16:47.258775 INFO: [NOCDAPC] D2_APC_0: 0x0
10137 17:16:47.262561 INFO: [NOCDAPC] D2_APC_1: 0xfff
10138 17:16:47.265889 INFO: [NOCDAPC] D3_APC_0: 0x0
10139 17:16:47.269069 INFO: [NOCDAPC] D3_APC_1: 0xfff
10140 17:16:47.272235 INFO: [NOCDAPC] D4_APC_0: 0x0
10141 17:16:47.275600 INFO: [NOCDAPC] D4_APC_1: 0xfff
10142 17:16:47.278622 INFO: [NOCDAPC] D5_APC_0: 0x0
10143 17:16:47.281903 INFO: [NOCDAPC] D5_APC_1: 0xfff
10144 17:16:47.285161 INFO: [NOCDAPC] D6_APC_0: 0x0
10145 17:16:47.288482 INFO: [NOCDAPC] D6_APC_1: 0xfff
10146 17:16:47.288568 INFO: [NOCDAPC] D7_APC_0: 0x0
10147 17:16:47.291650
10148 17:16:47.291739 INFO: [NOCDAPC] D7_APC_1: 0xfff
10149 17:16:47.294929 INFO: [NOCDAPC] D8_APC_0: 0x0
10150 17:16:47.298207 INFO: [NOCDAPC] D8_APC_1: 0xfff
10151 17:16:47.301467 INFO: [NOCDAPC] D9_APC_0: 0x0
10152 17:16:47.305233 INFO: [NOCDAPC] D9_APC_1: 0xfff
10153 17:16:47.308407 INFO: [NOCDAPC] D10_APC_0: 0x0
10154 17:16:47.311787 INFO: [NOCDAPC] D10_APC_1: 0xfff
10155 17:16:47.314837 INFO: [NOCDAPC] D11_APC_0: 0x0
10156 17:16:47.318241 INFO: [NOCDAPC] D11_APC_1: 0xfff
10157 17:16:47.321422 INFO: [NOCDAPC] D12_APC_0: 0x0
10158 17:16:47.325053 INFO: [NOCDAPC] D12_APC_1: 0xfff
10159 17:16:47.328122 INFO: [NOCDAPC] D13_APC_0: 0x0
10160 17:16:47.331268 INFO: [NOCDAPC] D13_APC_1: 0xfff
10161 17:16:47.334314 INFO: [NOCDAPC] D14_APC_0: 0x0
10162 17:16:47.337639 INFO: [NOCDAPC] D14_APC_1: 0xfff
10163 17:16:47.337726 INFO: [NOCDAPC] D15_APC_0: 0x0
10164 17:16:47.341396 INFO: [NOCDAPC] D15_APC_1: 0xfff
10165 17:16:47.344355 INFO: [NOCDAPC] APC_CON: 0x4
10166 17:16:47.347783 INFO: [APUAPC] set_apusys_apc done
10167 17:16:47.350878 INFO: [DEVAPC] devapc_init done
10168 17:16:47.357899 INFO: GICv3 without legacy support detected.
10169 17:16:47.361077 INFO: ARM GICv3 driver initialized in EL3
10170 17:16:47.364161 INFO: Maximum SPI INTID supported: 639
10171 17:16:47.367492 INFO: BL31: Initializing runtime services
10172 17:16:47.373797 WARNING: BL31: cortex_a55: CPU workaround for 1530923 was missing!
10173 17:16:47.377043 INFO: SPM: enable CPC mode
10174 17:16:47.380517 INFO: mcdi ready for mcusys-off-idle and system suspend
10175 17:16:47.386809 INFO: BL31: Preparing for EL3 exit to normal world
10176 17:16:47.389997 INFO: Entry point address = 0x80000000
10177 17:16:47.390084 INFO: SPSR = 0x8
10178 17:16:47.397842
10179 17:16:47.397923
10180 17:16:47.397994
10181 17:16:47.401074 Starting depthcharge on Spherion...
10182 17:16:47.401156
10183 17:16:47.401222 Wipe memory regions:
10184 17:16:47.401283
10185 17:16:47.401825 end: 2.2.3 depthcharge-start (duration 00:00:36) [common]
10186 17:16:47.401938 start: 2.2.4 bootloader-commands (timeout 00:04:24) [common]
10187 17:16:47.402023 Setting prompt string to ['asurada:']
10188 17:16:47.402101 bootloader-commands: Wait for prompt ['asurada:'] (timeout 00:04:24)
10189 17:16:47.403784 [0x00000040000000, 0x00000054600000)
10190 17:16:47.403863
10191 17:16:47.526486 [0x00000054660000, 0x00000080000000)
10192 17:16:47.529588
10193 17:16:47.785841 [0x000000821a7280, 0x000000ffe64000)
10194 17:16:47.789107
10195 17:16:48.530920 [0x00000100000000, 0x00000240000000)
10196 17:16:48.534138
10197 17:16:50.423605 Initializing XHCI USB controller at 0x11200000.
10198 17:16:50.423753
10199 17:16:51.464916 [firmware-asurada-13885.B-collabora] Dec 7 2021 09:38:38
10200 17:16:51.465087
10201 17:16:51.465161
10202 17:16:51.465258
10203 17:16:51.465664 Setting prompt string to ['asurada:', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10205 17:16:51.566479 asurada: tftpboot 192.168.201.1 8082969/tftp-deploy-q1z0x9j0/kernel/image.itb 8082969/tftp-deploy-q1z0x9j0/kernel/cmdline
10206 17:16:51.566631 Setting prompt string to 'jumping to kernel'
10207 17:16:51.566709 Setting prompt string to ['jumping to kernel']
10208 17:16:51.566780 Setting prompt string to ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10209 17:16:51.566857 bootloader-commands: Wait for prompt ['jumping to kernel', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:04:20)
10210 17:16:51.571535 tftpboot 192.168.201.1 8082969/tftp-deploy-q1z0x9j0/kernel/image.ittp-deploy-q1z0x9j0/kernel/cmdline
10211 17:16:51.571623
10212 17:16:51.571692 Waiting for link
10213 17:16:51.571753
10214 17:16:51.731512 R8152: Initializing
10215 17:16:51.731664
10216 17:16:51.734848 Version 6 (ocp_data = 5c30)
10217 17:16:51.734951
10218 17:16:51.738226 R8152: Done initializing
10219 17:16:51.738301
10220 17:16:51.738366 Adding net device
10221 17:16:51.738427
10222 17:16:53.671274 done.
10223 17:16:53.671434
10224 17:16:53.671507 MAC: 00:24:32:30:7c:7b
10225 17:16:53.671573
10226 17:16:53.674336 Sending DHCP discover... done.
10227 17:16:53.674416
10228 17:16:53.677485 Waiting for reply... done.
10229 17:16:53.677564
10230 17:16:53.680711 Sending DHCP request... done.
10231 17:16:53.680789
10232 17:16:53.685851 Waiting for reply... done.
10233 17:16:53.685929
10234 17:16:53.685994 My ip is 192.168.201.14
10235 17:16:53.686054
10236 17:16:53.689101 The DHCP server ip is 192.168.201.1
10237 17:16:53.689181
10238 17:16:53.695841 TFTP server IP predefined by user: 192.168.201.1
10239 17:16:53.695933
10240 17:16:53.702412 Bootfile predefined by user: 8082969/tftp-deploy-q1z0x9j0/kernel/image.itb
10241 17:16:53.702491
10242 17:16:53.706091 Sending tftp read request... done.
10243 17:16:53.706184
10244 17:16:53.709320 Waiting for the transfer...
10245 17:16:53.709397
10246 17:16:54.235559 00000000 ################################################################
10247 17:16:54.235700
10248 17:16:54.757542 00080000 ################################################################
10249 17:16:54.757681
10250 17:16:55.278497 00100000 ################################################################
10251 17:16:55.278645
10252 17:16:55.802168 00180000 ################################################################
10253 17:16:55.802311
10254 17:16:56.422836 00200000 ################################################################
10255 17:16:56.422983
10256 17:16:56.970464 00280000 ################################################################
10257 17:16:56.970599
10258 17:16:57.537670 00300000 ################################################################
10259 17:16:57.537824
10260 17:16:58.112808 00380000 ################################################################
10261 17:16:58.112959
10262 17:16:58.685806 00400000 ################################################################
10263 17:16:58.685945
10264 17:16:59.230419 00480000 ################################################################
10265 17:16:59.230555
10266 17:16:59.788194 00500000 ################################################################
10267 17:16:59.788331
10268 17:17:00.362732 00580000 ################################################################
10269 17:17:00.362868
10270 17:17:00.992875 00600000 ################################################################
10271 17:17:00.993282
10272 17:17:01.660282 00680000 ################################################################
10273 17:17:01.660911
10274 17:17:02.335763 00700000 ################################################################
10275 17:17:02.336305
10276 17:17:02.931127 00780000 ################################################################
10277 17:17:02.931266
10278 17:17:03.520846 00800000 ################################################################
10279 17:17:03.521043
10280 17:17:04.094406 00880000 ################################################################
10281 17:17:04.094543
10282 17:17:04.718031 00900000 ################################################################
10283 17:17:04.718570
10284 17:17:05.357664 00980000 ################################################################
10285 17:17:05.357829
10286 17:17:05.979585 00a00000 ################################################################
10287 17:17:05.980136
10288 17:17:06.693381 00a80000 ################################################################
10289 17:17:06.693535
10290 17:17:07.380754 00b00000 ################################################################
10291 17:17:07.381301
10292 17:17:08.079083 00b80000 ################################################################
10293 17:17:08.079620
10294 17:17:08.754513 00c00000 ################################################################
10295 17:17:08.754652
10296 17:17:09.319427 00c80000 ################################################################
10297 17:17:09.319587
10298 17:17:09.973783 00d00000 ################################################################
10299 17:17:09.973933
10300 17:17:10.662443 00d80000 ################################################################
10301 17:17:10.663073
10302 17:17:11.329673 00e00000 ################################################################
10303 17:17:11.330198
10304 17:17:12.010348 00e80000 ################################################################
10305 17:17:12.010919
10306 17:17:12.641021 00f00000 ################################################################
10307 17:17:12.641179
10308 17:17:13.311187 00f80000 ################################################################
10309 17:17:13.311695
10310 17:17:13.919695 01000000 ################################################################
10311 17:17:13.919836
10312 17:17:15.156012 01080000 ################################################################
10313 17:17:15.156157
10314 17:17:16.089986 01100000 ################################################################
10315 17:17:16.090129
10316 17:17:16.623719 01180000 ################################################################
10317 17:17:16.623859
10318 17:17:17.175887 01200000 ################################################################
10319 17:17:17.176031
10320 17:17:17.743179 01280000 ################################################################
10321 17:17:17.743337
10322 17:17:18.349267 01300000 ################################################################
10323 17:17:18.349436
10324 17:17:18.897074 01380000 ################################################################
10325 17:17:18.897225
10326 17:17:19.433449 01400000 ################################################################
10327 17:17:19.433590
10328 17:17:20.025139 01480000 ################################################################
10329 17:17:20.025276
10330 17:17:20.578761 01500000 ################################################################
10331 17:17:20.578939
10332 17:17:21.122581 01580000 ################################################################
10333 17:17:21.122720
10334 17:17:21.648091 01600000 ################################################################
10335 17:17:21.648238
10336 17:17:22.200477 01680000 ################################################################
10337 17:17:22.200624
10338 17:17:22.763662 01700000 ################################################################
10339 17:17:22.763813
10340 17:17:23.335259 01780000 ################################################################
10341 17:17:23.335402
10342 17:17:23.949527 01800000 ################################################################
10343 17:17:23.949687
10344 17:17:24.512946 01880000 ################################################################
10345 17:17:24.513387
10346 17:17:25.094939 01900000 ################################################################
10347 17:17:25.095083
10348 17:17:25.662327 01980000 ################################################################
10349 17:17:25.662468
10350 17:17:26.238268 01a00000 ################################################################
10351 17:17:26.238423
10352 17:17:26.790058 01a80000 ################################################################
10353 17:17:26.790239
10354 17:17:27.361132 01b00000 ################################################################
10355 17:17:27.361278
10356 17:17:27.931097 01b80000 ################################################################
10357 17:17:27.931239
10358 17:17:28.507702 01c00000 ################################################################
10359 17:17:28.507867
10360 17:17:29.083108 01c80000 ################################################################
10361 17:17:29.083262
10362 17:17:29.680535 01d00000 ################################################################
10363 17:17:29.680674
10364 17:17:30.117035 01d80000 ############################################### done.
10365 17:17:30.117186
10366 17:17:30.120145 The bootfile was 31313859 bytes long.
10367 17:17:30.120235
10368 17:17:30.123389 Sending tftp read request... done.
10369 17:17:30.123485
10370 17:17:30.123561 Waiting for the transfer...
10371 17:17:30.123632
10372 17:17:30.126762 00000000 # done.
10373 17:17:30.126860
10374 17:17:30.132891 Command line loaded dynamically from TFTP file: 8082969/tftp-deploy-q1z0x9j0/kernel/cmdline
10375 17:17:30.132991
10376 17:17:30.146112 The command line is: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10377 17:17:30.146216
10378 17:17:30.146315 Loading FIT.
10379 17:17:30.146406
10380 17:17:30.149335 Image ramdisk-1 has 22225805 bytes.
10381 17:17:30.149433
10382 17:17:30.153302 Image fdt-1 has 46773 bytes.
10383 17:17:30.153401
10384 17:17:30.155823 Image kernel-1 has 9039409 bytes.
10385 17:17:30.155922
10386 17:17:30.165540 Compat preference: google,spherion-rev2-sku1 google,spherion-rev2 google,spherion-sku1 google,spherion
10387 17:17:30.165627
10388 17:17:30.182571 Config conf-1 (default), kernel kernel-1, fdt fdt-1, ramdisk ramdisk-1, compat google,spherion-rev3 google,spherion-rev2 (match) google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192
10389 17:17:30.182751
10390 17:17:30.189253 Choosing best match conf-1 for compat google,spherion-rev2.
10391 17:17:30.189426
10392 17:17:30.195922 Connected to device vid:did:rid of 1ae0:0028:00
10393 17:17:30.196087
10394 17:17:30.206196 tpm_get_response: command 0x17b, return code 0x0
10395 17:17:30.206333
10396 17:17:30.209579 ec_init: CrosEC protocol v3 supported (256, 248)
10397 17:17:30.209695
10398 17:17:30.217243 tpm_cleanup: add release locality here.
10399 17:17:30.217372
10400 17:17:30.217497 Shutting down all USB controllers.
10401 17:17:30.217635
10402 17:17:30.220221 Removing current net device
10403 17:17:30.220361
10404 17:17:30.227457 Exiting depthcharge with code 4 at timestamp: 72047520
10405 17:17:30.227634
10406 17:17:30.230478 LZMA decompressing kernel-1 to 0x821a6718
10407 17:17:30.230667
10408 17:17:30.233663 LZMA decompressing kernel-1 to 0x40000000
10409 17:17:30.233874
10410 17:17:31.361165 jumping to kernel
10411 17:17:31.361310
10412 17:17:31.361964 end: 2.2.4 bootloader-commands (duration 00:00:44) [common]
10413 17:17:31.362114 start: 2.2.5 auto-login-action (timeout 00:03:40) [common]
10414 17:17:31.362232 Setting prompt string to ['Linux version [0-9]']
10415 17:17:31.362419 Setting prompt string to ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}']
10416 17:17:31.362530 auto-login-action: Wait for prompt ['Linux version [0-9]', 'Tftp failed.', 'Dhcp release failed.', 'No space left for ramdisk', 'TFTP failed for ramdisk.', 'Dhcp release failed.', 'Out of space adding TFTP server IP to the command line.', 'No network device.', 'Error code \\d+( \\([\\w\\s]+\\))?\\r\\n', '(Bulk read error(.*)){3}'] (timeout 00:05:00)
10417 17:17:31.444408 [ 0.000000] Booting Linux on physical CPU 0x0000000000 [0x412fd050]
10418 17:17:31.448423 start: 2.2.5.1 login-action (timeout 00:03:40) [common]
10419 17:17:31.448530 The string '/ #' does not look like a typical prompt and could match status messages instead. Please check the job log files and use a prompt string which matches the actual prompt string more closely.
10420 17:17:31.448621 Setting prompt string to ['-+\\[ cut here \\]-+\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '(Unhandled fault.*)\\r\\n', 'Kernel panic - (.*) end Kernel panic', 'Stack:\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '^[^\\n]+WARNING:.*?$', '^[^\\n]+Oops(?: -|:).*?$', '^[^\\n]+BUG:.*?$']
10421 17:17:31.448700 Using line separator: #'\n'#
10422 17:17:31.448762 No login prompt set.
10423 17:17:31.448825 Parsing kernel messages
10424 17:17:31.448882 ['-+\\[ cut here \\]-+\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '(Unhandled fault.*)\\r\\n', 'Kernel panic - (.*) end Kernel panic', 'Stack:\\s+(.*\\s+-+\\[ end trace (\\w*) \\]-+)', '^[^\\n]+WARNING:.*?$', '^[^\\n]+Oops(?: -|:).*?$', '^[^\\n]+BUG:.*?$', '/ #', 'Login timed out', 'Login incorrect']
10425 17:17:31.448981 [login-action] Waiting for messages, (timeout 00:03:40)
10426 17:17:31.467762 [ 0.000000] Linux version 6.1.0-rc6 (KernelCI@build-j93566-arm64-gcc-10-defconfig-arm64-chromebook-6tbsx) (aarch64-linux-gnu-gcc (Debian 10.2.1-6) 10.2.1 20210110, GNU ld (GNU Binutils for Debian) 2.35.2) #1 SMP PREEMPT Tue Nov 22 16:59:36 UTC 2022
10427 17:17:31.470561 [ 0.000000] random: crng init done
10428 17:17:31.477615 [ 0.000000] Machine model: Google Spherion (rev0 - 3)
10429 17:17:31.480727 [ 0.000000] efi: UEFI not found.
10430 17:17:31.487323 [ 0.000000] Reserved memory: created DMA memory pool at 0x0000000050000000, size 41 MiB
10431 17:17:31.493922 [ 0.000000] OF: reserved mem: initialized node scp@50000000, compatible id shared-dma-pool
10432 17:17:31.503993 [ 0.000000] earlycon: mtk8250 at MMIO32 0x0000000011002000 (options '115200n8')
10433 17:17:31.506739 [ 0.000000] printk: bootconsole [mtk8250] enabled
10434 17:17:31.514345 [ 0.000000] NUMA: No NUMA configuration found
10435 17:17:31.521238 [ 0.000000] NUMA: Faking a node at [mem 0x0000000040000000-0x000000023fffffff]
10436 17:17:31.527440 [ 0.000000] NUMA: NODE_DATA [mem 0x23efc8a00-0x23efcafff]
10437 17:17:31.527530 [ 0.000000] Zone ranges:
10438 17:17:31.534708 [ 0.000000] DMA [mem 0x0000000040000000-0x00000000ffffffff]
10439 17:17:31.537903 [ 0.000000] DMA32 empty
10440 17:17:31.544167 [ 0.000000] Normal [mem 0x0000000100000000-0x000000023fffffff]
10441 17:17:31.547156 [ 0.000000] Movable zone start for each node
10442 17:17:31.550463 [ 0.000000] Early memory node ranges
10443 17:17:31.557447 [ 0.000000] node 0: [mem 0x0000000040000000-0x000000004fffffff]
10444 17:17:31.563731 [ 0.000000] node 0: [mem 0x0000000050000000-0x00000000528fffff]
10445 17:17:31.570386 [ 0.000000] node 0: [mem 0x0000000052900000-0x00000000545fffff]
10446 17:17:31.577255 [ 0.000000] node 0: [mem 0x0000000054700000-0x00000000ffdfffff]
10447 17:17:31.583695 [ 0.000000] node 0: [mem 0x0000000100000000-0x000000023fffffff]
10448 17:17:31.589907 [ 0.000000] Initmem setup node 0 [mem 0x0000000040000000-0x000000023fffffff]
10449 17:17:31.646899 [ 0.000000] On node 0, zone DMA: 256 pages in unavailable ranges
10450 17:17:31.653813 [ 0.000000] On node 0, zone Normal: 512 pages in unavailable ranges
10451 17:17:31.660362 [ 0.000000] cma: Reserved 32 MiB at 0x00000000fde00000
10452 17:17:31.663512 [ 0.000000] psci: probing for conduit method from DT.
10453 17:17:31.670035 [ 0.000000] psci: PSCIv1.1 detected in firmware.
10454 17:17:31.673723 [ 0.000000] psci: Using standard PSCI v0.2 function IDs
10455 17:17:31.679844 [ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
10456 17:17:31.683037 [ 0.000000] psci: SMC Calling Convention v1.2
10457 17:17:31.689965 [ 0.000000] percpu: Embedded 20 pages/cpu s44840 r8192 d28888 u81920
10458 17:17:31.693212 [ 0.000000] Detected VIPT I-cache on CPU0
10459 17:17:31.699360 [ 0.000000] CPU features: detected: GIC system register CPU interface
10460 17:17:31.706207 [ 0.000000] CPU features: detected: Virtualization Host Extensions
10461 17:17:31.713310 [ 0.000000] CPU features: kernel page table isolation forced ON by KASLR
10462 17:17:31.719496 [ 0.000000] CPU features: detected: Kernel page table isolation (KPTI)
10463 17:17:31.729600 [ 0.000000] CPU features: detected: Qualcomm erratum 1009, or ARM erratum 1286807, 2441009
10464 17:17:31.735730 [ 0.000000] CPU features: detected: ARM errata 1165522, 1319367, or 1530923
10465 17:17:31.739115 [ 0.000000] alternatives: applying boot alternatives
10466 17:17:31.745908 [ 0.000000] Fallback order for Node 0: 0
10467 17:17:31.752243 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 2063616
10468 17:17:31.755922 [ 0.000000] Policy zone: Normal
10469 17:17:31.765601 [ 0.000000] Kernel command line: console_msg_format=syslog earlycon console=ttyS0,115200n8 root=/dev/ram0 ip=dhcp tftpserverip=192.168.201.1
10470 17:17:31.768820
10471 17:17:31.778512 <5>[ 0.000000] Unknown kernel command line parameters "tftpserverip=192.168.201.1", will be passed to user space.
10472 17:17:31.788703 <6>[ 0.000000] Dentry cache hash table entries: 1048576 (order: 11, 8388608 bytes, linear)
10473 17:17:31.798543 <6>[ 0.000000] Inode-cache hash table entries: 524288 (order: 10, 4194304 bytes, linear)
10474 17:17:31.805267 <6>[ 0.000000] mem auto-init: stack:off, heap alloc:off, heap free:off
10475 17:17:31.808347 <6>[ 0.000000] software IO TLB: area num 8.
10476 17:17:31.865131 <6>[ 0.000000] software IO TLB: mapped [mem 0x00000000f9e00000-0x00000000fde00000] (64MB)
10477 17:17:32.014312 <6>[ 0.000000] Memory: 7959052K/8385536K available (16256K kernel code, 3786K rwdata, 9016K rodata, 7616K init, 610K bss, 393716K reserved, 32768K cma-reserved)
10478 17:17:32.020815 <6>[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
10479 17:17:32.027347 <6>[ 0.000000] rcu: Preemptible hierarchical RCU implementation.
10480 17:17:32.030814 <6>[ 0.000000] rcu: RCU event tracing is enabled.
10481 17:17:32.037055 <6>[ 0.000000] rcu: RCU restricting CPUs from NR_CPUS=256 to nr_cpu_ids=8.
10482 17:17:32.044182 <6>[ 0.000000] Trampoline variant of Tasks RCU enabled.
10483 17:17:32.047643 <6>[ 0.000000] Tracing variant of Tasks RCU enabled.
10484 17:17:32.057047 <6>[ 0.000000] rcu: RCU calculated value of scheduler-enlistment delay is 25 jiffies.
10485 17:17:32.063483 <6>[ 0.000000] rcu: Adjusting geometry for rcu_fanout_leaf=16, nr_cpu_ids=8
10486 17:17:32.070143 <6>[ 0.000000] NR_IRQS: 64, nr_irqs: 64, preallocated irqs: 0
10487 17:17:32.076528 <6>[ 0.000000] GICv3: GIC: Using split EOI/Deactivate mode
10488 17:17:32.080068 <6>[ 0.000000] GICv3: 608 SPIs implemented
10489 17:17:32.083229 <6>[ 0.000000] GICv3: 0 Extended SPIs implemented
10490 17:17:32.089783 <6>[ 0.000000] Root IRQ handler: gic_handle_irq
10491 17:17:32.093335 <6>[ 0.000000] GICv3: GICv3 features: 16 PPIs
10492 17:17:32.099975 <6>[ 0.000000] GICv3: CPU0: found redistributor 0 region 0:0x000000000c040000
10493 17:17:32.112766 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-0[0] { /cpus/cpu@0[0] /cpus/cpu@100[1] /cpus/cpu@200[2] /cpus/cpu@300[3] }
10494 17:17:32.126544 <6>[ 0.000000] GICv3: GIC: PPI partition interrupt-partition-1[1] { /cpus/cpu@400[4] /cpus/cpu@500[5] /cpus/cpu@600[6] /cpus/cpu@700[7] }
10495 17:17:32.132468 <6>[ 0.000000] rcu: srcu_init: Setting srcu_struct sizes based on contention.
10496 17:17:32.140477 <6>[ 0.000000] arch_timer: cp15 timer(s) running at 13.00MHz (phys).
10497 17:17:32.154120 <6>[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x2ff89eacb, max_idle_ns: 440795202429 ns
10498 17:17:32.160377 <6>[ 0.000000] sched_clock: 56 bits at 13MHz, resolution 76ns, wraps every 4398046511101ns
10499 17:17:32.167728 <6>[ 0.009233] Console: colour dummy device 80x25
10500 17:17:32.177247 <6>[ 0.013962] Calibrating delay loop (skipped), value calculated using timer frequency.. 26.00 BogoMIPS (lpj=52000)
10501 17:17:32.183573 <6>[ 0.024404] pid_max: default: 32768 minimum: 301
10502 17:17:32.187369 <6>[ 0.029275] LSM: Security Framework initializing
10503 17:17:32.193682 <6>[ 0.034243] Mount-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10504 17:17:32.203457 <6>[ 0.042055] Mountpoint-cache hash table entries: 16384 (order: 5, 131072 bytes, linear)
10505 17:17:32.213409 <6>[ 0.051474] cblist_init_generic: Setting adjustable number of callback queues.
10506 17:17:32.219478 <6>[ 0.058927] cblist_init_generic: Setting shift to 3 and lim to 1.
10507 17:17:32.222904 <6>[ 0.065265] cblist_init_generic: Setting shift to 3 and lim to 1.
10508 17:17:32.225969
10509 17:17:32.229418 <6>[ 0.071706] rcu: Hierarchical SRCU implementation.
10510 17:17:32.236453 <6>[ 0.076720] rcu: Max phase no-delay instances is 1000.
10511 17:17:32.242591 <6>[ 0.083729] EFI services will not be available.
10512 17:17:32.246026 <6>[ 0.088705] smp: Bringing up secondary CPUs ...
10513 17:17:32.254604 <6>[ 0.093780] Detected VIPT I-cache on CPU1
10514 17:17:32.260460 <6>[ 0.093852] GICv3: CPU1: found redistributor 100 region 0:0x000000000c060000
10515 17:17:32.267871 <6>[ 0.093883] CPU1: Booted secondary processor 0x0000000100 [0x412fd050]
10516 17:17:32.270358 <6>[ 0.094212] Detected VIPT I-cache on CPU2
10517 17:17:32.277201 <6>[ 0.094262] GICv3: CPU2: found redistributor 200 region 0:0x000000000c080000
10518 17:17:32.280489
10519 17:17:32.287437 <6>[ 0.094278] CPU2: Booted secondary processor 0x0000000200 [0x412fd050]
10520 17:17:32.290541 <6>[ 0.094532] Detected VIPT I-cache on CPU3
10521 17:17:32.297033 <6>[ 0.094578] GICv3: CPU3: found redistributor 300 region 0:0x000000000c0a0000
10522 17:17:32.303345 <6>[ 0.094592] CPU3: Booted secondary processor 0x0000000300 [0x412fd050]
10523 17:17:32.310276 <6>[ 0.094892] CPU features: detected: Spectre-v4
10524 17:17:32.313591 <6>[ 0.094898] CPU features: detected: Spectre-BHB
10525 17:17:32.316667 <6>[ 0.094904] Detected PIPT I-cache on CPU4
10526 17:17:32.323372 <6>[ 0.094963] GICv3: CPU4: found redistributor 400 region 0:0x000000000c0c0000
10527 17:17:32.333159 <6>[ 0.094980] CPU4: Booted secondary processor 0x0000000400 [0x414fd0b0]
10528 17:17:32.336368 <6>[ 0.095268] Detected PIPT I-cache on CPU5
10529 17:17:32.343439 <6>[ 0.095331] GICv3: CPU5: found redistributor 500 region 0:0x000000000c0e0000
10530 17:17:32.349266 <6>[ 0.095347] CPU5: Booted secondary processor 0x0000000500 [0x414fd0b0]
10531 17:17:32.353336 <6>[ 0.095626] Detected PIPT I-cache on CPU6
10532 17:17:32.362629 <6>[ 0.095693] GICv3: CPU6: found redistributor 600 region 0:0x000000000c100000
10533 17:17:32.369218 <6>[ 0.095708] CPU6: Booted secondary processor 0x0000000600 [0x414fd0b0]
10534 17:17:32.372424 <6>[ 0.095984] Detected PIPT I-cache on CPU7
10535 17:17:32.379416 <6>[ 0.096049] GICv3: CPU7: found redistributor 700 region 0:0x000000000c120000
10536 17:17:32.385561 <6>[ 0.096064] CPU7: Booted secondary processor 0x0000000700 [0x414fd0b0]
10537 17:17:32.388809 <6>[ 0.096111] smp: Brought up 1 node, 8 CPUs
10538 17:17:32.392492
10539 17:17:32.395799 <6>[ 0.237381] SMP: Total of 8 processors activated.
10540 17:17:32.402138 <6>[ 0.242301] CPU features: detected: 32-bit EL0 Support
10541 17:17:32.408612 <6>[ 0.247698] CPU features: detected: Data cache clean to the PoU not required for I/D coherence
10542 17:17:32.415394 <6>[ 0.256498] CPU features: detected: Common not Private translations
10543 17:17:32.421635 <6>[ 0.262974] CPU features: detected: CRC32 instructions
10544 17:17:32.428009 <6>[ 0.268325] CPU features: detected: RCpc load-acquire (LDAPR)
10545 17:17:32.431673 <6>[ 0.274285] CPU features: detected: LSE atomic instructions
10546 17:17:32.434890
10547 17:17:32.438200 <6>[ 0.280066] CPU features: detected: Privileged Access Never
10548 17:17:32.444693 <6>[ 0.285881] CPU features: detected: RAS Extension Support
10549 17:17:32.451459 <6>[ 0.291489] CPU features: detected: Speculative Store Bypassing Safe (SSBS)
10550 17:17:32.454591 <6>[ 0.298752] CPU: All CPU(s) started at EL2
10551 17:17:32.457865
10552 17:17:32.460874 <6>[ 0.303068] alternatives: applying system-wide alternatives
10553 17:17:32.471585 <6>[ 0.313684] devtmpfs: initialized
10554 17:17:32.483911 <6>[ 0.322443] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
10555 17:17:32.486840
10556 17:17:32.493751 <6>[ 0.332407] futex hash table entries: 2048 (order: 5, 131072 bytes, linear)
10557 17:17:32.500526 <6>[ 0.340423] pinctrl core: initialized pinctrl subsystem
10558 17:17:32.503605 <6>[ 0.347048] DMI not present or invalid.
10559 17:17:32.509915 <6>[ 0.351420] NET: Registered PF_NETLINK/PF_ROUTE protocol family
10560 17:17:32.519869 <6>[ 0.358280] DMA: preallocated 1024 KiB GFP_KERNEL pool for atomic allocations
10561 17:17:32.526723 <6>[ 0.365865] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA pool for atomic allocations
10562 17:17:32.536178 <6>[ 0.374073] DMA: preallocated 1024 KiB GFP_KERNEL|GFP_DMA32 pool for atomic allocations
10563 17:17:32.539332 <6>[ 0.382317] audit: initializing netlink subsys (disabled)
10564 17:17:32.549386 <5>[ 0.388011] audit: type=2000 audit(0.276:1): state=initialized audit_enabled=0 res=1
10565 17:17:32.555800 <6>[ 0.388710] thermal_sys: Registered thermal governor 'step_wise'
10566 17:17:32.562720 <6>[ 0.395979] thermal_sys: Registered thermal governor 'power_allocator'
10567 17:17:32.566094 <6>[ 0.402235] cpuidle: using governor menu
10568 17:17:32.572511 <6>[ 0.413241] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
10569 17:17:32.578995 <6>[ 0.420340] ASID allocator initialised with 32768 entries
10570 17:17:32.585779 <6>[ 0.426866] Serial: AMBA PL011 UART driver
10571 17:17:32.593838 <4>[ 0.435840] Trying to register duplicate clock ID: 134
10572 17:17:32.648641 <6>[ 0.494076] KASLR enabled
10573 17:17:32.662423 <6>[ 0.501226] HugeTLB: registered 1.00 GiB page size, pre-allocated 0 pages
10574 17:17:32.669201 <6>[ 0.508239] HugeTLB: 16380 KiB vmemmap can be freed for a 1.00 GiB page
10575 17:17:32.676188 <6>[ 0.515075] HugeTLB: registered 32.0 MiB page size, pre-allocated 0 pages
10576 17:17:32.682595 <6>[ 0.522078] HugeTLB: 508 KiB vmemmap can be freed for a 32.0 MiB page
10577 17:17:32.688764 <6>[ 0.528738] HugeTLB: registered 2.00 MiB page size, pre-allocated 0 pages
10578 17:17:32.695769 <6>[ 0.535744] HugeTLB: 28 KiB vmemmap can be freed for a 2.00 MiB page
10579 17:17:32.701972 <6>[ 0.542318] HugeTLB: registered 64.0 KiB page size, pre-allocated 0 pages
10580 17:17:32.708431 <6>[ 0.549320] HugeTLB: 0 KiB vmemmap can be freed for a 64.0 KiB page
10581 17:17:32.715152 <6>[ 0.556810] ACPI: Interpreter disabled.
10582 17:17:32.721891 <6>[ 0.562883] iommu: Default domain type: Translated
10583 17:17:32.728184 <6>[ 0.567997] iommu: DMA domain TLB invalidation policy: strict mode
10584 17:17:32.731547 <5>[ 0.574641] SCSI subsystem initialized
10585 17:17:32.738337 <6>[ 0.578802] usbcore: registered new interface driver usbfs
10586 17:17:32.741535 <6>[ 0.584532] usbcore: registered new interface driver hub
10587 17:17:32.744754
10588 17:17:32.748420 <6>[ 0.590081] usbcore: registered new device driver usb
10589 17:17:32.754538 <6>[ 0.596131] pps_core: LinuxPPS API ver. 1 registered
10590 17:17:32.764379 <6>[ 0.601327] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
10591 17:17:32.768016 <6>[ 0.610676] PTP clock support registered
10592 17:17:32.771129 <6>[ 0.614917] EDAC MC: Ver: 3.0.0
10593 17:17:32.777570 <6>[ 0.619493] FPGA manager framework
10594 17:17:32.780715 <6>[ 0.623172] Advanced Linux Sound Architecture Driver Initialized.
10595 17:17:32.783922
10596 17:17:32.787600 <6>[ 0.629923] vgaarb: loaded
10597 17:17:32.793818 <6>[ 0.633071] clocksource: Switched to clocksource arch_sys_counter
10598 17:17:32.797495 <5>[ 0.639507] VFS: Disk quotas dquot_6.6.0
10599 17:17:32.803849 <6>[ 0.643695] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
10600 17:17:32.806858 <6>[ 0.650883] pnp: PnP ACPI: disabled
10601 17:17:32.815775 <6>[ 0.657679] NET: Registered PF_INET protocol family
10602 17:17:32.825509 <6>[ 0.663282] IP idents hash table entries: 131072 (order: 8, 1048576 bytes, linear)
10603 17:17:32.836986 <6>[ 0.675602] tcp_listen_portaddr_hash hash table entries: 4096 (order: 4, 65536 bytes, linear)
10604 17:17:32.847199 <6>[ 0.684416] Table-perturb hash table entries: 65536 (order: 6, 262144 bytes, linear)
10605 17:17:32.853496 <6>[ 0.692386] TCP established hash table entries: 65536 (order: 7, 524288 bytes, linear)
10606 17:17:32.862822 <6>[ 0.701087] TCP bind hash table entries: 65536 (order: 9, 2097152 bytes, linear)
10607 17:17:32.869914 <6>[ 0.710827] TCP: Hash tables configured (established 65536 bind 65536)
10608 17:17:32.876136 <6>[ 0.717688] UDP hash table entries: 4096 (order: 5, 131072 bytes, linear)
10609 17:17:32.886336 <6>[ 0.724887] UDP-Lite hash table entries: 4096 (order: 5, 131072 bytes, linear)
10610 17:17:32.892564 <6>[ 0.732590] NET: Registered PF_UNIX/PF_LOCAL protocol family
10611 17:17:32.899340 <6>[ 0.738679] RPC: Registered named UNIX socket transport module.
10612 17:17:32.902993 <6>[ 0.744829] RPC: Registered udp transport module.
10613 17:17:32.909309 <6>[ 0.749760] RPC: Registered tcp transport module.
10614 17:17:32.915625 <6>[ 0.754692] RPC: Registered tcp NFSv4.1 backchannel transport module.
10615 17:17:32.918798 <6>[ 0.761358] PCI: CLS 0 bytes, default 64
10616 17:17:32.922339 <6>[ 0.765702] Unpacking initramfs...
10617 17:17:32.939306 <6>[ 0.777665] hw perfevents: enabled with armv8_cortex_a55 PMU driver, 7 counters available
10618 17:17:32.948850 <6>[ 0.786330] hw perfevents: enabled with armv8_cortex_a76 PMU driver, 7 counters available
10619 17:17:32.952064 <6>[ 0.795175] kvm [1]: IPA Size Limit: 40 bits
10620 17:17:32.959018 <6>[ 0.799707] kvm [1]: GICv3: no GICV resource entry
10621 17:17:32.962261 <6>[ 0.804730] kvm [1]: disabling GICv2 emulation
10622 17:17:32.968595 <6>[ 0.809416] kvm [1]: GIC system register CPU interface enabled
10623 17:17:32.971716 <6>[ 0.815571] kvm [1]: vgic interrupt IRQ18
10624 17:17:32.978682 <6>[ 0.819926] kvm [1]: VHE mode initialized successfully
10625 17:17:32.985052 <5>[ 0.826333] Initialise system trusted keyrings
10626 17:17:32.992010 <6>[ 0.831144] workingset: timestamp_bits=42 max_order=21 bucket_order=0
10627 17:17:32.998992 <6>[ 0.841168] squashfs: version 4.0 (2009/01/31) Phillip Lougher
10628 17:17:33.005625 <5>[ 0.847560] NFS: Registering the id_resolver key type
10629 17:17:33.009306 <5>[ 0.852863] Key type id_resolver registered
10630 17:17:33.015789 <5>[ 0.857278] Key type id_legacy registered
10631 17:17:33.022534 <6>[ 0.861560] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
10632 17:17:33.028810 <6>[ 0.868483] nfs4flexfilelayout_init: NFSv4 Flexfile Layout Driver Registering...
10633 17:17:33.035166 <6>[ 0.876196] 9p: Installing v9fs 9p2000 file system support
10634 17:17:33.072744 <5>[ 0.914919] Key type asymmetric registered
10635 17:17:33.076361 <5>[ 0.919252] Asymmetric key parser 'x509' registered
10636 17:17:33.085948 <6>[ 0.924396] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 245)
10637 17:17:33.089736 <6>[ 0.932014] io scheduler mq-deadline registered
10638 17:17:33.092847 <6>[ 0.936772] io scheduler kyber registered
10639 17:17:33.110245 <6>[ 0.952378] EINJ: ACPI disabled.
10640 17:17:33.133474 <4>[ 0.968840] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10641 17:17:33.143369 <4>[ 0.979508] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10642 17:17:33.155098 <6>[ 0.997176] Serial: 8250/16550 driver, 4 ports, IRQ sharing enabled
10643 17:17:33.163161 <6>[ 1.005164] printk: console [ttyS0] disabled
10644 17:17:33.191035 <6>[ 1.029811] 11002000.serial: ttyS0 at MMIO 0x11002000 (irq = 254, base_baud = 1625000) is a ST16650V2
10645 17:17:33.197696 <6>[ 1.039286] printk: console [ttyS0] enabled
10646 17:17:33.201492 <6>[ 1.039286] printk: console [ttyS0] enabled
10647 17:17:33.207555 <6>[ 1.048187] printk: bootconsole [mtk8250] disabled
10648 17:17:33.210687 <6>[ 1.048187] printk: bootconsole [mtk8250] disabled
10649 17:17:33.217597 <6>[ 1.059415] SuperH (H)SCI(F) driver initialized
10650 17:17:33.220789 <6>[ 1.064679] msm_serial: driver initialized
10651 17:17:33.229619 <6>[ 1.074511] loop: module loaded
10652 17:17:33.232634
10653 17:17:33.238900 <6>[ 1.080422] vgpu11_sshub: Bringing 400000uV into 575000-575000uV
10654 17:17:33.261832 <4>[ 1.103748] mtk-pmic-keys: Failed to locate of_node [id: -1]
10655 17:17:33.268681 <6>[ 1.110470] megasas: 07.719.03.00-rc1
10656 17:17:33.277902 <6>[ 1.120201] tun: Universal TUN/TAP device driver, 1.6
10657 17:17:33.281190 <6>[ 1.126280] thunder_xcv, ver 1.0
10658 17:17:33.285170 <6>[ 1.129785] thunder_bgx, ver 1.0
10659 17:17:33.288205 <6>[ 1.133278] nicpf, ver 1.0
10660 17:17:33.298684 <6>[ 1.137309] hns3: Hisilicon Ethernet Network Driver for Hip08 Family - version
10661 17:17:33.301721 <6>[ 1.144784] hns3: Copyright (c) 2017 Huawei Corporation.
10662 17:17:33.308683 <6>[ 1.150375] hclge is initializing
10663 17:17:33.311964 <6>[ 1.153976] e1000: Intel(R) PRO/1000 Network Driver
10664 17:17:33.318167 <6>[ 1.159108] e1000: Copyright (c) 1999-2006 Intel Corporation.
10665 17:17:33.324998 <6>[ 1.165135] e1000e: Intel(R) PRO/1000 Network Driver
10666 17:17:33.328153 <6>[ 1.170351] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
10667 17:17:33.334778 <6>[ 1.176549] igb: Intel(R) Gigabit Ethernet Network Driver
10668 17:17:33.341326 <6>[ 1.182202] igb: Copyright (c) 2007-2014 Intel Corporation.
10669 17:17:33.347786 <6>[ 1.188049] igbvf: Intel(R) Gigabit Virtual Function Network Driver
10670 17:17:33.354762 <6>[ 1.194567] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
10671 17:17:33.357672 <6>[ 1.201155] sky2: driver version 1.30
10672 17:17:33.364224 <6>[ 1.206028] VFIO - User Level meta-driver version: 0.3
10673 17:17:33.372243 <6>[ 1.214204] usbcore: registered new interface driver usb-storage
10674 17:17:33.381079 <6>[ 1.223123] mt6397-rtc mt6359-rtc: registered as rtc0
10675 17:17:33.391257 <6>[ 1.228596] mt6397-rtc mt6359-rtc: setting system clock to 2022-11-22T17:17:33 UTC (1669137453)
10676 17:17:33.394267 <6>[ 1.238103] i2c_dev: i2c /dev entries driver
10677 17:17:33.408626 <6>[ 1.247183] mtk-wdt 10007000.watchdog: Watchdog enabled (timeout=31 sec, nowayout=0)
10678 17:17:33.415015 <6>[ 1.257116] sdhci: Secure Digital Host Controller Interface driver
10679 17:17:33.421329 <6>[ 1.263550] sdhci: Copyright(c) Pierre Ossman
10680 17:17:33.428124 <6>[ 1.268929] Synopsys Designware Multimedia Card Interface Driver
10681 17:17:33.434967 <6>[ 1.276037] sdhci-pltfm: SDHCI platform and OF driver helper
10682 17:17:33.441956 <6>[ 1.284061] ledtrig-cpu: registered to indicate activity on CPUs
10683 17:17:33.453119 <6>[ 1.291672] SMCCC: SOC_ID: ID = jep106:0426:8192 Revision = 0x00000000
10684 17:17:33.456401 <6>[ 1.299094] usbcore: registered new interface driver usbhid
10685 17:17:33.459425
10686 17:17:33.462465 <6>[ 1.304925] usbhid: USB HID core driver
10687 17:17:33.469479 <6>[ 1.309219] spi_master spi0: will run message pump with realtime priority
10688 17:17:33.504784 <6>[ 1.340563] input: cros_ec as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input0
10689 17:17:33.525526 <6>[ 1.357402] input: cros_ec_buttons as /devices/platform/soc/11010000.spi/spi_master/spi0/spi0.0/11010000.spi:ec@0:keyboard-controller/input/input1
10690 17:17:33.531838 <6>[ 1.373255] cros-ec-spi spi0.0: Chrome EC device registered
10691 17:17:33.555023 <6>[ 1.396947] NET: Registered PF_PACKET protocol family
10692 17:17:33.561392 <6>[ 1.402498] 9pnet: Installing 9P2000 support
10693 17:17:33.565036 <5>[ 1.407110] Key type dns_resolver registered
10694 17:17:33.568287 <6>[ 1.412350] registered taskstats version 1
10695 17:17:33.574492 <5>[ 1.416782] Loading compiled-in X.509 certificates
10696 17:17:33.605794 <4>[ 1.441437] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10697 17:17:33.615669 <4>[ 1.452209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10698 17:17:33.626394 <6>[ 1.468210] xhci-mtk 11200000.usb: uwk - reg:0x420, version:102
10699 17:17:33.633400 <6>[ 1.475040] xhci-mtk 11200000.usb: xHCI Host Controller
10700 17:17:33.639438 <6>[ 1.480550] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 1
10701 17:17:33.649518 <6>[ 1.488405] xhci-mtk 11200000.usb: hcc params 0x01400f99 hci version 0x110 quirks 0x0000000000210010
10702 17:17:33.656299 <6>[ 1.497835] xhci-mtk 11200000.usb: irq 262, io mem 0x11200000
10703 17:17:33.662868 <6>[ 1.503925] xhci-mtk 11200000.usb: xHCI Host Controller
10704 17:17:33.669898 <6>[ 1.509408] xhci-mtk 11200000.usb: new USB bus registered, assigned bus number 2
10705 17:17:33.676361 <6>[ 1.517073] xhci-mtk 11200000.usb: Host supports USB 3.1 Enhanced SuperSpeed
10706 17:17:33.682625 <6>[ 1.524759] hub 1-0:1.0: USB hub found
10707 17:17:33.685863 <6>[ 1.528782] hub 1-0:1.0: 1 port detected
10708 17:17:33.695786 <6>[ 1.533131] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
10709 17:17:33.699539 <6>[ 1.541739] hub 2-0:1.0: USB hub found
10710 17:17:33.702277 <6>[ 1.545756] hub 2-0:1.0: 1 port detected
10711 17:17:33.728898 <4>[ 1.564148] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10712 17:17:33.738479 <4>[ 1.574854] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10713 17:17:33.765587 <4>[ 1.600584] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10714 17:17:33.774806 <4>[ 1.611339] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10715 17:17:33.867227 <6>[ 1.709227] Freeing initrd memory: 21700K
10716 17:17:34.110165 <6>[ 1.949322] usb 1-1: new high-speed USB device number 2 using xhci-mtk
10717 17:17:34.263430 <6>[ 2.105369] hub 1-1:1.0: USB hub found
10718 17:17:34.266547 <6>[ 2.109727] hub 1-1:1.0: 4 ports detected
10719 17:17:34.281499 <4>[ 2.116957] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10720 17:17:34.291092 <4>[ 2.127649] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10721 17:17:34.391212 <6>[ 2.229691] usb 2-1: new SuperSpeed USB device number 2 using xhci-mtk
10722 17:17:34.417830 <6>[ 2.259643] hub 2-1:1.0: USB hub found
10723 17:17:34.420860 <6>[ 2.264167] hub 2-1:1.0: 3 ports detected
10724 17:17:34.435752 <4>[ 2.271423] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10725 17:17:34.445818 <4>[ 2.282148] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10726 17:17:34.472204 <4>[ 2.307665] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10727 17:17:34.481887 <4>[ 2.318444] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10728 17:17:34.594555 <6>[ 2.433348] usb 1-1.4: new high-speed USB device number 3 using xhci-mtk
10729 17:17:34.727263 <6>[ 2.569277] hub 1-1.4:1.0: USB hub found
10730 17:17:34.730307 <6>[ 2.573931] hub 1-1.4:1.0: 2 ports detected
10731 17:17:34.759620 <4>[ 2.595209] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10732 17:17:34.769638 <4>[ 2.605964] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10733 17:17:34.810684 <6>[ 2.649595] usb 2-1.3: new SuperSpeed USB device number 3 using xhci-mtk
10734 17:17:34.854148 <4>[ 2.690098] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10735 17:17:34.864608 <4>[ 2.700828] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10736 17:17:35.026649 <6>[ 2.865252] usb 1-1.4.1: new high-speed USB device number 4 using xhci-mtk
10737 17:17:35.155200 <4>[ 2.990978] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10738 17:17:35.165380 <4>[ 3.001699] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10739 17:17:35.230523 <6>[ 3.069343] usb 1-1.4.2: new high-speed USB device number 5 using xhci-mtk
10740 17:17:35.361604 <4>[ 3.197228] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10741 17:17:35.371149 <4>[ 3.207932] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10742 17:17:44.010130 <3>[ 11.852563] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10743 17:17:44.016807 <3>[ 11.859221] i2c-mt65xx 11d00000.i2c: cannot get main clock
10744 17:17:44.023390 <3>[ 11.865647] i2c-mt65xx 11d20000.i2c: cannot get main clock
10745 17:17:44.029985 <3>[ 11.872017] i2c-mt65xx 11d21000.i2c: cannot get main clock
10746 17:17:44.036912 <3>[ 11.878399] i2c-mt65xx 11f00000.i2c: cannot get main clock
10747 17:17:44.048542 <6>[ 11.891409] mtk-msdc 11f70000.mmc: Got CD GPIO
10748 17:17:44.058804 <4>[ 11.894835] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10749 17:17:44.068108 <4>[ 11.906839] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10750 17:17:44.076090 <6>[ 11.918594] platform 14001000.mutex: deferred probe pending
10751 17:17:44.082376 <6>[ 11.924443] platform 1401d000.m4u: deferred probe pending
10752 17:17:44.088931 <6>[ 11.930098] platform 11cb0000.i2c: deferred probe pending
10753 17:17:44.092032 <6>[ 11.935750] platform 11d00000.i2c: deferred probe pending
10754 17:17:44.098491 <6>[ 11.941401] platform 11d20000.i2c: deferred probe pending
10755 17:17:44.104977 <6>[ 11.947052] platform 11d21000.i2c: deferred probe pending
10756 17:17:44.111975 <6>[ 11.952703] platform 11f00000.i2c: deferred probe pending
10757 17:17:44.115226 <6>[ 11.958354] platform pwmleds: deferred probe pending
10758 17:17:44.121737 <6>[ 11.963570] platform 14002000.smi: deferred probe pending
10759 17:17:44.128161 <6>[ 11.969221] platform 14003000.larb: deferred probe pending
10760 17:17:44.131401 <6>[ 11.974958] platform 14004000.larb: deferred probe pending
10761 17:17:44.137881 <6>[ 11.980696] platform 1502e000.larb: deferred probe pending
10762 17:17:44.144855 <6>[ 11.986432] platform 1582e000.larb: deferred probe pending
10763 17:17:44.151054 <6>[ 11.992170] platform 1600d000.larb: deferred probe pending
10764 17:17:44.154259 <6>[ 11.997908] platform 1602e000.larb: deferred probe pending
10765 17:17:44.161652 <6>[ 12.003644] platform 17010000.larb: deferred probe pending
10766 17:17:44.167897 <6>[ 12.009381] platform 11f60000.mmc: deferred probe pending
10767 17:17:44.174250 <6>[ 12.015032] platform 1a001000.larb: deferred probe pending
10768 17:17:44.177680 <6>[ 12.020768] platform 1a002000.larb: deferred probe pending
10769 17:17:44.184749 <6>[ 12.026506] platform 1a00f000.larb: deferred probe pending
10770 17:17:44.191218 <6>[ 12.032249] platform 1a010000.larb: deferred probe pending
10771 17:17:44.193804 <6>[ 12.037988] platform 1a011000.larb: deferred probe pending
10772 17:17:44.200783 <6>[ 12.043726] platform 1b00f000.larb: deferred probe pending
10773 17:17:44.207207 <6>[ 12.049464] platform 1b10f000.larb: deferred probe pending
10774 17:17:44.214066 <6>[ 12.055201] platform 1f002000.larb: deferred probe pending
10775 17:17:44.217132 <6>[ 12.060938] platform 11f70000.mmc: deferred probe pending
10776 17:17:44.227461 <6>[ 12.066589] platform 10006000.syscon:power-controller: deferred probe pending
10777 17:17:46.115342 <6>[ 13.961774] ALSA device list:
10778 17:17:46.122789 <6>[ 13.965010] No soundcards found.
10779 17:17:46.133806 <6>[ 13.976694] Freeing unused kernel memory: 7616K
10780 17:17:46.137770 <6>[ 13.981606] Run /init as init process
10781 17:17:46.162357 Starting syslogd: OK
10782 17:17:46.166864 Starting klogd: OK
10783 17:17:46.176442 Running sysctl: OK
10784 17:17:46.182736 Populating /dev using udev: <30>[ 14.027553] udevd[175]: starting version 3.2.9
10785 17:17:46.192102 <27>[ 14.035402] udevd[175]: specified user 'tss' unknown
10786 17:17:46.198944 <27>[ 14.040765] udevd[175]: specified group 'tss' unknown
10787 17:17:46.202128 <30>[ 14.047193] udevd[176]: starting eudev-3.2.9
10788 17:17:46.229228 <27>[ 14.072400] udevd[176]: specified user 'tss' unknown
10789 17:17:46.235530 <27>[ 14.077795] udevd[176]: specified group 'tss' unknown
10790 17:17:46.406707 <6>[ 14.249299] usbcore: registered new interface driver r8152
10791 17:17:46.416760 <6>[ 14.259543] usbcore: registered new interface driver cdc_ether
10792 17:17:46.424742 <6>[ 14.266946] tpm_tis_spi spi1.0: TPM ready IRQ confirmed on attempt 1
10793 17:17:46.432255 <6>[ 14.274477] usbcore: registered new interface driver r8153_ecm
10794 17:17:46.450369 <6>[ 14.293184] tpm_tis_spi spi1.0: 2.0 TPM (device-id 0x28, rev-id 0)
10795 17:17:46.481474 <3>[ 14.313422] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10796 17:17:46.486312 <3>[ 14.322747] i2c-mt65xx 11d00000.i2c: cannot get main clock
10797 17:17:46.489606 <3>[ 14.331068] i2c-mt65xx 11d20000.i2c: cannot get main clock
10798 17:17:46.498585 <6>[ 14.338519] mc: Linux media interface: v0.10
10799 17:17:46.502401 <3>[ 14.339946] i2c-mt65xx 11d21000.i2c: cannot get main clock
10800 17:17:46.506888 <6>[ 14.345386] usb 2-1.3: reset SuperSpeed USB device number 3 using xhci-mtk
10801 17:17:46.513464 <3>[ 14.352623] i2c-mt65xx 11f00000.i2c: cannot get main clock
10802 17:17:46.523010 <6>[ 14.356590] tpm_tis_spi spi1.0: Cr50 firmware version: B2-C:0 RO_A:0.0.11/bc74f7dc RW_A:0.6.30/cr50_v1.9308_B.954-4f0f7
10803 17:17:46.540819 <6>[ 14.380558] mtk-scp 10500000.scp: assigned reserved memory node scp@50000000
10804 17:17:46.547186 <4>[ 14.383085] r8152 2-1.3:1.0: Direct firmware load for rtl_nic/rtl8153a-4.fw failed with error -2
10805 17:17:46.557482 <4>[ 14.397561] r8152 2-1.3:1.0: unable to load firmware patch rtl_nic/rtl8153a-4.fw (-2)
10806 17:17:46.564508 <3>[ 14.399317] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10807 17:17:46.577201 <4>[ 14.406317] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10808 17:17:46.580358 <6>[ 14.408502] mtk-msdc 11f70000.mmc: Got CD GPIO
10809 17:17:46.587555 <6>[ 14.410042] videodev: Linux video capture interface: v2.00
10810 17:17:46.595527 <3>[ 14.413780] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10811 17:17:46.606107 <3>[ 14.413796] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10812 17:17:46.613037 <4>[ 14.424748] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10813 17:17:46.620178 <3>[ 14.429540] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10814 17:17:46.626267 <6>[ 14.434428] remoteproc remoteproc0: scp is available
10815 17:17:46.636638 <4>[ 14.434660] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10816 17:17:46.642660 <6>[ 14.434679] remoteproc remoteproc0: powering up scp
10817 17:17:46.652623 <4>[ 14.434702] remoteproc remoteproc0: Direct firmware load for mediatek/mt8192/scp.img failed with error -2
10818 17:17:46.655850 <3>[ 14.434707] remoteproc remoteproc0: request_firmware failed: -2
10819 17:17:46.662899 <6>[ 14.441668] Bluetooth: Core ver 2.22
10820 17:17:46.669791 <6>[ 14.442716] sbs-battery 0-000b: sbs-battery: battery gas gauge device registered
10821 17:17:46.675518 <3>[ 14.442966] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10822 17:17:46.682534 <6>[ 14.451433] NET: Registered PF_BLUETOOTH protocol family
10823 17:17:46.689711 <3>[ 14.451462] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10824 17:17:46.692714 <6>[ 14.451561] r8152 2-1.3:1.0 eth0: v1.12.13
10825 17:17:46.699055 <3>[ 14.456166] i2c-mt65xx 11d00000.i2c: cannot get main clock
10826 17:17:46.705728 <3>[ 14.457915] i2c-mt65xx 11d20000.i2c: cannot get main clock
10827 17:17:46.709449 <3>[ 14.459213] i2c-mt65xx 11d21000.i2c: cannot get main clock
10828 17:17:46.715530 <3>[ 14.460233] i2c-mt65xx 11f00000.i2c: cannot get main clock
10829 17:17:46.726592 <3>[ 14.461526] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10830 17:17:46.735716 <3>[ 14.461559] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10831 17:17:46.743358 <3>[ 14.461574] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10832 17:17:46.748545 <6>[ 14.469705] Bluetooth: HCI device and connection manager initialized
10833 17:17:46.752223 <6>[ 14.469776] Bluetooth: HCI socket layer initialized
10834 17:17:46.755605 <6>[ 14.472890] mtk-msdc 11f70000.mmc: Got CD GPIO
10835 17:17:46.765921 <6>[ 14.479433] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14005000
10836 17:17:46.775086 <4>[ 14.480532] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10837 17:17:46.785497 <4>[ 14.480761] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10838 17:17:46.794970 <3>[ 14.481511] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@0
10839 17:17:46.801870 <3>[ 14.481578] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10840 17:17:46.811981 <3>[ 14.481589] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10841 17:17:46.818355 <3>[ 14.481598] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10842 17:17:46.827976 <3>[ 14.481659] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10843 17:17:46.834849 <3>[ 14.481669] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10844 17:17:46.844447 <3>[ 14.481679] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10845 17:17:46.851423 <3>[ 14.481690] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10846 17:17:46.857904 <3>[ 14.481699] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10847 17:17:46.867724 <3>[ 14.481730] OF: graph: no port node found in /soc/spi@11010000/ec@0/typec/connector@1
10848 17:17:46.874296 <6>[ 14.485671] Bluetooth: L2CAP socket layer initialized
10849 17:17:46.878246 <3>[ 14.490309] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10850 17:17:46.887594 <6>[ 14.499244] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14006000
10851 17:17:46.894395 <6>[ 14.499283] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14007000
10852 17:17:46.903899 <6>[ 14.499315] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/color@14009000
10853 17:17:46.914129 <6>[ 14.499340] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ccorr@1400a000
10854 17:17:46.920334 <6>[ 14.499370] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/aal@1400b000
10855 17:17:46.930649 <6>[ 14.499401] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/gamma@1400c000
10856 17:17:46.933658 <6>[ 14.500133] Bluetooth: SCO socket layer initialized
10857 17:17:46.940642 <3>[ 14.539301] i2c-mt65xx 11d00000.i2c: cannot get main clock
10858 17:17:46.946978 <6>[ 14.541574] usb 1-1.4.1: Found UVC 1.10 device HD User Facing (04f2:b741)
10859 17:17:46.953459 <3>[ 14.551375] i2c-mt65xx 11d20000.i2c: cannot get main clock
10860 17:17:46.966768 <6>[ 14.555433] input: HD User Facing: HD User Facing as /devices/platform/soc/11200000.usb/usb1/1-1/1-1.4/1-1.4.1/1-1.4.1:1.0/input/input2
10861 17:17:46.973737 <3>[ 14.562139] i2c-mt65xx 11d21000.i2c: cannot get main clock
10862 17:17:46.977090 <6>[ 14.564910] usbcore: registered new interface driver uvcvideo
10863 17:17:46.983208 <3>[ 14.576299] i2c-mt65xx 11f00000.i2c: cannot get main clock
10864 17:17:46.990105 <6>[ 14.581849] usbcore: registered new interface driver btusb
10865 17:17:46.996369 <4>[ 14.586344] sbs-battery 0-000b: I2C adapter does not support I2C_FUNC_SMBUS_READ_BLOCK_DATA.
10866 17:17:46.999594
10867 17:17:47.003302 <4>[ 14.586344] Fallback method does not support PEC.
10868 17:17:47.012753 <3>[ 14.601612] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
10869 17:17:47.016023 <6>[ 14.615338] mtk-msdc 11f70000.mmc: Got CD GPIO
10870 17:17:47.026175 <4>[ 14.615382] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10871 17:17:47.036452 <4>[ 14.615733] mtk-power-controller 10006000.syscon:power-controller: supply domain not found, using dummy regulator
10872 17:17:47.045826 <6>[ 14.619474] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14005000
10873 17:17:47.056042 <6>[ 14.619533] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ovl@14006000
10874 17:17:47.062240 <6>[ 14.619565] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/rdma@14007000
10875 17:17:47.072445 <6>[ 14.619597] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/color@14009000
10876 17:17:47.078839 <6>[ 14.619620] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/ccorr@1400a000
10877 17:17:47.088946 <6>[ 14.619651] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/aal@1400b000
10878 17:17:47.099023 <6>[ 14.619681] mediatek-drm mediatek-drm.9.auto: Adding component match for /soc/gamma@1400c000
10879 17:17:47.102200 <3>[ 14.620342] i2c-mt65xx 11cb0000.i2c: cannot get main clock
10880 17:17:47.108476 <3>[ 14.621033] i2c-mt65xx 11d00000.i2c: cannot get main clock
10881 17:17:47.115473 <3>[ 14.621757] i2c-mt65xx 11d20000.i2c: cannot get main clock
10882 17:17:47.121698 <3>[ 14.622396] i2c-mt65xx 11d21000.i2c: cannot get main clock
10883 17:17:47.125100 <3>[ 14.623020] i2c-mt65xx 11f00000.i2c: cannot get main clock
10884 17:17:47.141231 <3>[ 14.981283] power_supply sbs-0-000b: driver failed to report `time_to_empty_now' property: -5
10885 17:17:47.163698 done
10886 17:17:47.171979 Saving random seed: OK
10887 17:17:47.187867 Starting network: OK
10888 17:17:47.227075 Starting dropbear sshd: <6>[ 15.068726] NET: Registered PF_INET6 protocol family
10889 17:17:47.232315 <6>[ 15.075617] Segment Routing with IPv6
10890 17:17:47.237386 <6>[ 15.079570] In-situ OAM (IOAM) with IPv6
10891 17:17:47.242653 OK
10892 17:17:47.250900 /bin/sh: can't access tty; job control turned off
10893 17:17:47.253781 Matched prompt #7: / #
10895 17:17:47.254457 Setting prompt string to ['/ #']
10896 17:17:47.254768 end: 2.2.5.1 login-action (duration 00:00:16) [common]
10898 17:17:47.255433 end: 2.2.5 auto-login-action (duration 00:00:16) [common]
10899 17:17:47.255733 start: 2.2.6 expect-shell-connection (timeout 00:03:24) [common]
10900 17:17:47.255955 Setting prompt string to ['/ #']
10901 17:17:47.256175 Forcing a shell prompt, looking for ['/ #']
10903 17:17:47.307042 / #
10904 17:17:47.307677 expect-shell-connection: Wait for prompt ['/ #'] (timeout 00:05:00)
10905 17:17:47.308215 Waiting using forced prompt support (timeout 00:02:30)
10906 17:17:47.313795
10907 17:17:47.314723 end: 2.2.6 expect-shell-connection (duration 00:00:00) [common]
10908 17:17:47.315338 start: 2.2.7 export-device-env (timeout 00:03:24) [common]
10909 17:17:47.315897 end: 2.2.7 export-device-env (duration 00:00:00) [common]
10910 17:17:47.316438 end: 2.2 depthcharge-retry (duration 00:01:36) [common]
10911 17:17:47.317019 end: 2 depthcharge-action (duration 00:01:36) [common]
10912 17:17:47.318229 start: 3 lava-test-retry (timeout 00:01:00) [common]
10913 17:17:47.318789 start: 3.1 lava-test-shell (timeout 00:01:00) [common]
10914 17:17:47.319252 Using namespace: common
10916 17:17:47.420910 / # #
10917 17:17:47.421579 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10918 17:17:47.427569 #
10919 17:17:47.428384 Using /lava-8082969
10921 17:17:47.529994 / # export SHELL=/bin/sh
10922 17:17:47.536366 export SHELL=/bin/sh
10924 17:17:47.638313 / # . /lava-8082969/environment
10925 17:17:47.645444 . /lava-8082969/environment
10927 17:17:47.747556 / # /lava-8082969/bin/lava-test-runner /lava-8082969/0
10928 17:17:47.748226 Test shell timeout: 10s (minimum of the action and connection timeout)
10929 17:17:47.753894 /lava-8082969/bin/lava-test-runner /lava-8082969/0
10930 17:17:47.772010 + export 'TESTRUN_ID=0_dmesg'
10931 17:17:47.778332 +<8>[ 15.620224] <LAVA_SIGNAL_STARTRUN 0_dmesg 8082969_1.5.2.3.1>
10932 17:17:47.779044 Received signal: <STARTRUN> 0_dmesg 8082969_1.5.2.3.1
10933 17:17:47.779457 Starting test lava.0_dmesg (8082969_1.5.2.3.1)
10934 17:17:47.779995 Skipping test definition patterns.
10935 17:17:47.781579 cd /lava-8082969/0/tests/0_dmesg
10936 17:17:47.782025 + cat uuid
10937 17:17:47.784775 + UUID=8082969_1.5.2.3.1
10938 17:17:47.785174 + set +x
10939 17:17:47.791878 + KERNELCI_LAVA=y /bin/sh /opt/kernelci/dmesg.sh
10940 17:17:47.801312 <8>[ 15.640236] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0>
10941 17:17:47.802114 Received signal: <TESTCASE> TEST_CASE_ID=crit RESULT=pass UNITS=lines MEASUREMENT=0
10943 17:17:47.820984 <8>[ 15.661093] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0>
10944 17:17:47.821784 Received signal: <TESTCASE> TEST_CASE_ID=alert RESULT=pass UNITS=lines MEASUREMENT=0
10946 17:17:47.841462 <8>[ 15.681455] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0>
10947 17:17:47.842331 Received signal: <TESTCASE> TEST_CASE_ID=emerg RESULT=pass UNITS=lines MEASUREMENT=0
10949 17:17:47.845063 + set +x
10950 17:17:47.847588 <8>[ 15.690921] <LAVA_SIGNAL_ENDRUN 0_dmesg 8082969_1.5.2.3.1>
10951 17:17:47.848285 Received signal: <ENDRUN> 0_dmesg 8082969_1.5.2.3.1
10952 17:17:47.848749 Ending use of test pattern.
10953 17:17:47.849157 Ending test lava.0_dmesg (8082969_1.5.2.3.1), duration 0.07
10955 17:17:47.851997 <LAVA_TEST_RUNNER EXIT>
10956 17:17:47.852689 ok: lava_test_shell seems to have completed
10957 17:17:47.853389 alert: pass
crit: pass
emerg: pass
10958 17:17:47.853940 end: 3.1 lava-test-shell (duration 00:00:01) [common]
10959 17:17:47.854461 end: 3 lava-test-retry (duration 00:00:01) [common]
10960 17:17:47.855015 start: 4 lava-test-retry (timeout 00:01:00) [common]
10961 17:17:47.855557 start: 4.1 lava-test-shell (timeout 00:01:00) [common]
10962 17:17:47.855953 Using namespace: common
10964 17:17:47.957696 / # #
10965 17:17:47.958411 lava-test-shell: Wait for prompt ['/ #'] (timeout 00:01:00)
10966 17:17:47.959181 Using /lava-8082969
10968 17:17:48.060932 export SHELL=/bin/sh
10969 17:17:48.061839 #
10971 17:17:48.163729 / # export SHELL=/bin/sh. /lava-8082969/environment
10972 17:17:48.164639
10974 17:17:48.266614 / # . /lava-8082969/environment/lava-8082969/bin/lava-test-runner /lava-8082969/1
10975 17:17:48.267274 Test shell timeout: 10s (minimum of the action and connection timeout)
10976 17:17:48.267996
10977 17:17:48.273123 / # /lava-8082969/bin/lava-test-runner /lava-8082969/1
10978 17:17:48.291208 + export 'TESTRUN_ID=1_bootrr'
10979 17:17:48.297191 <8>[ 16.139106] <LAVA_SIGNAL_STARTRUN 1_bootrr 8082969_1.5.2.3.5>
10980 17:17:48.297994 Received signal: <STARTRUN> 1_bootrr 8082969_1.5.2.3.5
10981 17:17:48.298399 Starting test lava.1_bootrr (8082969_1.5.2.3.5)
10982 17:17:48.298952 Skipping test definition patterns.
10983 17:17:48.301189 + cd /lava-8082969/1/tests/1_bootrr
10984 17:17:48.301747 + cat uuid
10985 17:17:48.304272 + UUID=8082969_1.5.2.3.5
10986 17:17:48.304763 + set +x
10987 17:17:48.313818 + export 'PATH=/opt/bootrr/helpers:/lava-8082969/1/../bin:/sbin:/usr/sbin:/bin:/usr/bin'
10988 17:17:48.314366 + cd /opt/bootrr
10989 17:17:48.317095 + sh helpers/bootrr-auto
10990 17:17:48.742279 <3>[ 16.585341] Bluetooth: hci0: Opcode 0x c03 failed: -110
10991 17:17:49.308862 /lava-8082969/1/../bin/lava-test-case
10992 17:17:49.311852
10993 17:17:49.317973 <8>[ 17.159060] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=deferred-probe-empty RESULT=pass>
10994 17:17:49.318234 Received signal: <TESTCASE> TEST_CASE_ID=deferred-probe-empty RESULT=pass
10996 17:17:49.330043 /lava-8082969/1/../bin/lava-test-case
10997 17:17:49.336524 <8>[ 17.177778] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=all-cpus-are-online RESULT=pass>
10998 17:17:49.336797 Received signal: <TESTCASE> TEST_CASE_ID=all-cpus-are-online RESULT=pass
11000 17:17:49.341579 /usr/bin/tpm2_getcap
11001 17:17:49.372478 TPM2_CC_NV_UndefineSpaceSpecial:
11002 17:17:49.375495 value: 0x440011F
11003 17:17:49.375959 commandIndex: 0x11f
11004 17:17:49.378361
11005 17:17:49.378833 reserved1: 0x0
11006 17:17:49.382189 nv: 1
11007 17:17:49.382633 extensive: 0
11008 17:17:49.385583 flushed: 0
11009 17:17:49.386027 cHandles: 0x2
11010 17:17:49.388775 rHandle: 0
11011 17:17:49.389195 V: 0
11012 17:17:49.391895 Res: 0x0
11013 17:17:49.392369 TPM2_CC_EvictControl:
11014 17:17:49.394808 value: 0x4400120
11015 17:17:49.394948 commandIndex: 0x120
11016 17:17:49.398410 reserved1: 0x0
11017 17:17:49.398496 nv: 1
11018 17:17:49.401597 extensive: 0
11019 17:17:49.401685 flushed: 0
11020 17:17:49.404849 cHandles: 0x2
11021 17:17:49.404937 rHandle: 0
11022 17:17:49.407849
11023 17:17:49.407932 V: 0
11024 17:17:49.411731 Res: 0x0
11025 17:17:49.411807 TPM2_CC_HierarchyControl:
11026 17:17:49.414811 value: 0x2C00121
11027 17:17:49.414914 commandIndex: 0x121
11028 17:17:49.418031 reserved1: 0x0
11029 17:17:49.418105 nv: 1
11030 17:17:49.421360 extensive: 1
11031 17:17:49.421436 flushed: 0
11032 17:17:49.424681 cHandles: 0x1
11033 17:17:49.424753 rHandle: 0
11034 17:17:49.427600
11035 17:17:49.427671 V: 0
11036 17:17:49.431354 Res: 0x0
11037 17:17:49.431427 TPM2_CC_NV_UndefineSpace:
11038 17:17:49.434399 value: 0x4400122
11039 17:17:49.434476 commandIndex: 0x122
11040 17:17:49.438111 reserved1: 0x0
11041 17:17:49.438185 nv: 1
11042 17:17:49.441241 extensive: 0
11043 17:17:49.441320 flushed: 0
11044 17:17:49.444429 cHandles: 0x2
11045 17:17:49.444502 rHandle: 0
11046 17:17:49.447548
11047 17:17:49.447619 V: 0
11048 17:17:49.450780 Res: 0x0
11049 17:17:49.450851 TPM2_CC_Clear:
11050 17:17:49.450940 value: 0x2C00126
11051 17:17:49.454134
11052 17:17:49.454212 commandIndex: 0x126
11053 17:17:49.457362 reserved1: 0x0
11054 17:17:49.457439 nv: 1
11055 17:17:49.461244 extensive: 1
11056 17:17:49.461321 flushed: 0
11057 17:17:49.464479 cHandles: 0x1
11058 17:17:49.464551 rHandle: 0
11059 17:17:49.467664 V: 0
11060 17:17:49.467738 Res: 0x0
11061 17:17:49.470805 TPM2_CC_ClearControl:
11062 17:17:49.470927 value: 0x2400127
11063 17:17:49.473989 commandIndex: 0x127
11064 17:17:49.477806 reserved1: 0x0
11065 17:17:49.477886 nv: 1
11066 17:17:49.480575 extensive: 0
11067 17:17:49.480650 flushed: 0
11068 17:17:49.484157 cHandles: 0x1
11069 17:17:49.484233 rHandle: 0
11070 17:17:49.487421 V: 0
11071 17:17:49.487493 Res: 0x0
11072 17:17:49.490626 TPM2_CC_ClockSet:
11073 17:17:49.490700 value: 0x2400128
11074 17:17:49.493850 commandIndex: 0x128
11075 17:17:49.493924 reserved1: 0x0
11076 17:17:49.497118 nv: 1
11077 17:17:49.497192 extensive: 0
11078 17:17:49.500312 flushed: 0
11079 17:17:49.500393 cHandles: 0x1
11080 17:17:49.504107 rHandle: 0
11081 17:17:49.504181 V: 0
11082 17:17:49.507101 Res: 0x0
11083 17:17:49.510265 TPM2_CC_HierarchyChangeAuth:
11084 17:17:49.510344 value: 0x2400129
11085 17:17:49.513652 commandIndex: 0x129
11086 17:17:49.513727 reserved1: 0x0
11087 17:17:49.517371 nv: 1
11088 17:17:49.517445 extensive: 0
11089 17:17:49.520578 flushed: 0
11090 17:17:49.520654 cHandles: 0x1
11091 17:17:49.523819 rHandle: 0
11092 17:17:49.523892 V: 0
11093 17:17:49.526972 Res: 0x0
11094 17:17:49.530229 TPM2_CC_NV_DefineSpace:
11095 17:17:49.530301 value: 0x240012A
11096 17:17:49.533489 commandIndex: 0x12a
11097 17:17:49.533563 reserved1: 0x0
11098 17:17:49.536712 nv: 1
11099 17:17:49.536787 extensive: 0
11100 17:17:49.539843 flushed: 0
11101 17:17:49.539916 cHandles: 0x1
11102 17:17:49.543430 rHandle: 0
11103 17:17:49.543503 V: 0
11104 17:17:49.546637 Res: 0x0
11105 17:17:49.549899 TPM2_CC_PCR_Allocate:
11106 17:17:49.549972 value: 0x240012B
11107 17:17:49.553122 commandIndex: 0x12b
11108 17:17:49.553199 reserved1: 0x0
11109 17:17:49.556857 nv: 1
11110 17:17:49.556933 extensive: 0
11111 17:17:49.560010 flushed: 0
11112 17:17:49.560087 cHandles: 0x1
11113 17:17:49.563206 rHandle: 0
11114 17:17:49.563280 V: 0
11115 17:17:49.566450 Res: 0x0
11116 17:17:49.569612 TPM2_CC_SetPrimaryPolicy:
11117 17:17:49.569690 value: 0x240012E
11118 17:17:49.572737 commandIndex: 0x12e
11119 17:17:49.572810 reserved1: 0x0
11120 17:17:49.576688 nv: 1
11121 17:17:49.576761 extensive: 0
11122 17:17:49.579896 flushed: 0
11123 17:17:49.579968 cHandles: 0x1
11124 17:17:49.582700 rHandle: 0
11125 17:17:49.582774 V: 0
11126 17:17:49.586787 Res: 0x0
11127 17:17:49.589153 TPM2_CC_ClockRateAdjust:
11128 17:17:49.589236 value: 0x2000130
11129 17:17:49.592989 commandIndex: 0x130
11130 17:17:49.593063 reserved1: 0x0
11131 17:17:49.596231 nv: 0
11132 17:17:49.596305 extensive: 0
11133 17:17:49.599290 flushed: 0
11134 17:17:49.599367 cHandles: 0x1
11135 17:17:49.602679 rHandle: 0
11136 17:17:49.602751 V: 0
11137 17:17:49.605757 Res: 0x0
11138 17:17:49.605847 TPM2_CC_CreatePrimary:
11139 17:17:49.610044
11140 17:17:49.610484 value: 0x12000131
11141 17:17:49.613224 commandIndex: 0x131
11142 17:17:49.613682 reserved1: 0x0
11143 17:17:49.616429 nv: 0
11144 17:17:49.616865 extensive: 0
11145 17:17:49.619572 flushed: 0
11146 17:17:49.620008 cHandles: 0x1
11147 17:17:49.622641 rHandle: 1
11148 17:17:49.623114 V: 0
11149 17:17:49.625823 Res: 0x0
11150 17:17:49.626281 TPM2_CC_NV_Increment:
11151 17:17:49.629132 value: 0x4400134
11152 17:17:49.632843 commandIndex: 0x134
11153 17:17:49.633351 reserved1: 0x0
11154 17:17:49.636025 nv: 1
11155 17:17:49.636530 extensive: 0
11156 17:17:49.639195 flushed: 0
11157 17:17:49.639683 cHandles: 0x2
11158 17:17:49.642419 rHandle: 0
11159 17:17:49.642866 V: 0
11160 17:17:49.646064 Res: 0x0
11161 17:17:49.646502 TPM2_CC_NV_SetBits:
11162 17:17:49.649242 value: 0x4400135
11163 17:17:49.649680 commandIndex: 0x135
11164 17:17:49.652363 reserved1: 0x0
11165 17:17:49.652930 nv: 1
11166 17:17:49.656047 extensive: 0
11167 17:17:49.656477 flushed: 0
11168 17:17:49.659156 cHandles: 0x2
11169 17:17:49.659583 rHandle: 0
11170 17:17:49.662465
11171 17:17:49.663007 V: 0
11172 17:17:49.665796 Res: 0x0
11173 17:17:49.666329 TPM2_CC_NV_Extend:
11174 17:17:49.668725 value: 0x4400136
11175 17:17:49.669153 commandIndex: 0x136
11176 17:17:49.672033 reserved1: 0x0
11177 17:17:49.672462 nv: 1
11178 17:17:49.675560 extensive: 0
11179 17:17:49.675987 flushed: 0
11180 17:17:49.678699 cHandles: 0x2
11181 17:17:49.679160 rHandle: 0
11182 17:17:49.682708 V: 0
11183 17:17:49.683287 Res: 0x0
11184 17:17:49.685575 TPM2_CC_NV_Write:
11185 17:17:49.686006 value: 0x4400137
11186 17:17:49.688806 commandIndex: 0x137
11187 17:17:49.691936 reserved1: 0x0
11188 17:17:49.692437 nv: 1
11189 17:17:49.695209 extensive: 0
11190 17:17:49.695645 flushed: 0
11191 17:17:49.698368 cHandles: 0x2
11192 17:17:49.698821 rHandle: 0
11193 17:17:49.702137 V: 0
11194 17:17:49.702572 Res: 0x0
11195 17:17:49.705347 TPM2_CC_NV_WriteLock:
11196 17:17:49.705788 value: 0x4400138
11197 17:17:49.708407 commandIndex: 0x138
11198 17:17:49.708846 reserved1: 0x0
11199 17:17:49.712339 nv: 1
11200 17:17:49.712774 extensive: 0
11201 17:17:49.715403 flushed: 0
11202 17:17:49.715890 cHandles: 0x2
11203 17:17:49.718733
11204 17:17:49.719328 rHandle: 0
11205 17:17:49.719717 V: 0
11206 17:17:49.721765
11207 17:17:49.722202 Res: 0x0
11208 17:17:49.725085 TPM2_CC_DictionaryAttackLockReset:
11209 17:17:49.728237 value: 0x2400139
11210 17:17:49.728774 commandIndex: 0x139
11211 17:17:49.731781 reserved1: 0x0
11212 17:17:49.732218 nv: 1
11213 17:17:49.734934 extensive: 0
11214 17:17:49.735380 flushed: 0
11215 17:17:49.738369 cHandles: 0x1
11216 17:17:49.738942 rHandle: 0
11217 17:17:49.742170 V: 0
11218 17:17:49.742714 Res: 0x0
11219 17:17:49.745062 TPM2_CC_DictionaryAttackParameters:
11220 17:17:49.748483 value: 0x240013A
11221 17:17:49.749020 commandIndex: 0x13a
11222 17:17:49.751713 reserved1: 0x0
11223 17:17:49.752395 nv: 1
11224 17:17:49.754665 extensive: 0
11225 17:17:49.755153 flushed: 0
11226 17:17:49.758328 cHandles: 0x1
11227 17:17:49.758764 rHandle: 0
11228 17:17:49.761808
11229 17:17:49.762338 V: 0
11230 17:17:49.764780 Res: 0x0
11231 17:17:49.765360 TPM2_CC_NV_ChangeAuth:
11232 17:17:49.767814 value: 0x240013B
11233 17:17:49.768257 commandIndex: 0x13b
11234 17:17:49.771022 reserved1: 0x0
11235 17:17:49.771461 nv: 1
11236 17:17:49.775236 extensive: 0
11237 17:17:49.775770 flushed: 0
11238 17:17:49.778012 cHandles: 0x1
11239 17:17:49.778459 rHandle: 0
11240 17:17:49.781065 V: 0
11241 17:17:49.781499 Res: 0x0
11242 17:17:49.784134 TPM2_CC_PCR_Event:
11243 17:17:49.787374 value: 0x240013C
11244 17:17:49.787800 commandIndex: 0x13c
11245 17:17:49.791064 reserved1: 0x0
11246 17:17:49.791603 nv: 1
11247 17:17:49.794297 extensive: 0
11248 17:17:49.794836 flushed: 0
11249 17:17:49.797355 cHandles: 0x1
11250 17:17:49.797814 rHandle: 0
11251 17:17:49.801126 V: 0
11252 17:17:49.801554 Res: 0x0
11253 17:17:49.804192 TPM2_CC_PCR_Reset:
11254 17:17:49.804628 value: 0x240013D
11255 17:17:49.807229 commandIndex: 0x13d
11256 17:17:49.807653 reserved1: 0x0
11257 17:17:49.811122
11258 17:17:49.811659 nv: 1
11259 17:17:49.812042 extensive: 0
11260 17:17:49.814325
11261 17:17:49.814870 flushed: 0
11262 17:17:49.817316 cHandles: 0x1
11263 17:17:49.817744 rHandle: 0
11264 17:17:49.820437 V: 0
11265 17:17:49.820906 Res: 0x0
11266 17:17:49.824247 TPM2_CC_SequenceComplete:
11267 17:17:49.824679 value: 0x300013E
11268 17:17:49.827467 commandIndex: 0x13e
11269 17:17:49.827896 reserved1: 0x0
11270 17:17:49.830630
11271 17:17:49.831088 nv: 0
11272 17:17:49.831430 extensive: 0
11273 17:17:49.833737
11274 17:17:49.834167 flushed: 1
11275 17:17:49.837418 cHandles: 0x1
11276 17:17:49.837952 rHandle: 0
11277 17:17:49.840400 V: 0
11278 17:17:49.840954 Res: 0x0
11279 17:17:49.843729 TPM2_CC_IncrementalSelfTest:
11280 17:17:49.844162 value: 0x400142
11281 17:17:49.846780 commandIndex: 0x142
11282 17:17:49.850845 reserved1: 0x0
11283 17:17:49.851412 nv: 1
11284 17:17:49.853724 extensive: 0
11285 17:17:49.854154 flushed: 0
11286 17:17:49.856957 cHandles: 0x0
11287 17:17:49.857503 rHandle: 0
11288 17:17:49.860016 V: 0
11289 17:17:49.860445 Res: 0x0
11290 17:17:49.863349 TPM2_CC_SelfTest:
11291 17:17:49.863779 value: 0x400143
11292 17:17:49.867077 commandIndex: 0x143
11293 17:17:49.867508 reserved1: 0x0
11294 17:17:49.870374 nv: 1
11295 17:17:49.870820 extensive: 0
11296 17:17:49.873449 flushed: 0
11297 17:17:49.873879 cHandles: 0x0
11298 17:17:49.876927 rHandle: 0
11299 17:17:49.877472 V: 0
11300 17:17:49.880344 Res: 0x0
11301 17:17:49.880775 TPM2_CC_Startup:
11302 17:17:49.883445 value: 0x400144
11303 17:17:49.883896 commandIndex: 0x144
11304 17:17:49.886483
11305 17:17:49.886936 reserved1: 0x0
11306 17:17:49.889891 nv: 1
11307 17:17:49.890423 extensive: 0
11308 17:17:49.893628 flushed: 0
11309 17:17:49.894255 cHandles: 0x0
11310 17:17:49.896689 rHandle: 0
11311 17:17:49.897219 V: 0
11312 17:17:49.899677 Res: 0x0
11313 17:17:49.900108 TPM2_CC_Shutdown:
11314 17:17:49.902861 value: 0x400145
11315 17:17:49.903340 commandIndex: 0x145
11316 17:17:49.906548 reserved1: 0x0
11317 17:17:49.907011 nv: 1
11318 17:17:49.909907 extensive: 0
11319 17:17:49.910389 flushed: 0
11320 17:17:49.913082 cHandles: 0x0
11321 17:17:49.913546 rHandle: 0
11322 17:17:49.916279 V: 0
11323 17:17:49.916706 Res: 0x0
11324 17:17:49.919479 TPM2_CC_StirRandom:
11325 17:17:49.919911 value: 0x400146
11326 17:17:49.923603 commandIndex: 0x146
11327 17:17:49.926345 reserved1: 0x0
11328 17:17:49.926776 nv: 1
11329 17:17:49.929826 extensive: 0
11330 17:17:49.930362 flushed: 0
11331 17:17:49.932926 cHandles: 0x0
11332 17:17:49.933461 rHandle: 0
11333 17:17:49.935908 V: 0
11334 17:17:49.936336 Res: 0x0
11335 17:17:49.939733 TPM2_CC_ActivateCredential:
11336 17:17:49.943025 value: 0x4000147
11337 17:17:49.943523 commandIndex: 0x147
11338 17:17:49.946202 reserved1: 0x0
11339 17:17:49.946632 nv: 0
11340 17:17:49.949346 extensive: 0
11341 17:17:49.949922 flushed: 0
11342 17:17:49.952307 cHandles: 0x2
11343 17:17:49.952881 rHandle: 0
11344 17:17:49.955414 V: 0
11345 17:17:49.955843 Res: 0x0
11346 17:17:49.959310 TPM2_CC_Certify:
11347 17:17:49.959883 value: 0x4000148
11348 17:17:49.962447 commandIndex: 0x148
11349 17:17:49.962875 reserved1: 0x0
11350 17:17:49.965998 nv: 0
11351 17:17:49.966529 extensive: 0
11352 17:17:49.969282 flushed: 0
11353 17:17:49.969728 cHandles: 0x2
11354 17:17:49.972788
11355 17:17:49.973327 rHandle: 0
11356 17:17:49.973671 V: 0
11357 17:17:49.975539
11358 17:17:49.975976 Res: 0x0
11359 17:17:49.978731 TPM2_CC_PolicyNV:
11360 17:17:49.979193 value: 0x6000149
11361 17:17:49.982465 commandIndex: 0x149
11362 17:17:49.982926 reserved1: 0x0
11363 17:17:49.985622 nv: 0
11364 17:17:49.986052 extensive: 0
11365 17:17:49.988578 flushed: 0
11366 17:17:49.989003 cHandles: 0x3
11367 17:17:49.992381 rHandle: 0
11368 17:17:49.992805 V: 0
11369 17:17:49.995568 Res: 0x0
11370 17:17:49.998748 TPM2_CC_CertifyCreation:
11371 17:17:49.999196 value: 0x400014A
11372 17:17:50.001872 commandIndex: 0x14a
11373 17:17:50.002303 reserved1: 0x0
11374 17:17:50.005083 nv: 0
11375 17:17:50.005538 extensive: 0
11376 17:17:50.008867 flushed: 0
11377 17:17:50.009299 cHandles: 0x2
11378 17:17:50.012404 rHandle: 0
11379 17:17:50.012941 V: 0
11380 17:17:50.015079 Res: 0x0
11381 17:17:50.015552 TPM2_CC_Duplicate:
11382 17:17:50.018729 value: 0x400014B
11383 17:17:50.019191 commandIndex: 0x14b
11384 17:17:50.022223 reserved1: 0x0
11385 17:17:50.025194 nv: 0
11386 17:17:50.025766 extensive: 0
11387 17:17:50.028207 flushed: 0
11388 17:17:50.028636 cHandles: 0x2
11389 17:17:50.032269 rHandle: 0
11390 17:17:50.032801 V: 0
11391 17:17:50.035312 Res: 0x0
11392 17:17:50.035759 TPM2_CC_GetTime:
11393 17:17:50.038529 value: 0x400014C
11394 17:17:50.039098 commandIndex: 0x14c
11395 17:17:50.041857 reserved1: 0x0
11396 17:17:50.042499 nv: 0
11397 17:17:50.044782 extensive: 0
11398 17:17:50.045229 flushed: 0
11399 17:17:50.048501 cHandles: 0x2
11400 17:17:50.049043 rHandle: 0
11401 17:17:50.051619 V: 0
11402 17:17:50.052090 Res: 0x0
11403 17:17:50.054605 TPM2_CC_GetSessionAuditDigest:
11404 17:17:50.057881 value: 0x600014D
11405 17:17:50.058307 commandIndex: 0x14d
11406 17:17:50.061639 reserved1: 0x0
11407 17:17:50.062219 nv: 0
11408 17:17:50.064975 extensive: 0
11409 17:17:50.065512 flushed: 0
11410 17:17:50.068032 cHandles: 0x3
11411 17:17:50.068461 rHandle: 0
11412 17:17:50.071331 V: 0
11413 17:17:50.074858 Res: 0x0
11414 17:17:50.075424 TPM2_CC_NV_Read:
11415 17:17:50.078002 value: 0x400014E
11416 17:17:50.078535 commandIndex: 0x14e
11417 17:17:50.081530 reserved1: 0x0
11418 17:17:50.081960 nv: 0
11419 17:17:50.084574 extensive: 0
11420 17:17:50.085048 flushed: 0
11421 17:17:50.087615 cHandles: 0x2
11422 17:17:50.088045 rHandle: 0
11423 17:17:50.091549 V: 0
11424 17:17:50.092083 Res: 0x0
11425 17:17:50.094493 TPM2_CC_NV_ReadLock:
11426 17:17:50.094950 value: 0x400014F
11427 17:17:50.097736 commandIndex: 0x14f
11428 17:17:50.098277 reserved1: 0x0
11429 17:17:50.100903
11430 17:17:50.101335 nv: 0
11431 17:17:50.101673 extensive: 0
11432 17:17:50.104672
11433 17:17:50.105104 flushed: 0
11434 17:17:50.108004 cHandles: 0x2
11435 17:17:50.108538 rHandle: 0
11436 17:17:50.111181 V: 0
11437 17:17:50.111715 Res: 0x0
11438 17:17:50.114472 TPM2_CC_ObjectChangeAuth:
11439 17:17:50.115035 value: 0x4000150
11440 17:17:50.117717 commandIndex: 0x150
11441 17:17:50.118179 reserved1: 0x0
11442 17:17:50.120952
11443 17:17:50.121383 nv: 0
11444 17:17:50.121723 extensive: 0
11445 17:17:50.124066
11446 17:17:50.124589 flushed: 0
11447 17:17:50.127985 cHandles: 0x2
11448 17:17:50.128541 rHandle: 0
11449 17:17:50.131121 V: 0
11450 17:17:50.131643 Res: 0x0
11451 17:17:50.134501 TPM2_CC_PolicySecret:
11452 17:17:50.135079 value: 0x4000151
11453 17:17:50.137689 commandIndex: 0x151
11454 17:17:50.138260 reserved1: 0x0
11455 17:17:50.140607 nv: 0
11456 17:17:50.141032 extensive: 0
11457 17:17:50.144018 flushed: 0
11458 17:17:50.144630 cHandles: 0x2
11459 17:17:50.147854 rHandle: 0
11460 17:17:50.148518 V: 0
11461 17:17:50.150755 Res: 0x0
11462 17:17:50.151227 TPM2_CC_Create:
11463 17:17:50.154053 value: 0x2000153
11464 17:17:50.157103 commandIndex: 0x153
11465 17:17:50.157536 reserved1: 0x0
11466 17:17:50.160517 nv: 0
11467 17:17:50.160970 extensive: 0
11468 17:17:50.163713 flushed: 0
11469 17:17:50.164142 cHandles: 0x1
11470 17:17:50.167484 rHandle: 0
11471 17:17:50.167913 V: 0
11472 17:17:50.170580 Res: 0x0
11473 17:17:50.171042 TPM2_CC_ECDH_ZGen:
11474 17:17:50.174087 value: 0x2000154
11475 17:17:50.174617 commandIndex: 0x154
11476 17:17:50.177406 reserved1: 0x0
11477 17:17:50.177941 nv: 0
11478 17:17:50.180285 extensive: 0
11479 17:17:50.180715 flushed: 0
11480 17:17:50.183522 cHandles: 0x1
11481 17:17:50.184054 rHandle: 0
11482 17:17:50.187145 V: 0
11483 17:17:50.190273 Res: 0x0
11484 17:17:50.190867 TPM2_CC_HMAC:
11485 17:17:50.191253 value: 0x2000155
11486 17:17:50.193868 commandIndex: 0x155
11487 17:17:50.196705 reserved1: 0x0
11488 17:17:50.197135 nv: 0
11489 17:17:50.199959 extensive: 0
11490 17:17:50.200390 flushed: 0
11491 17:17:50.203633 cHandles: 0x1
11492 17:17:50.204063 rHandle: 0
11493 17:17:50.206867 V: 0
11494 17:17:50.207330 Res: 0x0
11495 17:17:50.210302 TPM2_CC_Import:
11496 17:17:50.210839 value: 0x2000156
11497 17:17:50.213390 commandIndex: 0x156
11498 17:17:50.213919 reserved1: 0x0
11499 17:17:50.216417 nv: 0
11500 17:17:50.216881 extensive: 0
11501 17:17:50.220279 flushed: 0
11502 17:17:50.220735 cHandles: 0x1
11503 17:17:50.223094 rHandle: 0
11504 17:17:50.223520 V: 0
11505 17:17:50.226282 Res: 0x0
11506 17:17:50.226712 TPM2_CC_Load:
11507 17:17:50.230253 value: 0x12000157
11508 17:17:50.230832 commandIndex: 0x157
11509 17:17:50.233303 reserved1: 0x0
11510 17:17:50.236604 nv: 0
11511 17:17:50.237136 extensive: 0
11512 17:17:50.239748 flushed: 0
11513 17:17:50.240280 cHandles: 0x1
11514 17:17:50.243103 rHandle: 1
11515 17:17:50.243635 V: 0
11516 17:17:50.246720 Res: 0x0
11517 17:17:50.247432 TPM2_CC_Quote:
11518 17:17:50.250004 value: 0x2000158
11519 17:17:50.250669 commandIndex: 0x158
11520 17:17:50.252912 reserved1: 0x0
11521 17:17:50.253343 nv: 0
11522 17:17:50.256110 extensive: 0
11523 17:17:50.256539 flushed: 0
11524 17:17:50.259181 cHandles: 0x1
11525 17:17:50.259619 rHandle: 0
11526 17:17:50.262958 V: 0
11527 17:17:50.263390 Res: 0x0
11528 17:17:50.266250 TPM2_CC_RSA_Decrypt:
11529 17:17:50.266678 value: 0x2000159
11530 17:17:50.269463 commandIndex: 0x159
11531 17:17:50.272961 reserved1: 0x0
11532 17:17:50.273494 nv: 0
11533 17:17:50.276099 extensive: 0
11534 17:17:50.276640 flushed: 0
11535 17:17:50.278985 cHandles: 0x1
11536 17:17:50.279419 rHandle: 0
11537 17:17:50.282788 V: 0
11538 17:17:50.283249 Res: 0x0
11539 17:17:50.285962 TPM2_CC_HMAC_Start:
11540 17:17:50.286395 value: 0x1200015B
11541 17:17:50.289042 commandIndex: 0x15b
11542 17:17:50.289473 reserved1: 0x0
11543 17:17:50.292816 nv: 0
11544 17:17:50.293243 extensive: 0
11545 17:17:50.295965 flushed: 0
11546 17:17:50.298944 cHandles: 0x1
11547 17:17:50.299378 rHandle: 1
11548 17:17:50.302221 V: 0
11549 17:17:50.302649 Res: 0x0
11550 17:17:50.305503 TPM2_CC_SequenceUpdate:
11551 17:17:50.305933 value: 0x200015C
11552 17:17:50.309601 commandIndex: 0x15c
11553 17:17:50.310140 reserved1: 0x0
11554 17:17:50.312497 nv: 0
11555 17:17:50.312952 extensive: 0
11556 17:17:50.315757 flushed: 0
11557 17:17:50.316287 cHandles: 0x1
11558 17:17:50.318836 rHandle: 0
11559 17:17:50.319294 V: 0
11560 17:17:50.322030 Res: 0x0
11561 17:17:50.322459 TPM2_CC_Sign:
11562 17:17:50.325658 value: 0x200015D
11563 17:17:50.328835 commandIndex: 0x15d
11564 17:17:50.329262 reserved1: 0x0
11565 17:17:50.332121 nv: 0
11566 17:17:50.332650 extensive: 0
11567 17:17:50.335710 flushed: 0
11568 17:17:50.336145 cHandles: 0x1
11569 17:17:50.339034 rHandle: 0
11570 17:17:50.339560 V: 0
11571 17:17:50.342409 Res: 0x0
11572 17:17:50.342981 TPM2_CC_Unseal:
11573 17:17:50.345541 value: 0x200015E
11574 17:17:50.346078 commandIndex: 0x15e
11575 17:17:50.348380 reserved1: 0x0
11576 17:17:50.348809 nv: 0
11577 17:17:50.352509 extensive: 0
11578 17:17:50.353109 flushed: 0
11579 17:17:50.354992 cHandles: 0x1
11580 17:17:50.355449 rHandle: 0
11581 17:17:50.358293 V: 0
11582 17:17:50.358718 Res: 0x0
11583 17:17:50.362420 TPM2_CC_PolicySigned:
11584 17:17:50.365438 value: 0x4000160
11585 17:17:50.365968 commandIndex: 0x160
11586 17:17:50.368587 reserved1: 0x0
11587 17:17:50.369014 nv: 0
11588 17:17:50.371486 extensive: 0
11589 17:17:50.371915 flushed: 0
11590 17:17:50.375471 cHandles: 0x2
11591 17:17:50.376004 rHandle: 0
11592 17:17:50.378497 V: 0
11593 17:17:50.378951 Res: 0x0
11594 17:17:50.381899 TPM2_CC_ContextLoad:
11595 17:17:50.382328 value: 0x10000161
11596 17:17:50.384860 commandIndex: 0x161
11597 17:17:50.388102 reserved1: 0x0
11598 17:17:50.388529 nv: 0
11599 17:17:50.391580 extensive: 0
11600 17:17:50.392010 flushed: 0
11601 17:17:50.394621 cHandles: 0x0
11602 17:17:50.395071 rHandle: 1
11603 17:17:50.398477 V: 0
11604 17:17:50.399021 Res: 0x0
11605 17:17:50.401354 TPM2_CC_ContextSave:
11606 17:17:50.401791 value: 0x2000162
11607 17:17:50.404636 commandIndex: 0x162
11608 17:17:50.405064 reserved1: 0x0
11609 17:17:50.407783 nv: 0
11610 17:17:50.408214 extensive: 0
11611 17:17:50.411054 flushed: 0
11612 17:17:50.415257 cHandles: 0x1
11613 17:17:50.415812 rHandle: 0
11614 17:17:50.418104 V: 0
11615 17:17:50.418577 Res: 0x0
11616 17:17:50.421348 TPM2_CC_ECDH_KeyGen:
11617 17:17:50.421776 value: 0x2000163
11618 17:17:50.424506 commandIndex: 0x163
11619 17:17:50.424933 reserved1: 0x0
11620 17:17:50.428130 nv: 0
11621 17:17:50.428558 extensive: 0
11622 17:17:50.431205 flushed: 0
11623 17:17:50.431633 cHandles: 0x1
11624 17:17:50.434430 rHandle: 0
11625 17:17:50.434857 V: 0
11626 17:17:50.437659 Res: 0x0
11627 17:17:50.441306 TPM2_CC_FlushContext:
11628 17:17:50.441740 value: 0x165
11629 17:17:50.444053 commandIndex: 0x165
11630 17:17:50.444482 reserved1: 0x0
11631 17:17:50.447807 nv: 0
11632 17:17:50.448299 extensive: 0
11633 17:17:50.451086 flushed: 0
11634 17:17:50.451513 cHandles: 0x0
11635 17:17:50.454176 rHandle: 0
11636 17:17:50.454604 V: 0
11637 17:17:50.457226 Res: 0x0
11638 17:17:50.457676 TPM2_CC_LoadExternal:
11639 17:17:50.461053 value: 0x10000167
11640 17:17:50.461481 commandIndex: 0x167
11641 17:17:50.464099
11642 17:17:50.464557 reserved1: 0x0
11643 17:17:50.467206 nv: 0
11644 17:17:50.467635 extensive: 0
11645 17:17:50.470423 flushed: 0
11646 17:17:50.470869 cHandles: 0x0
11647 17:17:50.473712 rHandle: 1
11648 17:17:50.474136 V: 0
11649 17:17:50.477415 Res: 0x0
11650 17:17:50.477844 TPM2_CC_MakeCredential:
11651 17:17:50.480745 value: 0x2000168
11652 17:17:50.481174 commandIndex: 0x168
11653 17:17:50.484261 reserved1: 0x0
11654 17:17:50.484794 nv: 0
11655 17:17:50.486956
11656 17:17:50.487421 extensive: 0
11657 17:17:50.487787 flushed: 0
11658 17:17:50.490131
11659 17:17:50.490560 cHandles: 0x1
11660 17:17:50.493823 rHandle: 0
11661 17:17:50.494254 V: 0
11662 17:17:50.497008 Res: 0x0
11663 17:17:50.497538 TPM2_CC_NV_ReadPublic:
11664 17:17:50.500537 value: 0x2000169
11665 17:17:50.500967 commandIndex: 0x169
11666 17:17:50.503494 reserved1: 0x0
11667 17:17:50.503922 nv: 0
11668 17:17:50.506597 extensive: 0
11669 17:17:50.507064 flushed: 0
11670 17:17:50.509867 cHandles: 0x1
11671 17:17:50.510298 rHandle: 0
11672 17:17:50.513648 V: 0
11673 17:17:50.516921 Res: 0x0
11674 17:17:50.517376 TPM2_CC_PolicyAuthorize:
11675 17:17:50.519994 value: 0x200016A
11676 17:17:50.520539 commandIndex: 0x16a
11677 17:17:50.523322 reserved1: 0x0
11678 17:17:50.523776 nv: 0
11679 17:17:50.526510 extensive: 0
11680 17:17:50.527078 flushed: 0
11681 17:17:50.530100 cHandles: 0x1
11682 17:17:50.530555 rHandle: 0
11683 17:17:50.533332 V: 0
11684 17:17:50.533762 Res: 0x0
11685 17:17:50.536545
11686 17:17:50.536976 TPM2_CC_PolicyAuthValue:
11687 17:17:50.539918 value: 0x200016B
11688 17:17:50.540565 commandIndex: 0x16b
11689 17:17:50.543715 reserved1: 0x0
11690 17:17:50.544243 nv: 0
11691 17:17:50.546250 extensive: 0
11692 17:17:50.546681 flushed: 0
11693 17:17:50.550298 cHandles: 0x1
11694 17:17:50.550944 rHandle: 0
11695 17:17:50.553176 V: 0
11696 17:17:50.553604 Res: 0x0
11697 17:17:50.556315 TPM2_CC_PolicyCommandCode:
11698 17:17:50.559411 value: 0x200016C
11699 17:17:50.559843 commandIndex: 0x16c
11700 17:17:50.563278 reserved1: 0x0
11701 17:17:50.563707 nv: 0
11702 17:17:50.566755 extensive: 0
11703 17:17:50.567428 flushed: 0
11704 17:17:50.569552 cHandles: 0x1
11705 17:17:50.569979 rHandle: 0
11706 17:17:50.572611 V: 0
11707 17:17:50.573043 Res: 0x0
11708 17:17:50.576658
11709 17:17:50.577194 TPM2_CC_PolicyCounterTimer:
11710 17:17:50.579253 value: 0x200016D
11711 17:17:50.579687 commandIndex: 0x16d
11712 17:17:50.583080 reserved1: 0x0
11713 17:17:50.583615 nv: 0
11714 17:17:50.586100 extensive: 0
11715 17:17:50.586537 flushed: 0
11716 17:17:50.589238 cHandles: 0x1
11717 17:17:50.589668 rHandle: 0
11718 17:17:50.592483
11719 17:17:50.592914 V: 0
11720 17:17:50.596023 Res: 0x0
11721 17:17:50.596450 TPM2_CC_PolicyCpHash:
11722 17:17:50.599128 value: 0x200016E
11723 17:17:50.599558 commandIndex: 0x16e
11724 17:17:50.602379 reserved1: 0x0
11725 17:17:50.602824 nv: 0
11726 17:17:50.605941 extensive: 0
11727 17:17:50.606380 flushed: 0
11728 17:17:50.609285 cHandles: 0x1
11729 17:17:50.609725 rHandle: 0
11730 17:17:50.612389 V: 0
11731 17:17:50.612832 Res: 0x0
11732 17:17:50.615510 TPM2_CC_PolicyLocality:
11733 17:17:50.619127 value: 0x200016F
11734 17:17:50.619566 commandIndex: 0x16f
11735 17:17:50.622339 reserved1: 0x0
11736 17:17:50.622727 nv: 0
11737 17:17:50.625529 extensive: 0
11738 17:17:50.625907 flushed: 0
11739 17:17:50.628701 cHandles: 0x1
11740 17:17:50.629138 rHandle: 0
11741 17:17:50.632364 V: 0
11742 17:17:50.632803 Res: 0x0
11743 17:17:50.635441 TPM2_CC_PolicyNameHash:
11744 17:17:50.638756 value: 0x2000170
11745 17:17:50.639341 commandIndex: 0x170
11746 17:17:50.642364 reserved1: 0x0
11747 17:17:50.642867 nv: 0
11748 17:17:50.645419 extensive: 0
11749 17:17:50.645902 flushed: 0
11750 17:17:50.648641 cHandles: 0x1
11751 17:17:50.649080 rHandle: 0
11752 17:17:50.651678 V: 0
11753 17:17:50.652137 Res: 0x0
11754 17:17:50.654992 TPM2_CC_PolicyOR:
11755 17:17:50.655523 value: 0x2000171
11756 17:17:50.658619 commandIndex: 0x171
11757 17:17:50.661847 reserved1: 0x0
11758 17:17:50.662283 nv: 0
11759 17:17:50.664952 extensive: 0
11760 17:17:50.665391 flushed: 0
11761 17:17:50.668978 cHandles: 0x1
11762 17:17:50.669534 rHandle: 0
11763 17:17:50.671774 V: 0
11764 17:17:50.672211 Res: 0x0
11765 17:17:50.675036 TPM2_CC_PolicyTicket:
11766 17:17:50.675477 value: 0x2000172
11767 17:17:50.678085 commandIndex: 0x172
11768 17:17:50.678520 reserved1: 0x0
11769 17:17:50.682166 nv: 0
11770 17:17:50.682701 extensive: 0
11771 17:17:50.685464 flushed: 0
11772 17:17:50.686000 cHandles: 0x1
11773 17:17:50.688395 rHandle: 0
11774 17:17:50.688869 V: 0
11775 17:17:50.691738 Res: 0x0
11776 17:17:50.694728 TPM2_CC_ReadPublic:
11777 17:17:50.695196 value: 0x2000173
11778 17:17:50.697952 commandIndex: 0x173
11779 17:17:50.698376 reserved1: 0x0
11780 17:17:50.701595 nv: 0
11781 17:17:50.702019 extensive: 0
11782 17:17:50.704812 flushed: 0
11783 17:17:50.705237 cHandles: 0x1
11784 17:17:50.707635 rHandle: 0
11785 17:17:50.708058 V: 0
11786 17:17:50.711563 Res: 0x0
11787 17:17:50.711987 TPM2_CC_RSA_Encrypt:
11788 17:17:50.714413 value: 0x2000174
11789 17:17:50.717692 commandIndex: 0x174
11790 17:17:50.717774 reserved1: 0x0
11791 17:17:50.721242 nv: 0
11792 17:17:50.721663 extensive: 0
11793 17:17:50.724401 flushed: 0
11794 17:17:50.724824 cHandles: 0x1
11795 17:17:50.727729 rHandle: 0
11796 17:17:50.728149 V: 0
11797 17:17:50.730768 Res: 0x0
11798 17:17:50.731241 TPM2_CC_StartAuthSession:
11799 17:17:50.734410 value: 0x14000176
11800 17:17:50.737664 commandIndex: 0x176
11801 17:17:50.738106 reserved1: 0x0
11802 17:17:50.740661 nv: 0
11803 17:17:50.741081 extensive: 0
11804 17:17:50.744604 flushed: 0
11805 17:17:50.745147 cHandles: 0x2
11806 17:17:50.747626 rHandle: 1
11807 17:17:50.748173 V: 0
11808 17:17:50.750735 Res: 0x0
11809 17:17:50.751187 TPM2_CC_VerifySignature:
11810 17:17:50.753995 value: 0x2000177
11811 17:17:50.757318 commandIndex: 0x177
11812 17:17:50.757805 reserved1: 0x0
11813 17:17:50.760378 nv: 0
11814 17:17:50.760832 extensive: 0
11815 17:17:50.764143 flushed: 0
11816 17:17:50.764562 cHandles: 0x1
11817 17:17:50.767393 rHandle: 0
11818 17:17:50.767887 V: 0
11819 17:17:50.770632 Res: 0x0
11820 17:17:50.771077 TPM2_CC_ECC_Parameters:
11821 17:17:50.773904 value: 0x178
11822 17:17:50.774325 commandIndex: 0x178
11823 17:17:50.777339 reserved1: 0x0
11824 17:17:50.777876 nv: 0
11825 17:17:50.780880 extensive: 0
11826 17:17:50.781314 flushed: 0
11827 17:17:50.784020 cHandles: 0x0
11828 17:17:50.787302 rHandle: 0
11829 17:17:50.787720 V: 0
11830 17:17:50.790557 Res: 0x0
11831 17:17:50.791002 TPM2_CC_GetCapability:
11832 17:17:50.793800 value: 0x17A
11833 17:17:50.794216 commandIndex: 0x17a
11834 17:17:50.796930 reserved1: 0x0
11835 17:17:50.797370 nv: 0
11836 17:17:50.800026 extensive: 0
11837 17:17:50.800445 flushed: 0
11838 17:17:50.803800 cHandles: 0x0
11839 17:17:50.804290 rHandle: 0
11840 17:17:50.806915 V: 0
11841 17:17:50.807340 Res: 0x0
11842 17:17:50.810041 TPM2_CC_GetRandom:
11843 17:17:50.810462 value: 0x17B
11844 17:17:50.813801 commandIndex: 0x17b
11845 17:17:50.814337 reserved1: 0x0
11846 17:17:50.816828
11847 17:17:50.817249 nv: 0
11848 17:17:50.817575 extensive: 0
11849 17:17:50.820140
11850 17:17:50.820560 flushed: 0
11851 17:17:50.823713 cHandles: 0x0
11852 17:17:50.824132 rHandle: 0
11853 17:17:50.826868 V: 0
11854 17:17:50.827316 Res: 0x0
11855 17:17:50.830085 TPM2_CC_GetTestResult:
11856 17:17:50.830503 value: 0x17C
11857 17:17:50.833086 commandIndex: 0x17c
11858 17:17:50.833581 reserved1: 0x0
11859 17:17:50.836720 nv: 0
11860 17:17:50.837185 extensive: 0
11861 17:17:50.839784 flushed: 0
11862 17:17:50.840205 cHandles: 0x0
11863 17:17:50.843016 rHandle: 0
11864 17:17:50.843436 V: 0
11865 17:17:50.846212 Res: 0x0
11866 17:17:50.846628 TPM2_CC_Hash:
11867 17:17:50.849927 value: 0x17D
11868 17:17:50.850342 commandIndex: 0x17d
11869 17:17:50.853098 reserved1: 0x0
11870 17:17:50.853517 nv: 0
11871 17:17:50.856223 extensive: 0
11872 17:17:50.856641 flushed: 0
11873 17:17:50.859497 cHandles: 0x0
11874 17:17:50.859953 rHandle: 0
11875 17:17:50.862991 V: 0
11876 17:17:50.863409 Res: 0x0
11877 17:17:50.866478
11878 17:17:50.866926 TPM2_CC_PCR_Read:
11879 17:17:50.867273 value: 0x17E
11880 17:17:50.869380 commandIndex: 0x17e
11881 17:17:50.873135 reserved1: 0x0
11882 17:17:50.873554 nv: 0
11883 17:17:50.876190 extensive: 0
11884 17:17:50.876611 flushed: 0
11885 17:17:50.879432 cHandles: 0x0
11886 17:17:50.879880 rHandle: 0
11887 17:17:50.882532 V: 0
11888 17:17:50.882976 Res: 0x0
11889 17:17:50.886339 TPM2_CC_PolicyPCR:
11890 17:17:50.886759 value: 0x200017F
11891 17:17:50.889444 commandIndex: 0x17f
11892 17:17:50.889861 reserved1: 0x0
11893 17:17:50.892613 nv: 0
11894 17:17:50.893034 extensive: 0
11895 17:17:50.895812 flushed: 0
11896 17:17:50.896229 cHandles: 0x1
11897 17:17:50.899066 rHandle: 0
11898 17:17:50.899491 V: 0
11899 17:17:50.902665 Res: 0x0
11900 17:17:50.905955 TPM2_CC_PolicyRestart:
11901 17:17:50.906542 value: 0x2000180
11902 17:17:50.909087 commandIndex: 0x180
11903 17:17:50.909508 reserved1: 0x0
11904 17:17:50.912116 nv: 0
11905 17:17:50.912542 extensive: 0
11906 17:17:50.915884 flushed: 0
11907 17:17:50.916269 cHandles: 0x1
11908 17:17:50.919059 rHandle: 0
11909 17:17:50.919483 V: 0
11910 17:17:50.922195 Res: 0x0
11911 17:17:50.922624 TPM2_CC_ReadClock:
11912 17:17:50.925430 value: 0x181
11913 17:17:50.925850 commandIndex: 0x181
11914 17:17:50.928611 reserved1: 0x0
11915 17:17:50.932476 nv: 0
11916 17:17:50.932897 extensive: 0
11917 17:17:50.935542 flushed: 0
11918 17:17:50.935987 cHandles: 0x0
11919 17:17:50.938672 rHandle: 0
11920 17:17:50.939121 V: 0
11921 17:17:50.942196 Res: 0x0
11922 17:17:50.942660 TPM2_CC_PCR_Extend:
11923 17:17:50.945482 value: 0x2400182
11924 17:17:50.945960 commandIndex: 0x182
11925 17:17:50.948598 reserved1: 0x0
11926 17:17:50.949023 nv: 1
11927 17:17:50.951946 extensive: 0
11928 17:17:50.952370 flushed: 0
11929 17:17:50.955635 cHandles: 0x1
11930 17:17:50.956060 rHandle: 0
11931 17:17:50.958389 V: 0
11932 17:17:50.958987 Res: 0x0
11933 17:17:50.962117 TPM2_CC_NV_Certify:
11934 17:17:50.965341 value: 0x6000184
11935 17:17:50.965765 commandIndex: 0x184
11936 17:17:50.968332 reserved1: 0x0
11937 17:17:50.968754 nv: 0
11938 17:17:50.972242 extensive: 0
11939 17:17:50.972673 flushed: 0
11940 17:17:50.975290 cHandles: 0x3
11941 17:17:50.975713 rHandle: 0
11942 17:17:50.978526 V: 0
11943 17:17:50.978994 Res: 0x0
11944 17:17:50.981630 TPM2_CC_EventSequenceComplete:
11945 17:17:50.985086 value: 0x5400185
11946 17:17:50.985625 commandIndex: 0x185
11947 17:17:50.988064 reserved1: 0x0
11948 17:17:50.988487 nv: 1
11949 17:17:50.991837 extensive: 0
11950 17:17:50.992261 flushed: 1
11951 17:17:50.995047 cHandles: 0x2
11952 17:17:50.995473 rHandle: 0
11953 17:17:50.998581 V: 0
11954 17:17:50.999137 Res: 0x0
11955 17:17:51.001424 TPM2_CC_HashSequenceStart:
11956 17:17:51.004646 value: 0x10000186
11957 17:17:51.005074 commandIndex: 0x186
11958 17:17:51.008328 reserved1: 0x0
11959 17:17:51.008753 nv: 0
11960 17:17:51.011520 extensive: 0
11961 17:17:51.011945 flushed: 0
11962 17:17:51.014618 cHandles: 0x0
11963 17:17:51.015079 rHandle: 1
11964 17:17:51.017843 V: 0
11965 17:17:51.018269 Res: 0x0
11966 17:17:51.021395
11967 17:17:51.021820 TPM2_CC_PolicyDuplicationSelect:
11968 17:17:51.024620 value: 0x2000188
11969 17:17:51.027835 commandIndex: 0x188
11970 17:17:51.028352 reserved1: 0x0
11971 17:17:51.031178 nv: 0
11972 17:17:51.031601 extensive: 0
11973 17:17:51.034273 flushed: 0
11974 17:17:51.034696 cHandles: 0x1
11975 17:17:51.038242 rHandle: 0
11976 17:17:51.038767 V: 0
11977 17:17:51.041211 Res: 0x0
11978 17:17:51.041634 TPM2_CC_PolicyGetDigest:
11979 17:17:51.051099 value: 0x200<8>[ 18.890732] <LAVA_SIGNAL_TESTCASE TEST_CASE_ID=tpm-chip-is-online RESULT=pass>
11980 17:17:51.051530 0189
11981 17:17:51.052213 Received signal: <TESTCASE> TEST_CASE_ID=tpm-chip-is-online RESULT=pass
11983 17:17:51.054295 commandIndex: 0x189
11984 17:17:51.054720 reserved1: 0x0
11985 17:17:51.057447 nv: 0
11986 17:17:51.057955 extensive: 0
11987 17:17:51.060496 flushed: 0
11988 17:17:51.067514 cHa<8>[ 18.907933] <LAVA_SIGNAL_ENDRUN 1_bootrr 8082969_1.5.2.3.5>
11989 17:17:51.067960 ndles: 0x1
11990 17:17:51.068534 Received signal: <ENDRUN> 1_bootrr 8082969_1.5.2.3.5
11991 17:17:51.068895 Ending use of test pattern.
11992 17:17:51.069204 Ending test lava.1_bootrr (8082969_1.5.2.3.5), duration 2.77
11994 17:17:51.070779 rHandle: 0
11995 17:17:51.071166 V: 0
11996 17:17:51.073907 Res: 0x0
11997 17:17:51.074357 TPM2_CC_TestParms:
11998 17:17:51.077027 value: 0x18A
11999 17:17:51.077443 commandIndex: 0x18a
12000 17:17:51.080829 reserved1: 0x0
12001 17:17:51.081248 nv: 0
12002 17:17:51.084406 extensive: 0
12003 17:17:51.084959 flushed: 0
12004 17:17:51.087331 cHandles: 0x0
12005 17:17:51.087759 rHandle: 0
12006 17:17:51.090560 V: 0
12007 17:17:51.091001 Res: 0x0
12008 17:17:51.094145 TPM2_CC_Commit:
12009 17:17:51.094670 value: 0x200018B
12010 17:17:51.097355 commandIndex: 0x18b
12011 17:17:51.100419 reserved1: 0x0
12012 17:17:51.100840 nv: 0
12013 17:17:51.103534 extensive: 0
12014 17:17:51.103952 flushed: 0
12015 17:17:51.106754 cHandles: 0x1
12016 17:17:51.107321 rHandle: 0
12017 17:17:51.110608 V: 0
12018 17:17:51.111178 Res: 0x0
12019 17:17:51.113313 TPM2_CC_PolicyPassword:
12020 17:17:51.113731 value: 0x200018C
12021 17:17:51.117399 commandIndex: 0x18c
12022 17:17:51.120300 reserved1: 0x0
12023 17:17:51.120725 nv: 0
12024 17:17:51.123504 extensive: 0
12025 17:17:51.123927 flushed: 0
12026 17:17:51.126731 cHandles: 0x1
12027 17:17:51.127262 rHandle: 0
12028 17:17:51.129948 V: 0
12029 17:17:51.130475 Res: 0x0
12030 17:17:51.133951 TPM2_CC_PolicyNvWritten:
12031 17:17:51.134478 value: 0x200018F
12032 17:17:51.137026 commandIndex: 0x18f
12033 17:17:51.137551 reserved1: 0x0
12034 17:17:51.140048
12035 17:17:51.140542 nv: 0
12036 17:17:51.140907 extensive: 0
12037 17:17:51.143020
12038 17:17:51.143441 flushed: 0
12039 17:17:51.146555 cHandles: 0x1
12040 17:17:51.147130 rHandle: 0
12041 17:17:51.150289 V: 0
12042 17:17:51.150859 Res: 0x0
12043 17:17:51.151269 0x4008001:
12044 17:17:51.153333 value: 0x4008001
12045 17:17:51.156570 commandIndex: 0x8001
12046 17:17:51.156994 reserved1: 0x0
12047 17:17:51.159572 nv: 0
12048 17:17:51.159994 extensive: 0
12049 17:17:51.162755 flushed: 0
12050 17:17:51.163210 cHandles: 0x2
12051 17:17:51.166756 rHandle: 0
12052 17:17:51.167357 V: 0
12053 17:17:51.169584 Res: 0x0
12054 17:17:51.172861 /lava-8082969/1/../bin/lava-test-case
12055 17:17:51.173418 + set +x
12056 17:17:51.176024 <LAVA_TEST_RUNNER EXIT>
12057 17:17:51.176704 ok: lava_test_shell seems to have completed
12058 17:17:51.177297 all-cpus-are-online: pass
deferred-probe-empty: pass
tpm-chip-is-online: pass
12059 17:17:51.177735 end: 4.1 lava-test-shell (duration 00:00:03) [common]
12060 17:17:51.178168 end: 4 lava-test-retry (duration 00:00:03) [common]
12061 17:17:51.178594 start: 5 finalize (timeout 00:08:01) [common]
12062 17:17:51.179073 start: 5.1 power-off (timeout 00:00:30) [common]
12063 17:17:51.179797 Calling: 'nice' 'pduclient' '--daemon=localhost' '--hostname=mt8192-asurada-spherion-r0-cbg-2' '--port=1' '--command=off'
12064 17:17:51.238967 >> Command sent successfully.
12065 17:17:51.241494 Returned 0 in 0 seconds
12066 17:17:51.342705 end: 5.1 power-off (duration 00:00:00) [common]
12068 17:17:51.344313 start: 5.2 read-feedback (timeout 00:08:01) [common]
12069 17:17:51.345478 Listened to connection for namespace 'common' for up to 1s
12070 17:17:52.349900 Finalising connection for namespace 'common'
12071 17:17:52.350086 Disconnecting from shell: Finalise
12072 17:17:52.350189 / #
12073 17:17:52.450975 end: 5.2 read-feedback (duration 00:00:01) [common]
12074 17:17:52.451218 end: 5 finalize (duration 00:00:01) [common]
12075 17:17:52.451397 Cleaning after the job
12076 17:17:52.451540 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/ramdisk
12077 17:17:52.453408 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/kernel
12078 17:17:52.457130 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/dtb
12079 17:17:52.457311 Cleaning up download directory: /var/lib/lava/dispatcher/tmp/8082969/tftp-deploy-q1z0x9j0/modules
12080 17:17:52.461871 Override tmp directory removed at /var/lib/lava/dispatcher/tmp/8082969
12081 17:17:52.485416 Root tmp directory removed at /var/lib/lava/dispatcher/tmp/8082969
12082 17:17:52.485642 Job finished correctly